Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/56772/?format=api
{ "id": 56772, "url": "http://patches.dpdk.org/api/patches/56772/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190719123309.24417-6-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190719123309.24417-6-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190719123309.24417-6-rnagadheeraj@marvell.com", "date": "2019-07-19T12:33:38", "name": "[v2,05/10] crypto/nitrox: add software queue management functionality", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a35f09c164341a96ddd735469885e8f45a58737e", "submitter": { "id": 1365, "url": "http://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190719123309.24417-6-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 5622, "url": "http://patches.dpdk.org/api/series/5622/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5622", "date": "2019-07-19T12:33:30", "name": "add Nitrox crypto device support", "version": 2, "mbox": "http://patches.dpdk.org/series/5622/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56772/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56772/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0DEE31B99B;\n\tFri, 19 Jul 2019 14:33:57 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 91ACE5B3E\n\tfor <dev@dpdk.org>; Fri, 19 Jul 2019 14:33:42 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx6JCQVNN013480 for <dev@dpdk.org>; Fri, 19 Jul 2019 05:33:41 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2ts07vse5e-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 19 Jul 2019 05:33:41 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 19 Jul 2019 05:33:40 -0700", "from NAM03-BY2-obe.outbound.protection.outlook.com (104.47.42.56)\n\tby SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1367.3 via Frontend Transport; Fri, 19 Jul 2019 05:33:40 -0700", "from MN2PR18MB2797.namprd18.prod.outlook.com (20.179.22.16) by\n\tMN2PR18MB2527.namprd18.prod.outlook.com (20.179.82.202) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.2073.14; Fri, 19 Jul 2019 12:33:39 +0000", "from MN2PR18MB2797.namprd18.prod.outlook.com\n\t([fe80::5d53:ac2e:80ec:cd8f]) by\n\tMN2PR18MB2797.namprd18.prod.outlook.com\n\t([fe80::5d53:ac2e:80ec:cd8f%6]) with mapi id 15.20.2094.011;\n\tFri, 19 Jul 2019 12:33:39 +0000" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : references : in-reply-to : content-type\n\t: content-transfer-encoding : mime-version; s=pfpt0818;\n\tbh=rElaDV7XgYz09iodMjbR4M3X45a1tJ9mko/MkwJo/FI=;\n\tb=fBjlQIT5fdFBfF661ODU6gTYlOGqGa8MpYfk8gJco9RnwqtX0X1mZNLXWHVjSD5bRUbG\n\thIRC6OSteRd9krCW2cqCBRLa4lKGqcY4NeEP2B9TGBZPhcXFreQ4u62QT4rE/Gw4uWwI\n\toQcIeVp5bsvbvxHVHv1A+KJumlEYqVZKGueFYKYsjZXsEVYtKAT0M09J7Ap2HUP1gagU\n\tsVZclcuyL69TggabQ4tuCQjeEjDhhRUls9ZfW09PREVFQbU7yfdGXOIBoTnNgRqBMyFk\n\tWTkdWOrPwKfIhTpjZ4/556KVTDMmIuJCv6Nteq74Y3ZZgAFWn+SlyfSGjMB3DgQW7yWw\n\tjw== ", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=marvell.onmicrosoft.com; s=selector2-marvell-onmicrosoft-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=rElaDV7XgYz09iodMjbR4M3X45a1tJ9mko/MkwJo/FI=;\n\tb=V7/zy0KVPOLMj22O1XYrBL1ZUlVJEJLmVyzyp0vH2R3ImAerhLIw15Zgf7Up2lSskSnOCJ4LLz/55GKqLxKO/vpLWW6H4k/AwMKdaimPeIn9yMBgt9Szarn31P0wMKchOLa5rpvG3Fk4rRh7NBQsrmEqTi+vkh0jkibFUNCrBzc=" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n\tb=GuapL6BurIHi1yLRz9FOpA1PK+oGig5NplSNOR3fvq5dShTFH8vlk+RqqHjptqT7PuaeayAKBmFA/2C1PNVzVG/5Lc7SuxMaAwADDslAEm4M1YLLPnOLwjLpD0aSgb+5PPt6QdRvsKZ+6XSGGcVZCI2eF9Ra3/2jHsptVlYM5mHRM68zCUicFjtD2B2Z8XcqTnlgO8K9mIHrDK34uwPno4SjLmZkDygy701hGqQdjRnwrC6uEeqdlwjzBIbWzB0xqKvk2hvBgWA77O/JhvHvGokcvyBkk/pMMdqhLg8CI6kOqCcvv0s9bNxJDFdbeZO1PppGrucS8DUeL+9O5/Tsfw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n\ts=arcselector9901;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=rElaDV7XgYz09iodMjbR4M3X45a1tJ9mko/MkwJo/FI=;\n\tb=DI9Gj9lGC0heegp5BIjPB77qcKDMcZTaz2j3La1xGI6dsyM44CFm9PdCLPlxHbVBJ3wFkbJWwdRZuzsRg5FHB1k9yP6v3KGr2t1rghYcxHNu3I522bjlntKhjZqq1Y1N5hJa1a/+bZZVzvOGnI2SpstPgrwe7hm7MTombgApjG7407G54YDO/d01VtQv1XRNirvmJc1W7/xMNuRZpzitXU21PVif87Ym5PmfqtZBDdew4XcUd3TUwX94BYbdFv6zdMZTWYasNyWOfEqxe+M/IIvFgmdh366qvnrS8RgnSfba4lo23oRQSQTy05o+nQnX4Vx5PWZivPItSHGY1ZVZrQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1;spf=pass\n\tsmtp.mailfrom=marvell.com;dmarc=pass action=none\n\theader.from=marvell.com;dkim=pass header.d=marvell.com;arc=none", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "Srikanth Jampala <jsrikanth@marvell.com>, Nagadheeraj Rottela\n\t<rnagadheeraj@marvell.com>", "Thread-Topic": "[PATCH v2 05/10] crypto/nitrox: add software queue management\n\tfunctionality", "Thread-Index": "AQHVPi4wyohn1W4SN066JYWYrr3Rsg==", "Date": "Fri, 19 Jul 2019 12:33:38 +0000", "Message-ID": "<20190719123309.24417-6-rnagadheeraj@marvell.com>", "References": "<20190717052837.647-1-rnagadheeraj@marvell.com>\n\t<20190719123309.24417-1-rnagadheeraj@marvell.com>", "In-Reply-To": "<20190719123309.24417-1-rnagadheeraj@marvell.com>", "Accept-Language": "en-IN, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BM1PR0101CA0048.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:1a::34) To MN2PR18MB2797.namprd18.prod.outlook.com\n\t(2603:10b6:208:a0::16)", "x-ms-exchange-messagesentrepresentingtype": "1", "x-mailer": "git-send-email 2.13.6", "x-originating-ip": "[115.113.156.2]", "x-ms-publictraffictype": "Email", "x-ms-office365-filtering-correlation-id": "046446a1-604c-40f3-42ad-08d70c455361", "x-microsoft-antispam": "BCL:0; PCL:0;\n\tRULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(2017052603328)(7193020);\n\tSRVR:MN2PR18MB2527; ", "x-ms-traffictypediagnostic": "MN2PR18MB2527:", "x-microsoft-antispam-prvs": "<MN2PR18MB25277E4849843B77FCA10D84D6CB0@MN2PR18MB2527.namprd18.prod.outlook.com>", "x-ms-oob-tlc-oobclassifiers": "OLM:79;", "x-forefront-prvs": "01039C93E4", "x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(4636009)(136003)(346002)(39860400002)(396003)(366004)(376002)(199004)(189003)(2616005)(6486002)(107886003)(36756003)(486006)(5660300002)(316002)(99286004)(30864003)(6116002)(14454004)(102836004)(1076003)(476003)(86362001)(6916009)(6512007)(5640700003)(8936002)(76176011)(53936002)(186003)(26005)(54906003)(6436002)(2501003)(8676002)(81166006)(1730700003)(81156014)(478600001)(3846002)(66476007)(66446008)(64756008)(52116002)(25786009)(68736007)(50226002)(4326008)(2906002)(66946007)(71200400001)(446003)(71190400001)(11346002)(14444005)(66066001)(55236004)(2351001)(7736002)(6506007)(305945005)(66556008)(256004)(386003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2527;\n\tH:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "received-spf": "None (protection.outlook.com: marvell.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "x/trOR8QpgSC9s0GLATZq/GAom8bzPJLIcEYcT7Mcxng/+cr072TzrScRn2Gjx2XFFcRuNBKoawOLqt1iYWzxElCIgwFK8qSke61BWfpF+t2YBeDc1pWz6L328Ox4niz4qF/0PuiqkUqJK/n80UVr6kg4Fo/NoLw4CIPQL1MirA8C6kOOEvTaIIID4gbXFizU6oM1a1J3wZ7L1mAGPBQhsOj9xz8K+DX25BhdQY+5TOdaSWjuhHfjYi4ZaPV/DopS0w4IbhbPDmcu4o/pdp8YWQvW9V3ch18eWA1O8NINvrbSUgChfI+FtkII/Fkb0vaGNeFUXEDhlcJRWXw9Oa5Kn101eg/rgJVTjQLvzJH8JYTvYE31H7GDlL2JjMdlQ7GR1c2WNqVS2n6fa+AvZbGkmdawso9akYHz2lpBjH5ceI=", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "046446a1-604c-40f3-42ad-08d70c455361", "X-MS-Exchange-CrossTenant-originalarrivaltime": "19 Jul 2019 12:33:38.8713\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "rnagadheeraj@marvell.com", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2527", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:5.22.84,1.0.8\n\tdefinitions=2019-07-19_09:2019-07-19,2019-07-19 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 05/10] crypto/nitrox: add software queue\n\tmanagement functionality", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add software queue management code corresponding to queue pair setup\nand release functions.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/crypto/nitrox/Makefile | 2 +\n drivers/crypto/nitrox/meson.build | 2 +\n drivers/crypto/nitrox/nitrox_qp.c | 74 +++++++++++++++++\n drivers/crypto/nitrox/nitrox_qp.h | 40 +++++++++\n drivers/crypto/nitrox/nitrox_sym.c | 132 ++++++++++++++++++++++++++++--\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 56 +++++++++++++\n drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 13 +++\n 7 files changed, 312 insertions(+), 7 deletions(-)\n create mode 100644 drivers/crypto/nitrox/nitrox_qp.c\n create mode 100644 drivers/crypto/nitrox/nitrox_qp.h\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.h", "diff": "diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile\nindex dedb74a34..f56992770 100644\n--- a/drivers/crypto/nitrox/Makefile\n+++ b/drivers/crypto/nitrox/Makefile\n@@ -28,5 +28,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_reqmgr.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_qp.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build\nindex 7c565c5a4..03788366b 100644\n--- a/drivers/crypto/nitrox/meson.build\n+++ b/drivers/crypto/nitrox/meson.build\n@@ -14,4 +14,6 @@ sources = files(\n \t\t'nitrox_logs.c',\n \t\t'nitrox_sym.c',\n \t\t'nitrox_sym_capabilities.c',\n+\t\t'nitrox_sym_reqmgr.c',\n+\t\t'nitrox_qp.c'\n \t\t)\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.c b/drivers/crypto/nitrox/nitrox_qp.c\nnew file mode 100644\nindex 000000000..9673bb4f3\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_qp.c\n@@ -0,0 +1,74 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <rte_malloc.h>\n+\n+#include \"nitrox_qp.h\"\n+#include \"nitrox_hal.h\"\n+#include \"nitrox_logs.h\"\n+\n+#define MAX_CMD_QLEN 16384\n+\n+static int\n+nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)\n+{\n+\tsize_t ridq_size = qp->count * sizeof(*qp->ridq);\n+\n+\tqp->ridq = rte_zmalloc_socket(\"nitrox ridq\", ridq_size,\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t socket_id);\n+\tif (!qp->ridq) {\n+\t\tNITROX_LOG(ERR, \"Failed to create rid queue\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n+\t\tuint32_t nb_descriptors, uint8_t instr_size, int socket_id)\n+{\n+\tint err;\n+\tuint32_t count;\n+\n+\tRTE_SET_USED(bar_addr);\n+\tRTE_SET_USED(instr_size);\n+\tcount = rte_align32pow2(nb_descriptors);\n+\tif (count > MAX_CMD_QLEN) {\n+\t\tNITROX_LOG(ERR, \"%s: Number of descriptors too big %d,\"\n+\t\t\t \" greater than max queue length %d\\n\",\n+\t\t\t dev_name, count,\n+\t\t\t MAX_CMD_QLEN);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqp->count = count;\n+\tqp->head = qp->tail = 0;\n+\trte_atomic16_init(&qp->pending_count);\n+\terr = nitrox_setup_ridq(qp, socket_id);\n+\tif (err)\n+\t\tgoto ridq_err;\n+\n+\treturn 0;\n+\n+ridq_err:\n+\treturn err;\n+\n+}\n+\n+static void\n+nitrox_release_ridq(struct nitrox_qp *qp)\n+{\n+\trte_free(qp->ridq);\n+}\n+\n+int\n+nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr)\n+{\n+\tRTE_SET_USED(bar_addr);\n+\tnitrox_release_ridq(qp);\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h\nnew file mode 100644\nindex 000000000..cf0102ff9\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_qp.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_QP_H_\n+#define _NITROX_QP_H_\n+\n+#include <stdbool.h>\n+\n+#include <rte_io.h>\n+\n+struct nitrox_softreq;\n+\n+struct rid {\n+\tstruct nitrox_softreq *sr;\n+};\n+\n+struct nitrox_qp {\n+\tstruct rid *ridq;\n+\tuint32_t count;\n+\tuint32_t head;\n+\tuint32_t tail;\n+\tstruct rte_mempool *sr_mp;\n+\tstruct rte_cryptodev_stats stats;\n+\tuint16_t qno;\n+\trte_atomic16_t pending_count;\n+};\n+\n+static inline bool\n+nitrox_qp_is_empty(struct nitrox_qp *qp)\n+{\n+\treturn (rte_atomic16_read(&qp->pending_count) == 0);\n+}\n+\n+int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr,\n+\t\t const char *dev_name, uint32_t nb_descriptors,\n+\t\t uint8_t inst_size, int socket_id);\n+int nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr);\n+\n+#endif /* _NITROX_QP_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c\nindex c05042e54..05f089cae 100644\n--- a/drivers/crypto/nitrox/nitrox_sym.c\n+++ b/drivers/crypto/nitrox/nitrox_sym.c\n@@ -10,9 +10,12 @@\n #include \"nitrox_sym.h\"\n #include \"nitrox_device.h\"\n #include \"nitrox_sym_capabilities.h\"\n+#include \"nitrox_qp.h\"\n+#include \"nitrox_sym_reqmgr.h\"\n #include \"nitrox_logs.h\"\n \n #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox\n+#define NPS_PKT_IN_INSTR_SIZE 64\n \n struct nitrox_sym_device {\n \tstruct rte_cryptodev *cdev;\n@@ -78,12 +81,127 @@ nitrox_sym_dev_info_get(struct rte_cryptodev *cdev,\n \tinfo->sym.max_nb_sessions = 0;\n }\n \n+static void\n+nitrox_sym_dev_stats_get(struct rte_cryptodev *cdev,\n+\t\t\t struct rte_cryptodev_stats *stats)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];\n+\n+\t\tif (!qp)\n+\t\t\tcontinue;\n+\n+\t\tstats->enqueued_count += qp->stats.enqueued_count;\n+\t\tstats->dequeued_count += qp->stats.dequeued_count;\n+\t\tstats->enqueue_err_count += qp->stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp->stats.dequeue_err_count;\n+\t}\n+}\n+\n+static void\n+nitrox_sym_dev_stats_reset(struct rte_cryptodev *cdev)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];\n+\n+\t\tif (!qp)\n+\t\t\tcontinue;\n+\n+\t\tmemset(&qp->stats, 0, sizeof(qp->stats));\n+\t}\n+}\n+\n static int\n-nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)\n+nitrox_sym_dev_qp_setup(struct rte_cryptodev *cdev, uint16_t qp_id,\n+\t\t\tconst struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\tint socket_id)\n {\n-\tRTE_SET_USED(cdev);\n-\tRTE_SET_USED(qp_id);\n+\tstruct nitrox_sym_device *sym_dev = cdev->data->dev_private;\n+\tstruct nitrox_device *ndev = sym_dev->ndev;\n+\tstruct nitrox_qp *qp = NULL;\n+\tint err;\n+\n+\tNITROX_LOG(DEBUG, \"queue %d\\n\", qp_id);\n+\tif (qp_id >= ndev->nr_queues) {\n+\t\tNITROX_LOG(ERR, \"queue %u invalid, max queues supported %d\\n\",\n+\t\t\t qp_id, ndev->nr_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cdev->data->queue_pairs[qp_id]) {\n+\t\terr = nitrox_sym_dev_qp_release(cdev, qp_id);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\tqp = rte_zmalloc_socket(\"nitrox PMD qp\", sizeof(*qp),\n+\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (!qp) {\n+\t\tNITROX_LOG(ERR, \"Failed to allocate nitrox qp\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tqp->qno = qp_id;\n+\terr = nitrox_qp_setup(qp, ndev->bar_addr, cdev->data->name,\n+\t\t\t qp_conf->nb_descriptors, NPS_PKT_IN_INSTR_SIZE,\n+\t\t\t socket_id);\n+\tif (unlikely(err))\n+\t\tgoto qp_setup_err;\n+\n+\tqp->sr_mp = nitrox_sym_req_pool_create(cdev, qp->count, qp_id,\n+\t\t\t\t\t socket_id);\n+\tif (unlikely(!qp->sr_mp))\n+\t\tgoto req_pool_err;\n+\n+\tcdev->data->queue_pairs[qp_id] = qp;\n+\tNITROX_LOG(DEBUG, \"queue %d setup done\\n\", qp_id);\n \treturn 0;\n+\n+req_pool_err:\n+\tnitrox_qp_release(qp, ndev->bar_addr);\n+qp_setup_err:\n+\trte_free(qp);\n+\treturn err;\n+}\n+\n+static int\n+nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)\n+{\n+\tstruct nitrox_sym_device *sym_dev = cdev->data->dev_private;\n+\tstruct nitrox_device *ndev = sym_dev->ndev;\n+\tstruct nitrox_qp *qp;\n+\tint err;\n+\n+\tNITROX_LOG(DEBUG, \"queue %d\\n\", qp_id);\n+\tif (qp_id >= ndev->nr_queues) {\n+\t\tNITROX_LOG(ERR, \"queue %u invalid, max queues supported %d\\n\",\n+\t\t\t qp_id, ndev->nr_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqp = cdev->data->queue_pairs[qp_id];\n+\tif (!qp) {\n+\t\tNITROX_LOG(DEBUG, \"queue %u already freed\\n\", qp_id);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!nitrox_qp_is_empty(qp)) {\n+\t\tNITROX_LOG(ERR, \"queue %d not empty\\n\", qp_id);\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\tcdev->data->queue_pairs[qp_id] = NULL;\n+\terr = nitrox_qp_release(qp, ndev->bar_addr);\n+\tnitrox_sym_req_pool_free(qp->sr_mp);\n+\trte_free(qp);\n+\tNITROX_LOG(DEBUG, \"queue %d release done\\n\", qp_id);\n+\n+\treturn err;\n }\n \n static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n@@ -93,11 +211,11 @@ static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n \t.dev_close\t\t= nitrox_sym_dev_close,\n \t.dev_infos_get\t\t= nitrox_sym_dev_info_get,\n \n-\t.stats_get\t\t= NULL,\n-\t.stats_reset\t\t= NULL,\n+\t.stats_get\t\t= nitrox_sym_dev_stats_get,\n+\t.stats_reset\t\t= nitrox_sym_dev_stats_reset,\n \n-\t.queue_pair_setup\t= NULL,\n-\t.queue_pair_release = NULL,\n+\t.queue_pair_setup\t= nitrox_sym_dev_qp_setup,\n+\t.queue_pair_release = nitrox_sym_dev_qp_release,\n \n \t.sym_session_get_size = NULL,\n \t.sym_session_configure = NULL,\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nnew file mode 100644\nindex 000000000..42d67317c\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -0,0 +1,56 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_errno.h>\n+\n+#include \"nitrox_sym_reqmgr.h\"\n+#include \"nitrox_logs.h\"\n+\n+struct nitrox_softreq {\n+\trte_iova_t iova;\n+};\n+\n+static void\n+softreq_init(struct nitrox_softreq *sr, rte_iova_t iova)\n+{\n+\tmemset(sr, 0, sizeof(*sr));\n+\tsr->iova = iova;\n+}\n+\n+static void\n+req_pool_obj_init(__rte_unused struct rte_mempool *mp,\n+\t\t __rte_unused void *opaque, void *obj,\n+\t\t __rte_unused unsigned int obj_idx)\n+{\n+\tsoftreq_init(obj, rte_mempool_virt2iova(obj));\n+}\n+\n+struct rte_mempool *\n+nitrox_sym_req_pool_create(struct rte_cryptodev *cdev, uint32_t nobjs,\n+\t\t\t uint16_t qp_id, int socket_id)\n+{\n+\tchar softreq_pool_name[RTE_RING_NAMESIZE];\n+\tstruct rte_mempool *mp;\n+\n+\tsnprintf(softreq_pool_name, RTE_RING_NAMESIZE, \"%s_sr_%d\",\n+\t\t cdev->data->name, qp_id);\n+\tmp = rte_mempool_create(softreq_pool_name,\n+\t\t\t\tRTE_ALIGN_MUL_CEIL(nobjs, 64),\n+\t\t\t\tsizeof(struct nitrox_softreq),\n+\t\t\t\t64, 0, NULL, NULL, req_pool_obj_init, NULL,\n+\t\t\t\tsocket_id, 0);\n+\tif (unlikely(!mp))\n+\t\tNITROX_LOG(ERR, \"Failed to create req pool, qid %d, err %d\\n\",\n+\t\t\t qp_id, rte_errno);\n+\n+\treturn mp;\n+}\n+\n+void\n+nitrox_sym_req_pool_free(struct rte_mempool *mp)\n+{\n+\trte_mempool_free(mp);\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\nnew file mode 100644\nindex 000000000..5953c958c\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_SYM_REQMGR_H_\n+#define _NITROX_SYM_REQMGR_H_\n+\n+struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cdev,\n+\t\t\t\t\t uint32_t nobjs, uint16_t qp_id,\n+\t\t\t\t\t int socket_id);\n+void nitrox_sym_req_pool_free(struct rte_mempool *mp);\n+\n+#endif /* _NITROX_SYM_REQMGR_H_ */\n", "prefixes": [ "v2", "05/10" ] }