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GET /api/patches/56046/?format=api
{ "id": 56046, "url": "http://patches.dpdk.org/api/patches/56046/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190703165220.1068-1-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190703165220.1068-1-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190703165220.1068-1-pbhagavatula@marvell.com", "date": "2019-07-03T16:52:20", "name": "mempool/octeontx2: fix clang build failure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a2006376949927768454f933fb139428eedd86af", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190703165220.1068-1-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5319, "url": "http://patches.dpdk.org/api/series/5319/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5319", "date": "2019-07-03T16:52:20", "name": "mempool/octeontx2: fix clang build failure", "version": 1, "mbox": "http://patches.dpdk.org/series/5319/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56046/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/56046/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 734622956;\n\tWed, 3 Jul 2019 18:52:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D604228EE\n\tfor <dev@dpdk.org>; Wed, 3 Jul 2019 18:52:25 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx63Gnabl003943 for <dev@dpdk.org>; Wed, 3 Jul 2019 09:52:25 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tgrv19yhv-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Wed, 03 Jul 2019 09:52:24 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tWed, 3 Jul 2019 09:52:23 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Wed, 3 Jul 2019 09:52:23 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.31])\n\tby maili.marvell.com (Postfix) with ESMTP id 1320C3F703F;\n\tWed, 3 Jul 2019 09:52:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=zITpVEwVH3wL0SpzBtmeMPFzMTPpoQs106EPszNtYTI=; \n\tb=t9VynV1Z4bYy4hA0WWXXx/93uL71G+TZ7HKw2cDjP5bkNE4Q2IdhXZh7XsbMtpAtOVqk\n\tb1QgEQzdJtWeGZ/YCj2DvmKh8pyfaZwS/HuHrvFJbmIt7kdvO5cvUCDGhevNvxcuKRR/\n\tbmAbX3RiY8V4Eig2uFTyPvoqBsC07MgKT7V+0+Q1mrF1Bl/JVSyUsk+Y5KOaLcRikiMH\n\tzwVnEYckznIueasgGlNP1Cw8VIx895xVpvaUbzmuWutiURRDlkJcfwhKuQipwq9O0DnJ\n\t19DBKSFmlKIvfSJL4m4MtpgeUaS0MwuaF9WUpZIVNfr7/LwDm7YPHTMeshbFRK5gwAzB\n\tJg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Wed, 3 Jul 2019 22:22:20 +0530", "Message-ID": "<20190703165220.1068-1-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-07-03_04:, , signatures=0", "Subject": "[dpdk-dev] [PATCH] mempool/octeontx2: fix clang build failure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nThe ARMv8.1 CASP instruction works with even register pairs and since\nthere no register constraint in older versions of GCC/Clang, use\nexplicit register allocation to satisfy CASP requirements.\n\nFixs build issue with arm64-armv8a-linux-clang.\n\nFixes: ee338015e7a9 (\"mempool/octeontx2: add optimized dequeue operation for arm64\")\n\nReported-by: Gavin Hu <gavin.hu@arm.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n\nUpstreamed gcc fix:\nhttps://github.com/gcc-mirror/gcc/commit/a1bdb8f296aac911\n\n drivers/mempool/octeontx2/otx2_mempool_ops.c | 278 +++++++++----------\n 1 file changed, 127 insertions(+), 151 deletions(-)\n\n--\n2.22.0", "diff": "diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c\nindex 97146d1fe..e1764b030 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c\n@@ -54,233 +54,206 @@ npa_lf_aura_op_search_alloc(const int64_t wdata, int64_t * const addr,\n \treturn 0;\n }\n\n-/*\n- * Some versions of the compiler don't have support for __int128_t for\n- * CASP inline-asm. i.e. if the optimization level is reduced to -O0 the\n- * CASP restrictions aren't followed and the compiler might end up violation the\n- * CASP rules. Fix it by explicitly providing ((optimize(\"-O3\"))).\n- *\n- * Example:\n- * ccSPMGzq.s:1648: Error: reg pair must start from even reg at\n- * operand 1 - `casp x21,x22,x0,x1,[x19]'\n- */\n-static __attribute__((optimize(\"-O3\"))) __rte_noinline int __hot\n+static __rte_always_inline int\n npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,\n \t\t\t unsigned int n, void **obj_table)\n {\n-\tconst __uint128_t wdata128 = ((__uint128_t)wdata << 64) | wdata;\n+\tregister const uint64_t wdata64 __asm(\"x26\") = wdata;\n+\tregister const uint64_t wdata128 __asm(\"x27\") = wdata;\n \tuint64x2_t failed = vdupq_n_u64(~0);\n\n \tswitch (n) {\n \tcase 32:\n \t{\n-\t\t__uint128_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;\n-\t\t__uint128_t t10, t11;\n-\n \t\tasm volatile (\n \t\t\".cpu generic+lse\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t8], %H[t8], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t9], %H[t9], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t10], %H[t10], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t11], %H[t11], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d16, %[t0]\\n\"\n-\t\t\"fmov v16.D[1], %H[t0]\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d17, %[t1]\\n\"\n-\t\t\"fmov v17.D[1], %H[t1]\\n\"\n-\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d18, %[t2]\\n\"\n-\t\t\"fmov v18.D[1], %H[t2]\\n\"\n-\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d19, %[t3]\\n\"\n-\t\t\"fmov v19.D[1], %H[t3]\\n\"\n-\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x8, x9, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x10, x11, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x12, x13, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x14, x15, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x16, x17, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x18, x19, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x20, x21, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x22, x23, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d16, x0\\n\"\n+\t\t\"fmov v16.D[1], x1\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d17, x2\\n\"\n+\t\t\"fmov v17.D[1], x3\\n\"\n+\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d18, x4\\n\"\n+\t\t\"fmov v18.D[1], x5\\n\"\n+\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d19, x6\\n\"\n+\t\t\"fmov v19.D[1], x7\\n\"\n+\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, %[t4]\\n\"\n-\t\t\"fmov v20.D[1], %H[t4]\\n\"\n-\t\t\"fmov d21, %[t5]\\n\"\n-\t\t\"fmov v21.D[1], %H[t5]\\n\"\n-\t\t\"fmov d22, %[t6]\\n\"\n-\t\t\"fmov v22.D[1], %H[t6]\\n\"\n-\t\t\"fmov d23, %[t7]\\n\"\n-\t\t\"fmov v23.D[1], %H[t7]\\n\"\n+\t\t\"fmov d20, x8\\n\"\n+\t\t\"fmov v20.D[1], x9\\n\"\n+\t\t\"fmov d21, x10\\n\"\n+\t\t\"fmov v21.D[1], x11\\n\"\n+\t\t\"fmov d22, x12\\n\"\n+\t\t\"fmov v22.D[1], x13\\n\"\n+\t\t\"fmov d23, x14\\n\"\n+\t\t\"fmov v23.D[1], x15\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n \t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n \t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t\"fmov d16, %[t8]\\n\"\n-\t\t\"fmov v16.D[1], %H[t8]\\n\"\n-\t\t\"fmov d17, %[t9]\\n\"\n-\t\t\"fmov v17.D[1], %H[t9]\\n\"\n-\t\t\"fmov d18, %[t10]\\n\"\n-\t\t\"fmov v18.D[1], %H[t10]\\n\"\n-\t\t\"fmov d19, %[t11]\\n\"\n-\t\t\"fmov v19.D[1], %H[t11]\\n\"\n+\t\t\"fmov d16, x16\\n\"\n+\t\t\"fmov v16.D[1], x17\\n\"\n+\t\t\"fmov d17, x18\\n\"\n+\t\t\"fmov v17.D[1], x19\\n\"\n+\t\t\"fmov d18, x20\\n\"\n+\t\t\"fmov v18.D[1], x21\\n\"\n+\t\t\"fmov d19, x22\\n\"\n+\t\t\"fmov v19.D[1], x23\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, %[t0]\\n\"\n-\t\t\"fmov v20.D[1], %H[t0]\\n\"\n-\t\t\"fmov d21, %[t1]\\n\"\n-\t\t\"fmov v21.D[1], %H[t1]\\n\"\n-\t\t\"fmov d22, %[t2]\\n\"\n-\t\t\"fmov v22.D[1], %H[t2]\\n\"\n-\t\t\"fmov d23, %[t3]\\n\"\n-\t\t\"fmov v23.D[1], %H[t3]\\n\"\n+\t\t\"fmov d20, x0\\n\"\n+\t\t\"fmov v20.D[1], x1\\n\"\n+\t\t\"fmov d21, x2\\n\"\n+\t\t\"fmov v21.D[1], x3\\n\"\n+\t\t\"fmov d22, x4\\n\"\n+\t\t\"fmov v22.D[1], x5\\n\"\n+\t\t\"fmov d23, x6\\n\"\n+\t\t\"fmov v23.D[1], x7\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n \t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n \t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n-\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n-\t\t[t3] \"=&r\" (t3), [t4] \"=&r\" (t4), [t5] \"=&r\" (t5),\n-\t\t[t6] \"=&r\" (t6), [t7] \"=&r\" (t7), [t8] \"=&r\" (t8),\n-\t\t[t9] \"=&r\" (t9), [t10] \"=&r\" (t10), [t11] \"=&r\" (t11)\n-\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n-\t\t[loc] \"r\" (addr)\n-\t\t: \"memory\", \"v16\", \"v17\", \"v18\",\n-\t\t\"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n+\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n+\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n+\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n+\t\t\"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\", \"x15\", \"x16\",\n+\t\t\"x17\", \"x18\", \"x19\", \"x20\", \"x21\", \"x22\", \"x23\", \"v16\", \"v17\",\n+\t\t\"v18\", \"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n \t\t);\n \t\tbreak;\n \t}\n \tcase 16:\n \t{\n-\t\t__uint128_t t0, t1, t2, t3, t4, t5, t6, t7;\n-\n \t\tasm volatile (\n \t\t\".cpu generic+lse\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d16, %[t0]\\n\"\n-\t\t\"fmov v16.D[1], %H[t0]\\n\"\n-\t\t\"fmov d17, %[t1]\\n\"\n-\t\t\"fmov v17.D[1], %H[t1]\\n\"\n-\t\t\"fmov d18, %[t2]\\n\"\n-\t\t\"fmov v18.D[1], %H[t2]\\n\"\n-\t\t\"fmov d19, %[t3]\\n\"\n-\t\t\"fmov v19.D[1], %H[t3]\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x8, x9, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x10, x11, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x12, x13, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x14, x15, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d16, x0\\n\"\n+\t\t\"fmov v16.D[1], x1\\n\"\n+\t\t\"fmov d17, x2\\n\"\n+\t\t\"fmov v17.D[1], x3\\n\"\n+\t\t\"fmov d18, x4\\n\"\n+\t\t\"fmov v18.D[1], x5\\n\"\n+\t\t\"fmov d19, x6\\n\"\n+\t\t\"fmov v19.D[1], x7\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, %[t4]\\n\"\n-\t\t\"fmov v20.D[1], %H[t4]\\n\"\n-\t\t\"fmov d21, %[t5]\\n\"\n-\t\t\"fmov v21.D[1], %H[t5]\\n\"\n-\t\t\"fmov d22, %[t6]\\n\"\n-\t\t\"fmov v22.D[1], %H[t6]\\n\"\n-\t\t\"fmov d23, %[t7]\\n\"\n-\t\t\"fmov v23.D[1], %H[t7]\\n\"\n+\t\t\"fmov d20, x8\\n\"\n+\t\t\"fmov v20.D[1], x9\\n\"\n+\t\t\"fmov d21, x10\\n\"\n+\t\t\"fmov v21.D[1], x11\\n\"\n+\t\t\"fmov d22, x12\\n\"\n+\t\t\"fmov v22.D[1], x13\\n\"\n+\t\t\"fmov d23, x14\\n\"\n+\t\t\"fmov v23.D[1], x15\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n \t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n \t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n-\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n-\t\t[t3] \"=&r\" (t3), [t4] \"=&r\" (t4), [t5] \"=&r\" (t5),\n-\t\t[t6] \"=&r\" (t6), [t7] \"=&r\" (t7)\n-\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n-\t\t[loc] \"r\" (addr)\n-\t\t: \"memory\", \"v16\", \"v17\", \"v18\", \"v19\",\n-\t\t \"v20\", \"v21\", \"v22\", \"v23\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n+\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n+\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n+\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n+\t\t\"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\", \"x15\", \"v16\",\n+\t\t\"v17\", \"v18\", \"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n \t\t);\n \t\tbreak;\n \t}\n \tcase 8:\n \t{\n-\t\t__uint128_t t0, t1, t2, t3;\n-\n \t\tasm volatile (\n \t\t\".cpu generic+lse\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d16, %[t0]\\n\"\n-\t\t\"fmov v16.D[1], %H[t0]\\n\"\n-\t\t\"fmov d17, %[t1]\\n\"\n-\t\t\"fmov v17.D[1], %H[t1]\\n\"\n-\t\t\"fmov d18, %[t2]\\n\"\n-\t\t\"fmov v18.D[1], %H[t2]\\n\"\n-\t\t\"fmov d19, %[t3]\\n\"\n-\t\t\"fmov v19.D[1], %H[t3]\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d16, x0\\n\"\n+\t\t\"fmov v16.D[1], x1\\n\"\n+\t\t\"fmov d17, x2\\n\"\n+\t\t\"fmov v17.D[1], x3\\n\"\n+\t\t\"fmov d18, x4\\n\"\n+\t\t\"fmov v18.D[1], x5\\n\"\n+\t\t\"fmov d19, x6\\n\"\n+\t\t\"fmov v19.D[1], x7\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n \t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n-\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n-\t\t[t3] \"=&r\" (t3)\n-\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n-\t\t[loc] \"r\" (addr)\n-\t\t: \"memory\", \"v16\", \"v17\", \"v18\", \"v19\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n+\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n+\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n+\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n+\t\t\"v16\", \"v17\", \"v18\", \"v19\"\n \t\t);\n \t\tbreak;\n \t}\n \tcase 4:\n \t{\n-\t\t__uint128_t t0, t1;\n-\n \t\tasm volatile (\n \t\t\".cpu generic+lse\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d16, %[t0]\\n\"\n-\t\t\"fmov v16.D[1], %H[t0]\\n\"\n-\t\t\"fmov d17, %[t1]\\n\"\n-\t\t\"fmov v17.D[1], %H[t1]\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d16, x0\\n\"\n+\t\t\"fmov v16.D[1], x1\\n\"\n+\t\t\"fmov d17, x2\\n\"\n+\t\t\"fmov v17.D[1], x3\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n \t\t\"st1 { v16.2d, v17.2d}, [%[dst]], 32\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n-\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1)\n-\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n-\t\t[loc] \"r\" (addr)\n-\t\t: \"memory\", \"v16\", \"v17\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n+\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n+\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n+\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"v16\", \"v17\"\n \t\t);\n \t\tbreak;\n \t}\n \tcase 2:\n \t{\n-\t\t__uint128_t t0;\n-\n \t\tasm volatile (\n \t\t\".cpu generic+lse\\n\"\n-\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n-\t\t\"fmov d16, %[t0]\\n\"\n-\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n+\t\t\"fmov d16, x0\\n\"\n+\t\t\"fmov v16.D[1], x1\\n\"\n \t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n \t\t\"st1 { v16.2d}, [%[dst]], 16\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n-\t\t[t0] \"=&r\" (t0)\n-\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n-\t\t[loc] \"r\" (addr)\n-\t\t: \"memory\", \"v16\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n+\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n+\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n+\t\t: \"memory\", \"x0\", \"x1\", \"v16\"\n \t\t);\n \t\tbreak;\n \t}\n@@ -308,7 +281,7 @@ otx2_npa_clear_alloc(struct rte_mempool *mp, void **obj_table, unsigned int n)\n \t}\n }\n\n-static inline int __hot\n+static __rte_noinline int __hot\n otx2_npa_deq_arm64(struct rte_mempool *mp, void **obj_table, unsigned int n)\n {\n \tconst int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);\n@@ -332,7 +305,8 @@ otx2_npa_deq_arm64(struct rte_mempool *mp, void **obj_table, unsigned int n)\n\n \treturn 0;\n }\n-#endif\n+\n+#else\n\n static inline int __hot\n otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)\n@@ -359,6 +333,8 @@ otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)\n \treturn 0;\n }\n\n+#endif\n+\n static unsigned int\n otx2_npa_get_count(const struct rte_mempool *mp)\n {\n", "prefixes": [] }