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GET /api/patches/55729/?format=api
{ "id": 55729, "url": "http://patches.dpdk.org/api/patches/55729/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-34-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-34-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-34-jerinj@marvell.com", "date": "2019-06-30T18:05:45", "name": "[v2,33/57] net/octeontx2: add flow utility functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ebf8686014ac9a31e180b2c16b94de82539b2669", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-34-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55729/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55729/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D596B1BBF5;\n\tSun, 30 Jun 2019 20:11:12 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3EE761BA5B\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:08:17 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI50uJ015649 for <dev@dpdk.org>; Sun, 30 Jun 2019 11:08:16 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2te7gm3yck-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 11:08:16 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:08:14 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:08:14 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 2818A3F7040;\n\tSun, 30 Jun 2019 11:08:12 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=wdgq4vpFHm6Of/v/mEkFj62ky4jbc4rmnRvgn6EN4KA=;\n\tb=fS/K2pFW1Uy3E9G2jmLv5mslg/oQmyNI7n5U9fPGYBQdDUqtjfm0E4snrYtkzqsq/va8\n\tmar/ndF4MbJ033sgLFXRW2sDo2O9eWGP2P0f4n13OG1LDHRl7ZtRYYsJrUoAD84ikYb9\n\t2/cfR8Wvr+7EDJhWlAg5uPm6Z0b3XMRxGUQTWVNnZqFUxg9s38aWCFh/+kFcURFfGidJ\n\twnlG60W1RRgZZqio6V+Mgs6Zjhi+F26sYceiBscp48rdr2FliqT6LX6Y4kFGZw6IiHR1\n\ta2DP+V3rA9sZURhKKLmysf1D4QrG9fbAJO1oRo43kQkEImfMoSjpHkfZGZD8OtuDaFNl\n\tJw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Vivek Sharma <viveksharma@marvell.com>", "Date": "Sun, 30 Jun 2019 23:35:45 +0530", "Message-ID": "<20190630180609.36705-34-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 33/57] net/octeontx2: add flow utility\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nFirst pass rte_flow utility functions for octeontx2.\nThese will be used to communicate with AF driver.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vivek Sharma <viveksharma@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.h | 7 +-\n drivers/net/octeontx2/otx2_flow.h | 2 +\n drivers/net/octeontx2/otx2_flow_utils.c | 387 ++++++++++++++++++++++++\n 5 files changed, 392 insertions(+), 6 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_flow_utils.c", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex a0155e727..8d1aeae3f 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -37,6 +37,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_lookup.c\t\\\n \totx2_ethdev.c\t\\\n \totx2_flow_ctrl.c \\\n+\totx2_flow_utils.c \\\n \totx2_ethdev_irq.c \\\n \totx2_ethdev_ops.c \\\n \totx2_ethdev_debug.c \\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 2cac57d2b..75156ddbe 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -12,6 +12,7 @@ sources = files(\n \t\t'otx2_lookup.c',\n \t\t'otx2_ethdev.c',\n \t\t'otx2_flow_ctrl.c',\n+\t\t'otx2_flow_utils.c',\n \t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_ops.c',\n \t\t'otx2_ethdev_debug.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 8f8d93a39..e8a22b6ec 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -17,6 +17,7 @@\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n+#include \"otx2_flow.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n #include \"otx2_rx.h\"\n@@ -173,12 +174,6 @@ struct otx2_eth_qconf {\n \tuint16_t nb_desc;\n };\n \n-struct otx2_npc_flow_info {\n-\tuint16_t channel; /*rx channel */\n-\tuint16_t flow_prealloc_size;\n-\tuint16_t flow_max_priority;\n-};\n-\n struct otx2_fc_info {\n \tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n \tuint8_t rx_pause;\ndiff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h\nindex 95bb6c2bf..f5cc3b983 100644\n--- a/drivers/net/octeontx2/otx2_flow.h\n+++ b/drivers/net/octeontx2/otx2_flow.h\n@@ -15,6 +15,8 @@\n #include \"otx2_ethdev.h\"\n #include \"otx2_mbox.h\"\n \n+struct otx2_eth_dev;\n+\n int otx2_flow_init(struct otx2_eth_dev *hw);\n int otx2_flow_fini(struct otx2_eth_dev *hw);\n extern const struct rte_flow_ops otx2_flow_ops;\ndiff --git a/drivers/net/octeontx2/otx2_flow_utils.c b/drivers/net/octeontx2/otx2_flow_utils.c\nnew file mode 100644\nindex 000000000..6078a827b\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_flow_utils.c\n@@ -0,0 +1,387 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_ethdev.h\"\n+#include \"otx2_flow.h\"\n+\n+int\n+otx2_flow_mcam_free_counter(struct otx2_mbox *mbox, uint16_t ctr_id)\n+{\n+\tstruct npc_mcam_oper_counter_req *req;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npc_mcam_free_counter(mbox);\n+\treq->cntr = ctr_id;\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_flow_mcam_read_counter(struct otx2_mbox *mbox, uint32_t ctr_id,\n+\t\t\t uint64_t *count)\n+{\n+\tstruct npc_mcam_oper_counter_req *req;\n+\tstruct npc_mcam_oper_counter_rsp *rsp;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npc_mcam_counter_stats(mbox);\n+\treq->cntr = ctr_id;\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n+\n+\t*count = rsp->stat;\n+\treturn rc;\n+}\n+\n+int\n+otx2_flow_mcam_clear_counter(struct otx2_mbox *mbox, uint32_t ctr_id)\n+{\n+\tstruct npc_mcam_oper_counter_req *req;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npc_mcam_clear_counter(mbox);\n+\treq->cntr = ctr_id;\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_flow_mcam_free_entry(struct otx2_mbox *mbox, uint32_t entry)\n+{\n+\tstruct npc_mcam_free_entry_req *req;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n+\treq->entry = entry;\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_flow_mcam_free_all_entries(struct otx2_mbox *mbox)\n+{\n+\tstruct npc_mcam_free_entry_req *req;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n+\treq->all = 1;\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n+\n+\treturn rc;\n+}\n+\n+static void\n+flow_prep_mcam_ldata(uint8_t *ptr, const uint8_t *data, int len)\n+{\n+\tint idx;\n+\n+\tfor (idx = 0; idx < len; idx++)\n+\t\tptr[idx] = data[len - 1 - idx];\n+}\n+\n+static int\n+flow_check_copysz(size_t size, size_t len)\n+{\n+\tif (len <= size)\n+\t\treturn len;\n+\treturn -1;\n+}\n+\n+static inline int\n+flow_mem_is_zero(const void *mem, int len)\n+{\n+\tconst char *m = mem;\n+\tint i;\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tif (m[i] != 0)\n+\t\t\treturn 0;\n+\t}\n+\treturn 1;\n+}\n+\n+void\n+otx2_flow_get_hw_supp_mask(struct otx2_parse_state *pst,\n+\t\t\t struct otx2_flow_item_info *info, int lid, int lt)\n+{\n+\tstruct npc_xtract_info *xinfo;\n+\tchar *hw_mask = info->hw_mask;\n+\tint max_off, offset;\n+\tint i, j;\n+\tint intf;\n+\n+\tintf = pst->flow->nix_intf;\n+\txinfo = pst->npc->prx_dxcfg[intf][lid][lt].xtract;\n+\tmemset(hw_mask, 0, info->len);\n+\n+\tfor (i = 0; i < NPC_MAX_LD; i++) {\n+\t\tif (xinfo[i].hdr_off < info->hw_hdr_len)\n+\t\t\tcontinue;\n+\n+\t\tmax_off = xinfo[i].hdr_off + xinfo[i].len - info->hw_hdr_len;\n+\n+\t\tif (xinfo[i].enable == 0)\n+\t\t\tcontinue;\n+\n+\t\tif (max_off > info->len)\n+\t\t\tmax_off = info->len;\n+\n+\t\toffset = xinfo[i].hdr_off - info->hw_hdr_len;\n+\t\tfor (j = offset; j < max_off; j++)\n+\t\t\thw_mask[j] = 0xff;\n+\t}\n+}\n+\n+int\n+otx2_flow_update_parse_state(struct otx2_parse_state *pst,\n+\t\t\t struct otx2_flow_item_info *info, int lid, int lt,\n+\t\t\t uint8_t flags)\n+{\n+\tuint8_t int_info_mask[NPC_MAX_EXTRACT_DATA_LEN];\n+\tuint8_t int_info[NPC_MAX_EXTRACT_DATA_LEN];\n+\tstruct npc_lid_lt_xtract_info *xinfo;\n+\tint len = 0;\n+\tint intf;\n+\tint i;\n+\n+\totx2_npc_dbg(\"Parse state function info mask total %s\",\n+\t\t (const uint8_t *)info->mask);\n+\n+\tpst->layer_mask |= lid;\n+\tpst->lt[lid] = lt;\n+\tpst->flags[lid] = flags;\n+\n+\tintf = pst->flow->nix_intf;\n+\txinfo = &pst->npc->prx_dxcfg[intf][lid][lt];\n+\totx2_npc_dbg(\"Is_terminating = %d\", xinfo->is_terminating);\n+\tif (xinfo->is_terminating)\n+\t\tpst->terminate = 1;\n+\n+\t/* Need to check if flags are supported but in latest\n+\t * KPU profile, flags are used as enumeration! No way,\n+\t * it can be validated unless MBOX is changed to return\n+\t * set of valid values out of 2**8 possible values.\n+\t */\n+\tif (info->spec == NULL) {\t/* Nothing to match */\n+\t\totx2_npc_dbg(\"Info spec NULL\");\n+\t\tgoto done;\n+\t}\n+\n+\t/* Copy spec and mask into mcam match string, mask.\n+\t * Since both RTE FLOW and OTX2 MCAM use network-endianness\n+\t * for data, we are saved from nasty conversions.\n+\t */\n+\tfor (i = 0; i < NPC_MAX_LD; i++) {\n+\t\tstruct npc_xtract_info *x;\n+\t\tint k, idx, hdr_off;\n+\n+\t\tx = &xinfo->xtract[i];\n+\t\tlen = x->len;\n+\t\thdr_off = x->hdr_off;\n+\n+\t\tif (hdr_off < info->hw_hdr_len)\n+\t\t\tcontinue;\n+\n+\t\tif (x->enable == 0)\n+\t\t\tcontinue;\n+\n+\t\totx2_npc_dbg(\"x->hdr_off = %d, len = %d, info->len = %d,\"\n+\t\t\t \"x->key_off = %d\", x->hdr_off, len, info->len,\n+\t\t\t x->key_off);\n+\n+\t\thdr_off -= info->hw_hdr_len;\n+\n+\t\tif (hdr_off + len > info->len)\n+\t\t\tlen = info->len - hdr_off;\n+\n+\t\t/* Check for over-write of previous layer */\n+\t\tif (!flow_mem_is_zero(pst->mcam_mask + x->key_off,\n+\t\t\t\t len)) {\n+\t\t\t/* Cannot support this data match */\n+\t\t\trte_flow_error_set(pst->error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t pst->pattern,\n+\t\t\t\t\t \"Extraction unsupported\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\n+\t\tlen = flow_check_copysz((OTX2_MAX_MCAM_WIDTH_DWORDS * 8)\n+\t\t\t\t\t- x->key_off,\n+\t\t\t\t\tlen);\n+\t\tif (len < 0) {\n+\t\t\trte_flow_error_set(pst->error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t pst->pattern,\n+\t\t\t\t\t \"Internal Error\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\n+\t\t/* Need to reverse complete structure so that dest addr is at\n+\t\t * MSB so as to program the MCAM using mcam_data & mcam_mask\n+\t\t * arrays\n+\t\t */\n+\t\tflow_prep_mcam_ldata(int_info,\n+\t\t\t\t (const uint8_t *)info->spec + hdr_off,\n+\t\t\t\t x->len);\n+\t\tflow_prep_mcam_ldata(int_info_mask,\n+\t\t\t\t (const uint8_t *)info->mask + hdr_off,\n+\t\t\t\t x->len);\n+\n+\t\totx2_npc_dbg(\"Spec: \");\n+\t\tfor (k = 0; k < info->len; k++)\n+\t\t\totx2_npc_dbg(\"0x%.2x \",\n+\t\t\t\t ((const uint8_t *)info->spec)[k]);\n+\n+\t\totx2_npc_dbg(\"Int_info: \");\n+\t\tfor (k = 0; k < info->len; k++)\n+\t\t\totx2_npc_dbg(\"0x%.2x \", int_info[k]);\n+\n+\t\tmemcpy(pst->mcam_mask + x->key_off, int_info_mask, len);\n+\t\tmemcpy(pst->mcam_data + x->key_off, int_info, len);\n+\n+\t\totx2_npc_dbg(\"Parse state mcam data & mask\");\n+\t\tfor (idx = 0; idx < len ; idx++)\n+\t\t\totx2_npc_dbg(\"data[%d]: 0x%x, mask[%d]: 0x%x\", idx,\n+\t\t\t\t *(pst->mcam_data + idx + x->key_off), idx,\n+\t\t\t\t *(pst->mcam_mask + idx + x->key_off));\n+\t}\n+\n+done:\n+\t/* Next pattern to parse by subsequent layers */\n+\tpst->pattern++;\n+\treturn 0;\n+}\n+\n+static inline int\n+flow_range_is_valid(const char *spec, const char *last, const char *mask,\n+\t\t int len)\n+{\n+\t/* Mask must be zero or equal to spec as we do not support\n+\t * non-contiguous ranges.\n+\t */\n+\twhile (len--) {\n+\t\tif (last[len] &&\n+\t\t (spec[len] & mask[len]) != (last[len] & mask[len]))\n+\t\t\treturn 0; /* False */\n+\t}\n+\treturn 1;\n+}\n+\n+\n+static inline int\n+flow_mask_is_supported(const char *mask, const char *hw_mask, int len)\n+{\n+\t/*\n+\t * If no hw_mask, assume nothing is supported.\n+\t * mask is never NULL\n+\t */\n+\tif (hw_mask == NULL)\n+\t\treturn flow_mem_is_zero(mask, len);\n+\n+\twhile (len--) {\n+\t\tif ((mask[len] | hw_mask[len]) != hw_mask[len])\n+\t\t\treturn 0; /* False */\n+\t}\n+\treturn 1;\n+}\n+\n+int\n+otx2_flow_parse_item_basic(const struct rte_flow_item *item,\n+\t\t\t struct otx2_flow_item_info *info,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\t/* Item must not be NULL */\n+\tif (item == NULL) {\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t \"Item is NULL\");\n+\t\treturn -rte_errno;\n+\t}\n+\t/* If spec is NULL, both mask and last must be NULL, this\n+\t * makes it to match ANY value (eq to mask = 0).\n+\t * Setting either mask or last without spec is an error\n+\t */\n+\tif (item->spec == NULL) {\n+\t\tif (item->last == NULL && item->mask == NULL) {\n+\t\t\tinfo->spec = NULL;\n+\t\t\treturn 0;\n+\t\t}\n+\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t \"mask or last set without spec\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\t/* We have valid spec */\n+\tinfo->spec = item->spec;\n+\n+\t/* If mask is not set, use default mask, err if default mask is\n+\t * also NULL.\n+\t */\n+\tif (item->mask == NULL) {\n+\t\totx2_npc_dbg(\"Item mask null, using default mask\");\n+\t\tif (info->def_mask == NULL) {\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"No mask or default mask given\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t\tinfo->mask = info->def_mask;\n+\t} else {\n+\t\tinfo->mask = item->mask;\n+\t}\n+\n+\t/* mask specified must be subset of hw supported mask\n+\t * mask | hw_mask == hw_mask\n+\t */\n+\tif (!flow_mask_is_supported(info->mask, info->hw_mask, info->len)) {\n+\t\trte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t item, \"Unsupported field in the mask\");\n+\t\treturn -rte_errno;\n+\t}\n+\n+\t/* Now we have spec and mask. OTX2 does not support non-contiguous\n+\t * range. We should have either:\n+\t * - spec & mask == last & mask or,\n+\t * - last == 0 or,\n+\t * - last == NULL\n+\t */\n+\tif (item->last != NULL && !flow_mem_is_zero(item->last, info->len)) {\n+\t\tif (!flow_range_is_valid(item->spec, item->last, info->mask,\n+\t\t\t\t\t info->len)) {\n+\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"Unsupported range for match\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+otx2_flow_keyx_compress(uint64_t *data, uint32_t nibble_mask)\n+{\n+\tuint64_t cdata[2] = {0ULL, 0ULL}, nibble;\n+\tint i, j = 0;\n+\n+\tfor (i = 0; i < NPC_MAX_KEY_NIBBLES; i++) {\n+\t\tif (nibble_mask & (1 << i)) {\n+\t\t\tnibble = (data[i / 16] >> ((i & 0xf) * 4)) & 0xf;\n+\t\t\tcdata[j / 16] |= (nibble << ((j & 0xf) * 4));\n+\t\t\tj += 1;\n+\t\t}\n+\t}\n+\n+\tdata[0] = cdata[0];\n+\tdata[1] = cdata[1];\n+}\n+\n", "prefixes": [ "v2", "33/57" ] }