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GET /api/patches/55728/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55728,
    "url": "http://patches.dpdk.org/api/patches/55728/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-52-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190630180609.36705-52-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-52-jerinj@marvell.com",
    "date": "2019-06-30T18:06:03",
    "name": "[v2,51/57] net/octeontx2: add Tx burst support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b46093768348beb6a03f478f19e062f5db933f17",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-52-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5236,
            "url": "http://patches.dpdk.org/api/series/5236/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236",
            "date": "2019-06-30T18:05:12",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/5236/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55728/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/55728/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6ECBA1BC7A;\n\tSun, 30 Jun 2019 20:12:37 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 14CC31B9D4\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:09:10 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI6dmS028335; Sun, 30 Jun 2019 11:09:10 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2te5bn4gp7-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 30 Jun 2019 11:09:09 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:09:08 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:09:08 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 538D03F7040;\n\tSun, 30 Jun 2019 11:09:06 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=TlTL6mghCQ5fQcMC7Bcl/tlZulviE3R09iqulF7Bn/U=;\n\tb=Bd0E3BBcE9JIVwod1GGstl3uJ74IqhS8Mohg625oKC/dZ4h6A3t5qIr7+hSQ5rNuXTG4\n\to7OkkFf68cQeLrn1nF3V5dOK2KD//cr+RbX5TEEegAPbDysICSw1joPduMI+P4oc1XAa\n\t5szZumv7dfhI+RymWXeODRotNN/HUBuVHm1OdwfyJgn7KlQjJ85bPudN/AtBp0sVnbH0\n\tNbusrALJBqXCzD1jb/iBjWOxDIwE/QOj4Pp55Zapk/lra+gVxWKWmwCpW89bosRpE62t\n\tkiWQ0Uw7Rz+gthFfIOYv4oDJJ6UPaJ5EokSXSHnCa0dBY+j6x5DjMm2nQPkKDweOzeAX\n\tpQ== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>",
        "CC": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Harman Kalra\n\t<hkalra@marvell.com>",
        "Date": "Sun, 30 Jun 2019 23:36:03 +0530",
        "Message-ID": "<20190630180609.36705-52-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0",
        "Subject": "[dpdk-dev]  [PATCH v2 51/57] net/octeontx2: add Tx burst support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Tx burst support.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini     |   5 +\n doc/guides/nics/features/octeontx2_vec.ini |   5 +\n doc/guides/nics/features/octeontx2_vf.ini  |   5 +\n doc/guides/nics/octeontx2.rst              |   1 +\n drivers/net/octeontx2/Makefile             |   1 +\n drivers/net/octeontx2/meson.build          |   1 +\n drivers/net/octeontx2/otx2_ethdev.c        |   6 -\n drivers/net/octeontx2/otx2_ethdev.h        |   1 +\n drivers/net/octeontx2/otx2_tx.c            |  94 ++++++++\n drivers/net/octeontx2/otx2_tx.h            | 261 +++++++++++++++++++++\n 10 files changed, 374 insertions(+), 6 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_tx.c",
    "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 3280cba78..1856d9924 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -12,6 +12,7 @@ Link status          = Y\n Link status event    = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free       = Y\n Free Tx mbuf on demand = Y\n Queue start/stop     = Y\n Promiscuous mode     = Y\n@@ -28,6 +29,10 @@ Jumbo frame          = Y\n Scattered Rx         = Y\n VLAN offload         = Y\n QinQ offload         = Y\n+L3 checksum offload  = Y\n+L4 checksum offload  = Y\n+Inner L3 checksum    = Y\n+Inner L4 checksum    = Y\n Packet type parsing  = Y\n Timesync             = Y\n Timestamp offload    = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex 315722e60..053fca288 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -12,6 +12,7 @@ Link status          = Y\n Link status event    = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free       = Y\n Free Tx mbuf on demand = Y\n Queue start/stop     = Y\n Promiscuous mode     = Y\n@@ -27,6 +28,10 @@ Flow API             = Y\n Jumbo frame          = Y\n VLAN offload         = Y\n QinQ offload         = Y\n+L3 checksum offload  = Y\n+L4 checksum offload  = Y\n+Inner L3 checksum    = Y\n+Inner L4 checksum    = Y\n Packet type parsing  = Y\n Rx descriptor status = Y\n Basic stats          = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex 17b223221..bef451d01 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -11,6 +11,7 @@ Link status          = Y\n Link status event    = Y\n Runtime Rx queue setup = Y\n Runtime Tx queue setup = Y\n+Fast mbuf free       = Y\n Free Tx mbuf on demand = Y\n Queue start/stop     = Y\n RSS hash             = Y\n@@ -23,6 +24,10 @@ Jumbo frame          = Y\n Scattered Rx         = Y\n VLAN offload         = Y\n QinQ offload         = Y\n+L3 checksum offload  = Y\n+L4 checksum offload  = Y\n+Inner L3 checksum    = Y\n+Inner L4 checksum    = Y\n Packet type parsing  = Y\n Rx descriptor status = Y\n Basic stats          = Y\ndiff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex 9d6596ad8..90ca4e2d2 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -25,6 +25,7 @@ Features of the OCTEON TX2 Ethdev PMD are:\n - Receiver Side Scaling (RSS)\n - MAC/VLAN filtering\n - Generic flow API\n+- Inner and Outer Checksum offload\n - VLAN/QinQ stripping and insertion\n - Port hardware statistics\n - Link state information\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex a5f125655..c187d2555 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_rx.c \t\\\n+\totx2_tx.c \t\\\n \totx2_tm.c\t\\\n \totx2_rss.c\t\\\n \totx2_mac.c\t\\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 9d151f88d..94bf09a78 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources = files('otx2_rx.c',\n+\t\t'otx2_tx.c',\n \t\t'otx2_tm.c',\n \t\t'otx2_rss.c',\n \t\t'otx2_mac.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 1f8a22300..44753cbf5 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -14,12 +14,6 @@\n \n #include \"otx2_ethdev.h\"\n \n-static inline void\n-otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n-{\n-\tRTE_SET_USED(eth_dev);\n-}\n-\n static inline uint64_t\n nix_get_rx_offload_capa(struct otx2_eth_dev *dev)\n {\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 22cf86981..1f9323fe3 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -484,6 +484,7 @@ int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n \n /* Rx and Tx routines */\n void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);\n+void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);\n void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);\n \n /* Timesync - PTP routines */\ndiff --git a/drivers/net/octeontx2/otx2_tx.c b/drivers/net/octeontx2/otx2_tx.c\nnew file mode 100644\nindex 000000000..16d69b74f\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_tx.c\n@@ -0,0 +1,94 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_vect.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+#define NIX_XMIT_FC_OR_RETURN(txq, pkts) do {\t\t\t\t\\\n+\t/* Cached value is low, Update the fc_cache_pkts */\t\t\\\n+\tif (unlikely((txq)->fc_cache_pkts < (pkts))) {\t\t\t\\\n+\t\t/* Multiply with sqe_per_sqb to express in pkts */\t\\\n+\t\t(txq)->fc_cache_pkts =\t\t\t\t\t\\\n+\t\t\t((txq)->nb_sqb_bufs_adj - *(txq)->fc_mem) <<    \\\n+\t\t\t\t(txq)->sqes_per_sqb_log2;\t\t\\\n+\t\t/* Check it again for the room */\t\t\t\\\n+\t\tif (unlikely((txq)->fc_cache_pkts < (pkts)))\t\t\\\n+\t\t\treturn 0;\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+} while (0)\n+\n+\n+static __rte_always_inline uint16_t\n+nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t      uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct otx2_eth_txq *txq = tx_queue; uint16_t i;\n+\tconst rte_iova_t io_addr = txq->io_addr;\n+\tvoid *lmt_addr = txq->lmt_addr;\n+\n+\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\n+\totx2_lmt_mov(cmd, &txq->cmd[0], otx2_nix_tx_ext_subs(flags));\n+\n+\t/* Lets commit any changes in the packet */\n+\trte_cio_wmb();\n+\n+\tfor (i = 0; i < pkts; i++) {\n+\t\totx2_nix_xmit_prepare(tx_pkts[i], cmd, flags);\n+\t\t/* Passing no of segdw as 4: HDR + EXT + SG + SMEM */\n+\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n+\t\t\t\t\t     tx_pkts[i]->ol_flags, 4, flags);\n+\t\totx2_nix_xmit_one(cmd, lmt_addr, io_addr, flags);\n+\t}\n+\n+\t/* Reduce the cached count */\n+\ttxq->fc_cache_pkts -= pkts;\n+\n+\treturn pkts;\n+}\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+static uint16_t __rte_noinline\t__hot\t\t\t\t\t\\\n+otx2_nix_xmit_pkts_ ## name(void *tx_queue,\t\t\t\t\\\n+\t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\treturn nix_xmit_pkts(tx_queue, tx_pkts, pkts, cmd, flags);\t\\\n+}\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\n+static inline void\n+pick_tx_func(struct rte_eth_dev *eth_dev,\n+\t     const eth_tx_burst_t tx_burst[2][2][2][2][2])\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\t/* [TSTMP] [NOFF] [VLAN] [OL3_OL4_CSUM] [IL3_IL4_CSUM] */\n+\teth_dev->tx_pkt_burst = tx_burst\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+}\n+\n+void\n+otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t[f4][f3][f2][f1][f0] =  otx2_nix_xmit_pkts_ ## name,\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\t};\n+\n+\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n+\n+\trte_mb();\n+}\ndiff --git a/drivers/net/octeontx2/otx2_tx.h b/drivers/net/octeontx2/otx2_tx.h\nindex 4d0993f87..db4c1f70f 100644\n--- a/drivers/net/octeontx2/otx2_tx.h\n+++ b/drivers/net/octeontx2/otx2_tx.h\n@@ -25,4 +25,265 @@\n #define NIX_TX_NEED_EXT_HDR \\\n \t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F)\n \n+/* Function to determine no of tx subdesc required in case ext\n+ * sub desc is enabled.\n+ */\n+static __rte_always_inline int\n+otx2_nix_tx_ext_subs(const uint16_t flags)\n+{\n+\treturn (flags & NIX_TX_OFFLOAD_TSTAMP_F) ? 2 :\n+\t\t((flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) ? 1 : 0);\n+}\n+\n+static __rte_always_inline void\n+otx2_nix_xmit_prepare_tstamp(uint64_t *cmd,  const uint64_t *send_mem_desc,\n+\t\t\t     const uint64_t ol_flags, const uint16_t no_segdw,\n+\t\t\t     const uint16_t flags)\n+{\n+\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\tstruct nix_send_mem_s *send_mem;\n+\t\tuint16_t off = (no_segdw - 1) << 1;\n+\n+\t\tsend_mem = (struct nix_send_mem_s *)(cmd + off);\n+\t\tif (flags & NIX_TX_MULTI_SEG_F)\n+\t\t\t/* Retrieving the default desc values */\n+\t\t\tcmd[off] = send_mem_desc[6];\n+\n+\t\t/* Packets for which PKT_TX_IEEE1588_TMST is not set, tx tstamp\n+\t\t * should not be updated at tx tstamp registered address, rather\n+\t\t * a dummy address which is eight bytes ahead would be updated\n+\t\t */\n+\t\tsend_mem->addr = (rte_iova_t)((uint64_t *)send_mem_desc[7] +\n+\t\t\t\t!(ol_flags & PKT_TX_IEEE1588_TMST));\n+\t}\n+}\n+\n+static inline void\n+otx2_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tuint64_t ol_flags = 0, mask;\n+\tunion nix_send_hdr_w1_u w1;\n+\tunion nix_send_sg_s *sg;\n+\n+\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n+\tif (flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)(cmd + 2);\n+\t\tsg = (union nix_send_sg_s *)(cmd + 4);\n+\t\t/* Clear previous markings */\n+\t\tsend_hdr_ext->w0.lso = 0;\n+\t\tsend_hdr_ext->w1.u = 0;\n+\t} else {\n+\t\tsg = (union nix_send_sg_s *)(cmd + 2);\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1) {\n+\t\tol_flags = m->ol_flags;\n+\t\tw1.u = 0;\n+\t}\n+\n+\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n+\t\tsend_hdr->w0.total = m->data_len;\n+\t\tsend_hdr->w0.aura =\n+\t\t\tnpa_lf_aura_handle_to_aura(m->pool->pool_id);\n+\t}\n+\n+\t/*\n+\t * L3type:  2 => IPV4\n+\t *          3 => IPV4 with csum\n+\t *          4 => IPV6\n+\t * L3type and L3ptr needs to be set for either\n+\t * L3 csum or L4 csum or LSO\n+\t *\n+\t */\n+\n+\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n+\t    (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n+\t\tconst uint8_t csum = !!(ol_flags & PKT_TX_OUTER_UDP_CKSUM);\n+\t\tconst uint8_t ol3type =\n+\t\t\t((!!(ol_flags & PKT_TX_OUTER_IPV4)) << 1) +\n+\t\t\t((!!(ol_flags & PKT_TX_OUTER_IPV6)) << 2) +\n+\t\t\t!!(ol_flags & PKT_TX_OUTER_IP_CKSUM);\n+\n+\t\t/* Outer L3 */\n+\t\tw1.ol3type = ol3type;\n+\t\tmask = 0xffffull << ((!!ol3type) << 4);\n+\t\tw1.ol3ptr = ~mask & m->outer_l2_len;\n+\t\tw1.ol4ptr = ~mask & (w1.ol3ptr + m->outer_l3_len);\n+\n+\t\t/* Outer L4 */\n+\t\tw1.ol4type = csum + (csum << 1);\n+\n+\t\t/* Inner L3 */\n+\t\tw1.il3type = ((!!(ol_flags & PKT_TX_IPV4)) << 1) +\n+\t\t\t((!!(ol_flags & PKT_TX_IPV6)) << 2);\n+\t\tw1.il3ptr = w1.ol4ptr + m->l2_len;\n+\t\tw1.il4ptr = w1.il3ptr + m->l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.il3type = w1.il3type + !!(ol_flags & PKT_TX_IP_CKSUM);\n+\n+\t\t/* Inner L4 */\n+\t\tw1.il4type =  (ol_flags & PKT_TX_L4_MASK) >> 52;\n+\n+\t\t/* In case of no tunnel header use only\n+\t\t * shift IL3/IL4 fields a bit to use\n+\t\t * OL3/OL4 for header checksum\n+\t\t */\n+\t\tmask = !ol3type;\n+\t\tw1.u = ((w1.u & 0xFFFFFFFF00000000) >> (mask << 3)) |\n+\t\t\t((w1.u & 0X00000000FFFFFFFF) >> (mask << 4));\n+\n+\t} else if (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) {\n+\t\tconst uint8_t csum = !!(ol_flags & PKT_TX_OUTER_UDP_CKSUM);\n+\t\tconst uint8_t outer_l2_len = m->outer_l2_len;\n+\n+\t\t/* Outer L3 */\n+\t\tw1.ol3ptr = outer_l2_len;\n+\t\tw1.ol4ptr = outer_l2_len + m->outer_l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.ol3type = ((!!(ol_flags & PKT_TX_OUTER_IPV4)) << 1) +\n+\t\t\t((!!(ol_flags & PKT_TX_OUTER_IPV6)) << 2) +\n+\t\t\t!!(ol_flags & PKT_TX_OUTER_IP_CKSUM);\n+\n+\t\t/* Outer L4 */\n+\t\tw1.ol4type = csum + (csum << 1);\n+\n+\t} else if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) {\n+\t\tconst uint8_t l2_len = m->l2_len;\n+\n+\t\t/* Always use OLXPTR and OLXTYPE when only\n+\t\t * when one header is present\n+\t\t */\n+\n+\t\t/* Inner L3 */\n+\t\tw1.ol3ptr = l2_len;\n+\t\tw1.ol4ptr = l2_len + m->l3_len;\n+\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n+\t\tw1.ol3type = ((!!(ol_flags & PKT_TX_IPV4)) << 1) +\n+\t\t\t((!!(ol_flags & PKT_TX_IPV6)) << 2) +\n+\t\t\t!!(ol_flags & PKT_TX_IP_CKSUM);\n+\n+\t\t/* Inner L4 */\n+\t\tw1.ol4type =  (ol_flags & PKT_TX_L4_MASK) >> 52;\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR &&\n+\t    flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n+\t\tsend_hdr_ext->w1.vlan1_ins_ena = !!(ol_flags & PKT_TX_VLAN);\n+\t\t/* HW will update ptr after vlan0 update */\n+\t\tsend_hdr_ext->w1.vlan1_ins_ptr = 12;\n+\t\tsend_hdr_ext->w1.vlan1_ins_tci = m->vlan_tci;\n+\n+\t\tsend_hdr_ext->w1.vlan0_ins_ena = !!(ol_flags & PKT_TX_QINQ);\n+\t\t/* 2B before end of l2 header */\n+\t\tsend_hdr_ext->w1.vlan0_ins_ptr = 12;\n+\t\tsend_hdr_ext->w1.vlan0_ins_tci = m->vlan_tci_outer;\n+\t}\n+\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1)\n+\t\tsend_hdr->w1.u = w1.u;\n+\n+\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n+\t\tsg->seg1_size = m->data_len;\n+\t\t*(rte_iova_t *)(++sg) = rte_mbuf_data_iova(m);\n+\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n+\t\t\t/* Set don't free bit if reference count > 1 */\n+\t\t\tif (rte_pktmbuf_prefree_seg(m) == NULL)\n+\t\t\t\tsend_hdr->w0.df = 1; /* SET DF */\n+\t\t}\n+\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+\t\tif (!send_hdr->w0.df)\n+\t\t\t__mempool_check_cookies(m->pool, (void **)&m, 1, 0);\n+\t}\n+}\n+\n+\n+static __rte_always_inline void\n+otx2_nix_xmit_one(uint64_t *cmd, void *lmt_addr,\n+\t\t  const rte_iova_t io_addr, const uint32_t flags)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\totx2_lmt_mov(lmt_addr, cmd, otx2_nix_tx_ext_subs(flags));\n+\t\tlmt_status = otx2_lmt_submit(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n+\n+#define L3L4CSUM_F   NIX_TX_OFFLOAD_L3_L4_CSUM_F\n+#define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n+#define VLAN_F       NIX_TX_OFFLOAD_VLAN_QINQ_F\n+#define NOFF_F       NIX_TX_OFFLOAD_MBUF_NOFF_F\n+#define TSP_F        NIX_TX_OFFLOAD_TSTAMP_F\n+\n+/* [TSTMP] [NOFF] [VLAN] [OL3OL4CSUM] [L3L4CSUM] */\n+#define NIX_TX_FASTPATH_MODES\t\t\t\t\t\\\n+T(no_offload,\t\t\t\t0, 0, 0, 0, 0,\t4,\t\\\n+\t\tNIX_TX_OFFLOAD_NONE)\t\t\t\t\\\n+T(l3l4csum,\t\t\t\t0, 0, 0, 0, 1,\t4,\t\\\n+\t\tL3L4CSUM_F)\t\t\t\t\t\\\n+T(ol3ol4csum,\t\t\t\t0, 0, 0, 1, 0,\t4,\t\\\n+\t\tOL3OL4CSUM_F)\t\t\t\t\t\\\n+T(ol3ol4csum_l3l4csum,\t\t\t0, 0, 0, 1, 1,\t4,\t\\\n+\t\tOL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\\\n+T(vlan,\t\t\t\t\t0, 0, 1, 0, 0,\t6,\t\\\n+\t\tVLAN_F)\t\t\t\t\t\t\\\n+T(vlan_l3l4csum,\t\t\t0, 0, 1, 0, 1,\t6,\t\\\n+\t\tVLAN_F | L3L4CSUM_F)\t\t\t\t\\\n+T(vlan_ol3ol4csum,\t\t\t0, 0, 1, 1, 0,\t6,\t\\\n+\t\tVLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(vlan_ol3ol4csum_l3l4csum,\t\t0, 0, 1, 1, 1,\t6,\t\\\n+\t\tVLAN_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n+T(noff,\t\t\t\t\t0, 1, 0, 0, 0,\t4,\t\\\n+\t\tNOFF_F)\t\t\t\t\t\t\\\n+T(noff_l3l4csum,\t\t\t0, 1, 0, 0, 1,\t4,\t\\\n+\t\tNOFF_F | L3L4CSUM_F)\t\t\t\t\\\n+T(noff_ol3ol4csum,\t\t\t0, 1, 0, 1, 0,\t4,\t\\\n+\t\tNOFF_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(noff_ol3ol4csum_l3l4csum,\t\t0, 1, 0, 1, 1,\t4,\t\\\n+\t\tNOFF_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n+T(noff_vlan,\t\t\t\t0, 1, 1, 0, 0,\t6,\t\\\n+\t\tNOFF_F | VLAN_F)\t\t\t\t\\\n+T(noff_vlan_l3l4csum,\t\t\t0, 1, 1, 0, 1,\t6,\t\\\n+\t\tNOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n+T(noff_vlan_ol3ol4csum,\t\t\t0, 1, 1, 1, 0,\t6,\t\\\n+\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n+T(noff_vlan_ol3ol4csum_l3l4csum,\t0, 1, 1, 1, 1,\t6,\t\\\n+\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n+T(ts,\t\t\t\t\t1, 0, 0, 0, 0,\t8,\t\\\n+\t\tTSP_F)\t\t\t\t\t\t\\\n+T(ts_l3l4csum,\t\t\t1, 0, 0, 0, 1,\t8,\t\t\\\n+\t\tTSP_F | L3L4CSUM_F)\t\t\t\t\\\n+T(ts_ol3ol4csum,\t\t\t1, 0, 0, 1, 0,\t8,\t\\\n+\t\tTSP_F | OL3OL4CSUM_F)\t\t\t\t\\\n+T(ts_ol3ol4csum_l3l4csum,\t\t1, 0, 0, 1, 1,\t8,\t\\\n+\t\tTSP_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n+T(ts_vlan,\t\t\t\t1, 0, 1, 0, 0,\t8,\t\\\n+\t\tTSP_F | VLAN_F)\t\t\t\t\t\\\n+T(ts_vlan_l3l4csum,\t\t\t1, 0, 1, 0, 1,\t8,\t\\\n+\t\tTSP_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n+T(ts_vlan_ol3ol4csum,\t\t1, 0, 1, 1, 0,\t8,\t\t\\\n+\t\tTSP_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n+T(ts_vlan_ol3ol4csum_l3l4csum,\t1, 0, 1, 1, 1,\t8,\t\t\\\n+\t\tTSP_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n+T(ts_noff,\t\t\t\t1, 1, 0, 0, 0,\t8,\t\\\n+\t\tTSP_F | NOFF_F)\t\t\t\t\t\\\n+T(ts_noff_l3l4csum,\t\t\t1, 1, 0, 0, 1,\t8,\t\\\n+\t\tTSP_F | NOFF_F | L3L4CSUM_F)\t\t\t\\\n+T(ts_noff_ol3ol4csum,\t\t1, 1, 0, 1, 0,\t8,\t\t\\\n+\t\tTSP_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\\\n+T(ts_noff_ol3ol4csum_l3l4csum,\t1, 1, 0, 1, 1,\t8,\t\t\\\n+\t\tTSP_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n+T(ts_noff_vlan,\t\t\t1, 1, 1, 0, 0,\t8,\t\t\\\n+\t\tTSP_F | NOFF_F | VLAN_F)\t\t\t\\\n+T(ts_noff_vlan_l3l4csum,\t\t1, 1, 1, 0, 1,\t8,\t\\\n+\t\tTSP_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\\\n+T(ts_noff_vlan_ol3ol4csum,\t\t1, 1, 1, 1, 0,\t8,\t\\\n+\t\tTSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\\\n+T(ts_noff_vlan_ol3ol4csum_l3l4csum,\t1, 1, 1, 1, 1,\t8,\t\\\n+\t\tTSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\n+\n #endif /* __OTX2_TX_H__ */\n",
    "prefixes": [
        "v2",
        "51/57"
    ]
}