Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/55723/?format=api
{ "id": 55723, "url": "http://patches.dpdk.org/api/patches/55723/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-51-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-51-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-51-jerinj@marvell.com", "date": "2019-06-30T18:06:02", "name": "[v2,50/57] net/octeontx2: add Rx vector version", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "25ef4db591af6de34ff85b8652749d02ac3058e6", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-51-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55723/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55723/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 60A8B1B9FA;\n\tSun, 30 Jun 2019 20:12:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 41D231B9CF\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:09:07 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI54j5027147; Sun, 30 Jun 2019 11:09:06 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2te5bn4gp2-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 30 Jun 2019 11:09:06 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:09:05 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:09:05 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 64A3D3F7045;\n\tSun, 30 Jun 2019 11:09:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : subject\n\t: date : message-id : in-reply-to : references : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=LCTIHkf5d8CaoI2cZICYnM6UO/yzbUQweAhJqmzTsFo=;\n\tb=mZI3NAeTDqKD2jj0+X/KoqZOv7727IaD2z4MpK1iAIt8mTNsIInGh87VA8FACC5q2XOR\n\tjHiBSWl9wl5gHoqgqGiMYeV6tF7/QwVKYhGrglLGRvccAuZbZmWSRDpx+3uggeO0bFqQ\n\tihWoAiKikAoBeZlMN/CLaWCyLwLHcMRSplSb/bZwsg9Kya5ghvBW8ksXq74gZB164fxV\n\tlLkyNYcjdI1L+WKI5QHZIgnWbVc86CKzQBnVLitE60RiDfEcI1LVPNlJpTDsydakt7Sm\n\ta0L1995TMoDcOmmAnpltOjAmXX3SvlwMlWukeK6QeO8Hh8MXMRDq6q6NOgNaiVlbHDNF\n\tow== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>", "Date": "Sun, 30 Jun 2019 23:36:02 +0530", "Message-ID": "<20190630180609.36705-51-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 50/57] net/octeontx2: add Rx vector version", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd vector version of packet Receive function.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/octeontx2.rst | 1 +\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 2 +\n drivers/net/octeontx2/otx2_rx.c | 259 +++++++++++++++++++++++++++++-\n 4 files changed, 262 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex 3d9fc5f1d..9d6596ad8 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -30,6 +30,7 @@ Features of the OCTEON TX2 Ethdev PMD are:\n - Link state information\n - Link flow control\n - Scatter-Gather IO support\n+- Vector Poll mode driver\n - Debug utilities - Context dump and error interrupt support\n - IEEE1588 timestamping\n \ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 3e25d2ad4..a5f125655 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -14,6 +14,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2\n CFLAGS += -O3\n+CFLAGS += -flax-vector-conversions\n \n ifneq ($(CONFIG_RTE_ARCH_64),y)\n CFLAGS += -Wno-int-to-pointer-cast\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 975b2e715..9d151f88d 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -24,6 +24,8 @@ sources = files('otx2_rx.c',\n \n deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2']\n \n+cflags += ['-flax-vector-conversions']\n+\n extra_flags = []\n # This integrated controller runs only on a arm64 machine, remove 32bit warnings\n if not dpdk_conf.get('RTE_ARCH_64')\ndiff --git a/drivers/net/octeontx2/otx2_rx.c b/drivers/net/octeontx2/otx2_rx.c\nindex fca182785..deefe9588 100644\n--- a/drivers/net/octeontx2/otx2_rx.c\n+++ b/drivers/net/octeontx2/otx2_rx.c\n@@ -84,6 +84,239 @@ nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \treturn nb_pkts;\n }\n \n+#if defined(RTE_ARCH_ARM64)\n+\n+static __rte_always_inline uint64_t\n+nix_vlan_update(const uint64_t w2, uint64_t ol_flags, uint8x16_t *f)\n+{\n+\tif (w2 & BIT_ULL(21) /* vtag0_gone */) {\n+\t\tol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;\n+\t\t*f = vsetq_lane_u16((uint16_t)(w2 >> 32), *f, 5);\n+\t}\n+\n+\treturn ol_flags;\n+}\n+\n+static __rte_always_inline uint64_t\n+nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)\n+{\n+\tif (w2 & BIT_ULL(23) /* vtag1_gone */) {\n+\t\tol_flags |= PKT_RX_QINQ | PKT_RX_QINQ_STRIPPED;\n+\t\tmbuf->vlan_tci_outer = (uint16_t)(w2 >> 48);\n+\t}\n+\n+\treturn ol_flags;\n+}\n+\n+static __rte_always_inline uint16_t\n+nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t uint16_t pkts, const uint16_t flags)\n+{\n+\tstruct otx2_eth_rxq *rxq = rx_queue; uint16_t packets = 0;\n+\tuint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;\n+\tconst uint64_t mbuf_initializer = rxq->mbuf_initializer;\n+\tconst uint64x2_t data_off = vdupq_n_u64(rxq->data_off);\n+\tuint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;\n+\tuint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n+\tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n+\tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n+\tconst uint16_t *lookup_mem = rxq->lookup_mem;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uintptr_t desc = rxq->desc;\n+\tuint8x16_t f0, f1, f2, f3;\n+\tuint32_t head = rxq->head;\n+\n+\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n+\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n+\n+\twhile (packets < pkts) {\n+\t\t/* Get the CQ pointers, since the ring size is multiple of\n+\t\t * 4, We can avoid checking the wrap around of head\n+\t\t * value after the each access unlike scalar version.\n+\t\t */\n+\t\tconst uintptr_t cq0 = desc + CQE_SZ(head);\n+\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));\n+\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));\n+\n+\t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n+\t\tcq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));\n+\t\tcq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));\n+\t\tcq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));\n+\t\tcq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));\n+\n+\t\t/* Extract mbuf from NIX_RX_SG_S */\n+\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n+\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n+\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n+\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n+\n+\t\t/* Move mbufs to scalar registers for future use */\n+\t\tmbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);\n+\t\tmbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);\n+\t\tmbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);\n+\t\tmbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);\n+\n+\t\t/* Mask to get packet len from NIX_RX_SG_S */\n+\t\tconst uint8x16_t shuf_msk = {\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n+\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n+\t\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n+\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n+\t\t\t0xFF, 0xFF,\n+\t\t\t0xFF, 0xFF, 0xFF, 0xFF\n+\t\t\t};\n+\n+\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n+\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n+\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n+\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n+\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n+\n+\t\t/* Load CQE word0 and word 1 */\n+\t\tuint64x2_t cq0_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0)));\n+\t\tuint64x2_t cq1_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1)));\n+\t\tuint64x2_t cq2_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2)));\n+\t\tuint64x2_t cq3_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3)));\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n+\t\t\t/* Fill rss in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(vgetq_lane_u32(cq0_w0, 0), f0, 3);\n+\t\t\tf1 = vsetq_lane_u32(vgetq_lane_u32(cq1_w0, 0), f1, 3);\n+\t\t\tf2 = vsetq_lane_u32(vgetq_lane_u32(cq2_w0, 0), f2, 3);\n+\t\t\tf3 = vsetq_lane_u32(vgetq_lane_u32(cq3_w0, 0), f3, 3);\n+\t\t\tol_flags0 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags1 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags2 = PKT_RX_RSS_HASH;\n+\t\t\tol_flags3 = PKT_RX_RSS_HASH;\n+\t\t} else {\n+\t\t\tol_flags0 = 0; ol_flags1 = 0;\n+\t\t\tol_flags2 = 0; ol_flags3 = 0;\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_PTYPE_F) {\n+\t\t\t/* Fill packet_type in the rx_descriptor_fields1 */\n+\t\t\tf0 = vsetq_lane_u32(nix_ptype_get(lookup_mem,\n+\t\t\t\t\t vgetq_lane_u64(cq0_w0, 1)), f0, 0);\n+\t\t\tf1 = vsetq_lane_u32(nix_ptype_get(lookup_mem,\n+\t\t\t\t\t vgetq_lane_u64(cq1_w0, 1)), f1, 0);\n+\t\t\tf2 = vsetq_lane_u32(nix_ptype_get(lookup_mem,\n+\t\t\t\t\t vgetq_lane_u64(cq2_w0, 1)), f2, 0);\n+\t\t\tf3 = vsetq_lane_u32(nix_ptype_get(lookup_mem,\n+\t\t\t\t\t vgetq_lane_u64(cq3_w0, 1)), f3, 0);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {\n+\t\t\tol_flags0 |= nix_rx_olflags_get(lookup_mem,\n+\t\t\t\t\t\tvgetq_lane_u64(cq0_w0, 1));\n+\t\t\tol_flags1 |= nix_rx_olflags_get(lookup_mem,\n+\t\t\t\t\t\tvgetq_lane_u64(cq1_w0, 1));\n+\t\t\tol_flags2 |= nix_rx_olflags_get(lookup_mem,\n+\t\t\t\t\t\tvgetq_lane_u64(cq2_w0, 1));\n+\t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem,\n+\t\t\t\t\t\tvgetq_lane_u64(cq3_w0, 1));\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n+\t\t\tuint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);\n+\t\t\tuint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);\n+\t\t\tuint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16);\n+\t\t\tuint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16);\n+\n+\t\t\tol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0);\n+\t\t\tol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1);\n+\t\t\tol_flags2 = nix_vlan_update(cq2_w2, ol_flags2, &f2);\n+\t\t\tol_flags3 = nix_vlan_update(cq3_w2, ol_flags3, &f3);\n+\n+\t\t\tol_flags0 = nix_qinq_update(cq0_w2, ol_flags0, mbuf0);\n+\t\t\tol_flags1 = nix_qinq_update(cq1_w2, ol_flags1, mbuf1);\n+\t\t\tol_flags2 = nix_qinq_update(cq2_w2, ol_flags2, mbuf2);\n+\t\t\tol_flags3 = nix_qinq_update(cq3_w2, ol_flags3, mbuf3);\n+\t\t}\n+\n+\t\tif (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {\n+\t\t\tol_flags0 = nix_update_match_id(*(uint16_t *)\n+\t\t\t\t (cq0 + CQE_SZ(0) + 38), ol_flags0, mbuf0);\n+\t\t\tol_flags1 = nix_update_match_id(*(uint16_t *)\n+\t\t\t\t (cq0 + CQE_SZ(1) + 38), ol_flags1, mbuf1);\n+\t\t\tol_flags2 = nix_update_match_id(*(uint16_t *)\n+\t\t\t\t (cq0 + CQE_SZ(2) + 38), ol_flags2, mbuf2);\n+\t\t\tol_flags3 = nix_update_match_id(*(uint16_t *)\n+\t\t\t\t (cq0 + CQE_SZ(3) + 38), ol_flags3, mbuf3);\n+\t\t}\n+\n+\t\t/* Form rearm_data with ol_flags */\n+\t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n+\t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n+\t\trearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);\n+\t\trearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);\n+\n+\t\t/* Update rx_descriptor_fields1 */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);\n+\n+\t\t/* Update rearm_data */\n+\t\tvst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);\n+\t\tvst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);\n+\t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n+\t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n+\n+\t\t/* Store the mbufs to rx_pkts */\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n+\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n+\n+\t\t/* Prefetch mbufs */\n+\t\totx2_prefetch_store_keep(mbuf0);\n+\t\totx2_prefetch_store_keep(mbuf1);\n+\t\totx2_prefetch_store_keep(mbuf2);\n+\t\totx2_prefetch_store_keep(mbuf3);\n+\n+\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t\t__mempool_check_cookies(mbuf0->pool, (void **)&mbuf0, 1, 1);\n+\t\t__mempool_check_cookies(mbuf1->pool, (void **)&mbuf1, 1, 1);\n+\t\t__mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);\n+\t\t__mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);\n+\n+\t\t/* Advance head pointer and packets */\n+\t\thead += NIX_DESCS_PER_LOOP; head &= qmask;\n+\t\tpackets += NIX_DESCS_PER_LOOP;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= packets;\n+\n+\trte_cio_wmb();\n+\t/* Free all the CQs that we've processed */\n+\totx2_write64((rxq->wdata | packets), rxq->cq_door);\n+\n+\treturn packets;\n+}\n+\n+#else\n+\n+static inline uint16_t\n+nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t uint16_t pkts, const uint16_t flags)\n+{\n+\tRTE_SET_USED(rx_queue);\n+\tRTE_SET_USED(rx_pkts);\n+\tRTE_SET_USED(pkts);\n+\tRTE_SET_USED(flags);\n+\n+\treturn 0;\n+}\n+\n+#endif\n \n #define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t\\\n static uint16_t __rte_noinline\t__hot\t\t\t\t\t \\\n@@ -100,6 +333,16 @@ otx2_nix_recv_pkts_mseg_ ## name(void *rx_queue,\t\t\t \\\n \treturn nix_recv_pkts(rx_queue, rx_pkts, pkts,\t\t\t \\\n \t\t\t (flags) | NIX_RX_MULTI_SEG_F);\t\t \\\n }\t\t\t\t\t\t\t\t\t \\\n+\t\t\t\t\t\t\t\t\t \\\n+static uint16_t __rte_noinline\t__hot\t\t\t\t\t \\\n+otx2_nix_recv_pkts_vec_ ## name(void *rx_queue,\t\t\t\t \\\n+\t\t\tstruct rte_mbuf **rx_pkts, uint16_t pkts)\t \\\n+{\t\t\t\t\t\t\t\t\t \\\n+\t/* TSTMP is not supported by vector */\t\t\t\t \\\n+\tif ((flags) & NIX_RX_OFFLOAD_TSTAMP_F)\t\t\t\t \\\n+\t\treturn 0;\t\t\t\t\t\t \\\n+\treturn nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, (flags));\t \\\n+}\t\t\t\t\t\t\t\t\t \\\n \n NIX_RX_FASTPATH_MODES\n #undef R\n@@ -141,7 +384,21 @@ NIX_RX_FASTPATH_MODES\n #undef R\n \t};\n \n-\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t\\\n+\t[f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_vec_ ## name,\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\t/* For PTP enabled, scalar rx function should be chosen as most of the\n+\t * PTP apps are implemented to rx burst 1 pkt.\n+\t */\n+\tif (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\telse\n+\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n \n \tif (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\n \t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n", "prefixes": [ "v2", "50/57" ] }