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GET /api/patches/55718/?format=api
{ "id": 55718, "url": "http://patches.dpdk.org/api/patches/55718/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-33-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-33-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-33-jerinj@marvell.com", "date": "2019-06-30T18:05:44", "name": "[v2,32/57] net/octeontx2: introducing flow driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2bfc7404cd1072e684fffc83c9e95e6415335bfb", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-33-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55718/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55718/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 46FD81BBEE;\n\tSun, 30 Jun 2019 20:11:08 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0449C1B9C6\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:08:13 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI6fu7028350 for <dev@dpdk.org>; Sun, 30 Jun 2019 11:08:13 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2te5bn4gkm-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 11:08:13 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:08:11 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:08:12 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 5D5743F703F;\n\tSun, 30 Jun 2019 11:08:10 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=iiCWDZmt05afuE8I17iWwoAVhf05gu2V2fNfTt8XJI8=;\n\tb=B5ffTVu//z2pMWuOXe1jAT11S9OaNgGeZKeMZZD2S4wz7HTLUv39elSGRsAawCq2W1AN\n\tUsZ0qx03aUN1kuCt6y7TbHHQBXiRWu7tUVkwTV1oqN2TUscv/ude1Nxy/kwuzj2TAL2l\n\t8rSLLQ5yQ0oUailqdCPnmsiRXybGT9hdhL8fLd1ynL4KIeroytHwDYJT2/DQGb6iGCZn\n\tliAmhfwCq3hSgs+/ATAb/lWgpSeadV6Eu1z3Xj4pOztKlNBLzahpBxSnEpIPkHr9cVzm\n\tzxTcAIxX87uY6Wmy7qcGK8qlm42CFb02ahNVtuH06hsmMc+PeboNsdscROtZ6lF+dEJk\n\t4w== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Vivek Sharma <viveksharma@marvell.com>", "Date": "Sun, 30 Jun 2019 23:35:44 +0530", "Message-ID": "<20190630180609.36705-33-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 32/57] net/octeontx2: introducing flow driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nIntroducing flow infra for octeontx2.\nThis will be used to maintain rte_flow rules.\n\nCreate, destroy, validate, query, flush, isolate flow operations\nwill be supported.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vivek Sharma <viveksharma@marvell.com>\n---\n drivers/net/octeontx2/otx2_flow.h | 388 ++++++++++++++++++++++++++++++\n 1 file changed, 388 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_flow.h", "diff": "diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h\nnew file mode 100644\nindex 000000000..95bb6c2bf\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_flow.h\n@@ -0,0 +1,388 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_FLOW_H__\n+#define __OTX2_FLOW_H__\n+\n+#include <stdint.h>\n+\n+#include <rte_flow_driver.h>\n+#include <rte_malloc.h>\n+#include <rte_tailq.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_ethdev.h\"\n+#include \"otx2_mbox.h\"\n+\n+int otx2_flow_init(struct otx2_eth_dev *hw);\n+int otx2_flow_fini(struct otx2_eth_dev *hw);\n+extern const struct rte_flow_ops otx2_flow_ops;\n+\n+enum {\n+\tOTX2_INTF_RX = 0,\n+\tOTX2_INTF_TX = 1,\n+\tOTX2_INTF_MAX = 2,\n+};\n+\n+#define NPC_IH_LENGTH\t\t\t8\n+#define NPC_TPID_LENGTH\t\t\t2\n+#define NPC_COUNTER_NONE\t\t(-1)\n+/* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */\n+#define NPC_MAX_EXTRACT_DATA_LEN\t(64)\n+#define NPC_LDATA_LFLAG_LEN\t\t(16)\n+#define NPC_MCAM_TOT_ENTRIES\t\t(4096)\n+#define NPC_MAX_KEY_NIBBLES\t\t(31)\n+/* Nibble offsets */\n+#define NPC_LAYER_KEYX_SZ\t\t(3)\n+#define NPC_PARSE_KEX_S_LA_OFFSET\t(7)\n+#define NPC_PARSE_KEX_S_LID_OFFSET(lid)\t\t\\\n+\t((((lid) - NPC_LID_LA) * NPC_LAYER_KEYX_SZ) \\\n+\t+ NPC_PARSE_KEX_S_LA_OFFSET)\n+\n+\n+/* supported flow actions flags */\n+#define OTX2_FLOW_ACT_MARK (1 << 0)\n+#define OTX2_FLOW_ACT_FLAG (1 << 1)\n+#define OTX2_FLOW_ACT_DROP (1 << 2)\n+#define OTX2_FLOW_ACT_QUEUE (1 << 3)\n+#define OTX2_FLOW_ACT_RSS (1 << 4)\n+#define OTX2_FLOW_ACT_DUP (1 << 5)\n+#define OTX2_FLOW_ACT_SEC (1 << 6)\n+#define OTX2_FLOW_ACT_COUNT (1 << 7)\n+\n+/* terminating actions */\n+#define OTX2_FLOW_ACT_TERM (OTX2_FLOW_ACT_DROP | \\\n+\t\t\t OTX2_FLOW_ACT_QUEUE | \\\n+\t\t\t OTX2_FLOW_ACT_RSS | \\\n+\t\t\t OTX2_FLOW_ACT_DUP | \\\n+\t\t\t OTX2_FLOW_ACT_SEC)\n+\n+/* This mark value indicates flag action */\n+#define OTX2_FLOW_FLAG_VAL (0xffff)\n+\n+#define NIX_RX_ACT_MATCH_OFFSET\t\t(40)\n+#define NIX_RX_ACT_MATCH_MASK\t\t(0xFFFF)\n+\n+#define NIX_RSS_ACT_GRP_OFFSET\t\t(20)\n+#define NIX_RSS_ACT_ALG_OFFSET\t\t(56)\n+#define NIX_RSS_ACT_GRP_MASK\t\t(0xFFFFF)\n+#define NIX_RSS_ACT_ALG_MASK\t\t(0x1F)\n+\n+/* PMD-specific definition of the opaque struct rte_flow */\n+#define OTX2_MAX_MCAM_WIDTH_DWORDS\t7\n+\n+enum npc_mcam_intf {\n+\tNPC_MCAM_RX,\n+\tNPC_MCAM_TX\n+};\n+\n+struct npc_xtract_info {\n+\t/* Length in bytes of pkt data extracted. len = 0\n+\t * indicates that extraction is disabled.\n+\t */\n+\tuint8_t len;\n+\tuint8_t hdr_off; /* Byte offset of proto hdr: extract_src */\n+\tuint8_t key_off; /* Byte offset in MCAM key where data is placed */\n+\tuint8_t enable; /* Extraction enabled or disabled */\n+};\n+\n+/* Information for a given {LAYER, LTYPE} */\n+struct npc_lid_lt_xtract_info {\n+\t/* Info derived from parser configuration */\n+\tuint16_t npc_proto; /* Network protocol identified */\n+\tuint8_t valid_flags_mask; /* Flags applicable */\n+\tuint8_t is_terminating:1; /* No more parsing */\n+\tstruct npc_xtract_info xtract[NPC_MAX_LD];\n+};\n+\n+union npc_kex_ldata_flags_cfg {\n+\tstruct {\n+\t#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\tuint64_t rvsd_62_1\t: 61;\n+\t\tuint64_t lid\t\t: 3;\n+\t#else\n+\t\tuint64_t lid\t\t: 3;\n+\t\tuint64_t rvsd_62_1\t: 61;\n+\t#endif\n+\t} s;\n+\n+\tuint64_t i;\n+};\n+\n+typedef struct npc_lid_lt_xtract_info\n+\totx2_dxcfg_t[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT];\n+typedef struct npc_lid_lt_xtract_info\n+\totx2_fxcfg_t[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];\n+typedef union npc_kex_ldata_flags_cfg otx2_ld_flags_t[NPC_MAX_LD];\n+\n+\n+/* MBOX_MSG_NPC_GET_DATAX_CFG Response */\n+struct npc_get_datax_cfg {\n+\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n+\tunion npc_kex_ldata_flags_cfg ld_flags[NPC_MAX_LD];\n+\t/* Extract information indexed with [LID][LTYPE] */\n+\tstruct npc_lid_lt_xtract_info lid_lt_xtract[NPC_MAX_LID][NPC_MAX_LT];\n+\t/* Flags based extract indexed with [LDATA][FLAGS_LOWER_NIBBLE]\n+\t * Fields flags_ena_ld0, flags_ena_ld1 in\n+\t * struct npc_lid_lt_xtract_info indicate if this is applicable\n+\t * for a given {LAYER, LTYPE}\n+\t */\n+\tstruct npc_xtract_info flag_xtract[NPC_MAX_LD][NPC_MAX_LT];\n+};\n+\n+struct otx2_mcam_ents_info {\n+\t/* Current max & min values of mcam index */\n+\tuint32_t max_id;\n+\tuint32_t min_id;\n+\tuint32_t free_ent;\n+\tuint32_t live_ent;\n+};\n+\n+struct rte_flow {\n+\tuint8_t nix_intf;\n+\tuint32_t mcam_id;\n+\tint32_t ctr_id;\n+\tuint32_t priority;\n+\t/* Contiguous match string */\n+\tuint64_t mcam_data[OTX2_MAX_MCAM_WIDTH_DWORDS];\n+\tuint64_t mcam_mask[OTX2_MAX_MCAM_WIDTH_DWORDS];\n+\tuint64_t npc_action;\n+\tTAILQ_ENTRY(rte_flow) next;\n+};\n+\n+TAILQ_HEAD(otx2_flow_list, rte_flow);\n+\n+/* Accessed from ethdev private - otx2_eth_dev */\n+struct otx2_npc_flow_info {\n+\trte_atomic32_t mark_actions;\n+\tuint32_t keyx_supp_nmask[NPC_MAX_INTF];/* nibble mask */\n+\tuint32_t keyx_len[NPC_MAX_INTF];\t/* per intf key len in bits */\n+\tuint32_t datax_len[NPC_MAX_INTF];\t/* per intf data len in bits */\n+\tuint32_t keyw[NPC_MAX_INTF];\t\t/* max key + data len bits */\n+\tuint32_t mcam_entries;\t\t\t/* mcam entries supported */\n+\totx2_dxcfg_t prx_dxcfg;\t\t\t/* intf, lid, lt, extract */\n+\totx2_fxcfg_t prx_fxcfg;\t\t\t/* Flag extract */\n+\totx2_ld_flags_t prx_lfcfg;\t\t/* KEX LD_Flags CFG */\n+\t/* mcam entry info per priority level: both free & in-use */\n+\tstruct otx2_mcam_ents_info *flow_entry_info;\n+\t/* Bitmap of free preallocated entries in ascending index &\n+\t * descending priority\n+\t */\n+\tstruct rte_bitmap **free_entries;\n+\t/* Bitmap of free preallocated entries in descending index &\n+\t * ascending priority\n+\t */\n+\tstruct rte_bitmap **free_entries_rev;\n+\t/* Bitmap of live entries in ascending index & descending priority */\n+\tstruct rte_bitmap **live_entries;\n+\t/* Bitmap of live entries in descending index & ascending priority */\n+\tstruct rte_bitmap **live_entries_rev;\n+\t/* Priority bucket wise tail queue of all rte_flow resources */\n+\tstruct otx2_flow_list *flow_list;\n+\tuint32_t rss_grps; /* rss groups supported */\n+\tstruct rte_bitmap *rss_grp_entries;\n+\tuint16_t channel; /*rx channel */\n+\tuint16_t flow_prealloc_size;\n+\tuint16_t flow_max_priority;\n+};\n+\n+struct otx2_parse_state {\n+\tstruct otx2_npc_flow_info *npc;\n+\tconst struct rte_flow_item *pattern;\n+\tconst struct rte_flow_item *last_pattern; /* Temp usage */\n+\tstruct rte_flow_error *error;\n+\tstruct rte_flow *flow;\n+\tuint8_t tunnel;\n+\tuint8_t terminate;\n+\tuint8_t layer_mask;\n+\tuint8_t lt[NPC_MAX_LID];\n+\tuint8_t flags[NPC_MAX_LID];\n+\tuint8_t *mcam_data; /* point to flow->mcam_data + key_len */\n+\tuint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */\n+};\n+\n+struct otx2_flow_item_info {\n+\tconst void *def_mask; /* rte_flow default mask */\n+\tvoid *hw_mask; /* hardware supported mask */\n+\tint len; /* length of item */\n+\tconst void *spec; /* spec to use, NULL implies match any */\n+\tconst void *mask; /* mask to use */\n+\tuint8_t hw_hdr_len; /* Extra data len at each layer*/\n+};\n+\n+struct otx2_idev_kex_cfg {\n+\tstruct npc_get_kex_cfg_rsp kex_cfg;\n+\trte_atomic16_t kex_refcnt;\n+};\n+\n+enum npc_kpu_parser_flag {\n+\tNPC_F_NA = 0,\n+\tNPC_F_PKI,\n+\tNPC_F_PKI_VLAN,\n+\tNPC_F_PKI_ETAG,\n+\tNPC_F_PKI_ITAG,\n+\tNPC_F_PKI_MPLS,\n+\tNPC_F_PKI_NSH,\n+\tNPC_F_ETYPE_UNK,\n+\tNPC_F_ETHER_VLAN,\n+\tNPC_F_ETHER_ETAG,\n+\tNPC_F_ETHER_ITAG,\n+\tNPC_F_ETHER_MPLS,\n+\tNPC_F_ETHER_NSH,\n+\tNPC_F_STAG_CTAG,\n+\tNPC_F_STAG_CTAG_UNK,\n+\tNPC_F_STAG_STAG_CTAG,\n+\tNPC_F_STAG_STAG_STAG,\n+\tNPC_F_QINQ_CTAG,\n+\tNPC_F_QINQ_CTAG_UNK,\n+\tNPC_F_QINQ_QINQ_CTAG,\n+\tNPC_F_QINQ_QINQ_QINQ,\n+\tNPC_F_BTAG_ITAG,\n+\tNPC_F_BTAG_ITAG_STAG,\n+\tNPC_F_BTAG_ITAG_CTAG,\n+\tNPC_F_BTAG_ITAG_UNK,\n+\tNPC_F_ETAG_CTAG,\n+\tNPC_F_ETAG_BTAG_ITAG,\n+\tNPC_F_ETAG_STAG,\n+\tNPC_F_ETAG_QINQ,\n+\tNPC_F_ETAG_ITAG,\n+\tNPC_F_ETAG_ITAG_STAG,\n+\tNPC_F_ETAG_ITAG_CTAG,\n+\tNPC_F_ETAG_ITAG_UNK,\n+\tNPC_F_ITAG_STAG_CTAG,\n+\tNPC_F_ITAG_STAG,\n+\tNPC_F_ITAG_CTAG,\n+\tNPC_F_MPLS_4_LABELS,\n+\tNPC_F_MPLS_3_LABELS,\n+\tNPC_F_MPLS_2_LABELS,\n+\tNPC_F_IP_HAS_OPTIONS,\n+\tNPC_F_IP_IP_IN_IP,\n+\tNPC_F_IP_6TO4,\n+\tNPC_F_IP_MPLS_IN_IP,\n+\tNPC_F_IP_UNK_PROTO,\n+\tNPC_F_IP_IP_IN_IP_HAS_OPTIONS,\n+\tNPC_F_IP_6TO4_HAS_OPTIONS,\n+\tNPC_F_IP_MPLS_IN_IP_HAS_OPTIONS,\n+\tNPC_F_IP_UNK_PROTO_HAS_OPTIONS,\n+\tNPC_F_IP6_HAS_EXT,\n+\tNPC_F_IP6_TUN_IP6,\n+\tNPC_F_IP6_MPLS_IN_IP,\n+\tNPC_F_TCP_HAS_OPTIONS,\n+\tNPC_F_TCP_HTTP,\n+\tNPC_F_TCP_HTTPS,\n+\tNPC_F_TCP_PPTP,\n+\tNPC_F_TCP_UNK_PORT,\n+\tNPC_F_TCP_HTTP_HAS_OPTIONS,\n+\tNPC_F_TCP_HTTPS_HAS_OPTIONS,\n+\tNPC_F_TCP_PPTP_HAS_OPTIONS,\n+\tNPC_F_TCP_UNK_PORT_HAS_OPTIONS,\n+\tNPC_F_UDP_VXLAN,\n+\tNPC_F_UDP_VXLAN_NOVNI,\n+\tNPC_F_UDP_VXLAN_NOVNI_NSH,\n+\tNPC_F_UDP_VXLANGPE,\n+\tNPC_F_UDP_VXLANGPE_NSH,\n+\tNPC_F_UDP_VXLANGPE_MPLS,\n+\tNPC_F_UDP_VXLANGPE_NOVNI,\n+\tNPC_F_UDP_VXLANGPE_NOVNI_NSH,\n+\tNPC_F_UDP_VXLANGPE_NOVNI_MPLS,\n+\tNPC_F_UDP_VXLANGPE_UNK,\n+\tNPC_F_UDP_VXLANGPE_NONP,\n+\tNPC_F_UDP_GTP_GTPC,\n+\tNPC_F_UDP_GTP_GTPU_G_PDU,\n+\tNPC_F_UDP_GTP_GTPU_UNK,\n+\tNPC_F_UDP_UNK_PORT,\n+\tNPC_F_UDP_GENEVE,\n+\tNPC_F_UDP_GENEVE_OAM,\n+\tNPC_F_UDP_GENEVE_CRI_OPT,\n+\tNPC_F_UDP_GENEVE_OAM_CRI_OPT,\n+\tNPC_F_GRE_NVGRE,\n+\tNPC_F_GRE_HAS_SRE,\n+\tNPC_F_GRE_HAS_CSUM,\n+\tNPC_F_GRE_HAS_KEY,\n+\tNPC_F_GRE_HAS_SEQ,\n+\tNPC_F_GRE_HAS_CSUM_KEY,\n+\tNPC_F_GRE_HAS_CSUM_SEQ,\n+\tNPC_F_GRE_HAS_KEY_SEQ,\n+\tNPC_F_GRE_HAS_CSUM_KEY_SEQ,\n+\tNPC_F_GRE_HAS_ROUTE,\n+\tNPC_F_GRE_UNK_PROTO,\n+\tNPC_F_GRE_VER1,\n+\tNPC_F_GRE_VER1_HAS_SEQ,\n+\tNPC_F_GRE_VER1_HAS_ACK,\n+\tNPC_F_GRE_VER1_HAS_SEQ_ACK,\n+\tNPC_F_GRE_VER1_UNK_PROTO,\n+\tNPC_F_TU_ETHER_UNK,\n+\tNPC_F_TU_ETHER_CTAG,\n+\tNPC_F_TU_ETHER_CTAG_UNK,\n+\tNPC_F_TU_ETHER_STAG_CTAG,\n+\tNPC_F_TU_ETHER_STAG_CTAG_UNK,\n+\tNPC_F_TU_ETHER_STAG,\n+\tNPC_F_TU_ETHER_STAG_UNK,\n+\tNPC_F_TU_ETHER_QINQ_CTAG,\n+\tNPC_F_TU_ETHER_QINQ_CTAG_UNK,\n+\tNPC_F_TU_ETHER_QINQ,\n+\tNPC_F_TU_ETHER_QINQ_UNK,\n+\tNPC_F_LAST /* has to be the last item */\n+};\n+\n+\n+int otx2_flow_mcam_free_counter(struct otx2_mbox *mbox, uint16_t ctr_id);\n+\n+int otx2_flow_mcam_read_counter(struct otx2_mbox *mbox, uint32_t ctr_id,\n+\t\t\t\tuint64_t *count);\n+\n+int otx2_flow_mcam_clear_counter(struct otx2_mbox *mbox, uint32_t ctr_id);\n+\n+int otx2_flow_mcam_free_entry(struct otx2_mbox *mbox, uint32_t entry);\n+\n+int otx2_flow_mcam_free_all_entries(struct otx2_mbox *mbox);\n+\n+int otx2_flow_update_parse_state(struct otx2_parse_state *pst,\n+\t\t\t\t struct otx2_flow_item_info *info,\n+\t\t\t\t int lid, int lt, uint8_t flags);\n+\n+int otx2_flow_parse_item_basic(const struct rte_flow_item *item,\n+\t\t\t struct otx2_flow_item_info *info,\n+\t\t\t struct rte_flow_error *error);\n+\n+void otx2_flow_keyx_compress(uint64_t *data, uint32_t nibble_mask);\n+\n+int otx2_flow_mcam_alloc_and_write(struct rte_flow *flow,\n+\t\t\t\t struct otx2_mbox *mbox,\n+\t\t\t\t struct otx2_parse_state *pst,\n+\t\t\t\t struct otx2_npc_flow_info *flow_info);\n+\n+void otx2_flow_get_hw_supp_mask(struct otx2_parse_state *pst,\n+\t\t\t\tstruct otx2_flow_item_info *info,\n+\t\t\t\tint lid, int lt);\n+\n+const struct rte_flow_item *\n+otx2_flow_skip_void_and_any_items(const struct rte_flow_item *pattern);\n+\n+int otx2_flow_parse_lh(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_lg(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_lf(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_le(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_ld(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_lc(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_lb(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_la(struct otx2_parse_state *pst);\n+\n+int otx2_flow_parse_actions(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_flow_attr *attr,\n+\t\t\t const struct rte_flow_action actions[],\n+\t\t\t struct rte_flow_error *error,\n+\t\t\t struct rte_flow *flow);\n+\n+int otx2_flow_free_all_resources(struct otx2_eth_dev *hw);\n+\n+int otx2_flow_parse_mpls(struct otx2_parse_state *pst, int lid);\n+#endif /* __OTX2_FLOW_H__ */\n", "prefixes": [ "v2", "32/57" ] }