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GET /api/patches/55698/?format=api
{ "id": 55698, "url": "http://patches.dpdk.org/api/patches/55698/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-23-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-23-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-23-jerinj@marvell.com", "date": "2019-06-30T18:05:34", "name": "[v2,22/57] net/octeontx2: alloc and free TM HW resources", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2d8102e0e0c4abef2befe5656fd40b5a8ff36d72", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-23-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55698/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DBAE81BA68;\n\tSun, 30 Jun 2019 20:08:19 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D23A51B9E6\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:07:43 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI640t016301 for <dev@dpdk.org>; Sun, 30 Jun 2019 11:07:43 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2te7gm3yan-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 11:07:43 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:07:41 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:07:41 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 706273F703F;\n\tSun, 30 Jun 2019 11:07:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=ZjXhgFVEu4kYcft6J/VFZjSZcNANJ/iTLYSxZ3MhKVE=;\n\tb=rnmP9YoRnXSuclR2e1E/dYsWDY1eD46wW6v3OHW7NfiMixbGCpV+VVOQ08S/Y4aPDmKp\n\tcG71/waAt9jMKRoevFSTfx2Wo2NckGPNMzxdodsDffuiBZ8IKKHCu72SlXCbLIlDwGQY\n\tEh2dVUyhPwxhxL96Tg+TEjG5PRcG6fBznPqVOT0RI60Q6U0TQe4K0v2hsERab+93RDr5\n\tSWH8MzkPR2KFHhw55Zw0OqcnKAwlwjLC+Jm5arg9r4GHNJyLMiTpzywwbuiirtRKYvvb\n\tYB8cwpMtYUPoGZw0UDI1yOobHK8NRximIhXewysCNQEdhe82hz1n53Fb5f2XB1YtOgRu\n\tzg== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Krzysztof Kanas <kkanas@marvell.com>", "Date": "Sun, 30 Jun 2019 23:35:34 +0530", "Message-ID": "<20190630180609.36705-23-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 22/57] net/octeontx2: alloc and free TM HW\n\tresources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Krzysztof Kanas <kkanas@marvell.com>\n\nAllocate and free shaper/scheduler hardware resources for\nnodes of hirearchy levels in sw.\n\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/octeontx2/otx2_tm.c | 350 ++++++++++++++++++++++++++++++++\n 1 file changed, 350 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex bc0474242..91f31df05 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -54,6 +54,69 @@ nix_tm_node_search(struct otx2_eth_dev *dev,\n \treturn NULL;\n }\n \n+static uint32_t\n+check_rr(struct otx2_eth_dev *dev, uint32_t priority, uint32_t parent_id)\n+{\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tuint32_t rr_num = 0;\n+\n+\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\tif (!tm_node->parent)\n+\t\t\tcontinue;\n+\n+\t\tif (!(tm_node->parent->id == parent_id))\n+\t\t\tcontinue;\n+\n+\t\tif (tm_node->priority == priority)\n+\t\t\trr_num++;\n+\t}\n+\treturn rr_num;\n+}\n+\n+static int\n+nix_tm_update_parent_info(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_nix_tm_node *tm_node_child;\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tstruct otx2_nix_tm_node *parent;\n+\tuint32_t rr_num = 0;\n+\tuint32_t priority;\n+\n+\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\tif (!tm_node->parent)\n+\t\t\tcontinue;\n+\t\t/* Count group of children of same priority i.e are RR */\n+\t\tparent = tm_node->parent;\n+\t\tpriority = tm_node->priority;\n+\t\trr_num = check_rr(dev, priority, parent->id);\n+\n+\t\t/* Assuming that multiple RR groups are\n+\t\t * not configured based on capability.\n+\t\t */\n+\t\tif (rr_num > 1) {\n+\t\t\tparent->rr_prio = priority;\n+\t\t\tparent->rr_num = rr_num;\n+\t\t}\n+\n+\t\t/* Find out static priority children that are not in RR */\n+\t\tTAILQ_FOREACH(tm_node_child, &dev->node_list, node) {\n+\t\t\tif (!tm_node_child->parent)\n+\t\t\t\tcontinue;\n+\t\t\tif (parent->id != tm_node_child->parent->id)\n+\t\t\t\tcontinue;\n+\t\t\tif (parent->max_prio == UINT32_MAX &&\n+\t\t\t tm_node_child->priority != parent->rr_prio)\n+\t\t\t\tparent->max_prio = 0;\n+\n+\t\t\tif (parent->max_prio < tm_node_child->priority &&\n+\t\t\t parent->rr_prio != tm_node_child->priority)\n+\t\t\t\tparent->max_prio = tm_node_child->priority;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,\n \t\t\tuint32_t parent_node_id, uint32_t priority,\n@@ -115,6 +178,274 @@ nix_tm_clear_shaper_profiles(struct otx2_eth_dev *dev)\n \treturn 0;\n }\n \n+static int\n+nix_tm_free_resources(struct otx2_eth_dev *dev, uint32_t flags_mask,\n+\t\t uint32_t flags, bool hw_only)\n+{\n+\tstruct otx2_nix_tm_shaper_profile *shaper_profile;\n+\tstruct otx2_nix_tm_node *tm_node, *next_node;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_txsch_free_req *req;\n+\tuint32_t shaper_profile_id;\n+\tbool skip_node = false;\n+\tint rc = 0;\n+\n+\tnext_node = TAILQ_FIRST(&dev->node_list);\n+\twhile (next_node) {\n+\t\ttm_node = next_node;\n+\t\tnext_node = TAILQ_NEXT(tm_node, node);\n+\n+\t\t/* Check for only requested nodes */\n+\t\tif ((tm_node->flags & flags_mask) != flags)\n+\t\t\tcontinue;\n+\n+\t\tif (nix_tm_have_tl1_access(dev) &&\n+\t\t tm_node->hw_lvl_id == NIX_TXSCH_LVL_TL1)\n+\t\t\tskip_node = true;\n+\n+\t\totx2_tm_dbg(\"Free hwres for node %u, hwlvl %u, hw_id %u (%p)\",\n+\t\t\t tm_node->id, tm_node->hw_lvl_id,\n+\t\t\t tm_node->hw_id, tm_node);\n+\t\t/* Free specific HW resource if requested */\n+\t\tif (!skip_node && flags_mask &&\n+\t\t tm_node->flags & NIX_TM_NODE_HWRES) {\n+\t\t\treq = otx2_mbox_alloc_msg_nix_txsch_free(mbox);\n+\t\t\treq->flags = 0;\n+\t\t\treq->schq_lvl = tm_node->hw_lvl_id;\n+\t\t\treq->schq = tm_node->hw_id;\n+\t\t\trc = otx2_mbox_process(mbox);\n+\t\t\tif (rc)\n+\t\t\t\tbreak;\n+\t\t} else {\n+\t\t\tskip_node = false;\n+\t\t}\n+\t\ttm_node->flags &= ~NIX_TM_NODE_HWRES;\n+\n+\t\t/* Leave software elements if needed */\n+\t\tif (hw_only)\n+\t\t\tcontinue;\n+\n+\t\tshaper_profile_id = tm_node->params.shaper_profile_id;\n+\t\tshaper_profile =\n+\t\t\tnix_tm_shaper_profile_search(dev, shaper_profile_id);\n+\t\tif (shaper_profile)\n+\t\t\tshaper_profile->reference_count--;\n+\n+\t\tTAILQ_REMOVE(&dev->node_list, tm_node, node);\n+\t\trte_free(tm_node);\n+\t}\n+\n+\tif (!flags_mask) {\n+\t\t/* Free all hw resources */\n+\t\treq = otx2_mbox_alloc_msg_nix_txsch_free(mbox);\n+\t\treq->flags = TXSCHQ_FREE_ALL;\n+\n+\t\treturn otx2_mbox_process(mbox);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static uint8_t\n+nix_tm_copy_rsp_to_dev(struct otx2_eth_dev *dev,\n+\t\t struct nix_txsch_alloc_rsp *rsp)\n+{\n+\tuint16_t schq;\n+\tuint8_t lvl;\n+\n+\tfor (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {\n+\t\tfor (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) {\n+\t\t\tdev->txschq_list[lvl][schq] = rsp->schq_list[lvl][schq];\n+\t\t\tdev->txschq_contig_list[lvl][schq] =\n+\t\t\t\trsp->schq_contig_list[lvl][schq];\n+\t\t}\n+\n+\t\tdev->txschq[lvl] = rsp->schq[lvl];\n+\t\tdev->txschq_contig[lvl] = rsp->schq_contig[lvl];\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,\n+\t\t\t struct otx2_nix_tm_node *child,\n+\t\t\t struct otx2_nix_tm_node *parent)\n+{\n+\tuint32_t hw_id, schq_con_index, prio_offset;\n+\tuint32_t l_id, schq_index;\n+\n+\totx2_tm_dbg(\"Assign hw id for child node %u, lvl %u, hw_lvl %u (%p)\",\n+\t\t child->id, child->level_id, child->hw_lvl_id, child);\n+\n+\tchild->flags |= NIX_TM_NODE_HWRES;\n+\n+\t/* Process root nodes */\n+\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n+\t child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {\n+\t\tint idx = 0;\n+\t\tuint32_t tschq_con_index;\n+\n+\t\tl_id = child->hw_lvl_id;\n+\t\ttschq_con_index = dev->txschq_contig_index[l_id];\n+\t\thw_id = dev->txschq_contig_list[l_id][tschq_con_index];\n+\t\tchild->hw_id = hw_id;\n+\t\tdev->txschq_contig_index[l_id]++;\n+\t\t/* Update TL1 hw_id for its parent for config purpose */\n+\t\tidx = dev->txschq_index[NIX_TXSCH_LVL_TL1]++;\n+\t\thw_id = dev->txschq_list[NIX_TXSCH_LVL_TL1][idx];\n+\t\tchild->parent_hw_id = hw_id;\n+\t\treturn 0;\n+\t}\n+\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL1 &&\n+\t child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {\n+\t\tuint32_t tschq_con_index;\n+\n+\t\tl_id = child->hw_lvl_id;\n+\t\ttschq_con_index = dev->txschq_index[l_id];\n+\t\thw_id = dev->txschq_list[l_id][tschq_con_index];\n+\t\tchild->hw_id = hw_id;\n+\t\tdev->txschq_index[l_id]++;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Process children with parents */\n+\tl_id = child->hw_lvl_id;\n+\tschq_index = dev->txschq_index[l_id];\n+\tschq_con_index = dev->txschq_contig_index[l_id];\n+\n+\tif (child->priority == parent->rr_prio) {\n+\t\thw_id = dev->txschq_list[l_id][schq_index];\n+\t\tchild->hw_id = hw_id;\n+\t\tchild->parent_hw_id = parent->hw_id;\n+\t\tdev->txschq_index[l_id]++;\n+\t} else {\n+\t\tprio_offset = schq_con_index + child->priority;\n+\t\thw_id = dev->txschq_contig_list[l_id][prio_offset];\n+\t\tchild->hw_id = hw_id;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_assign_hw_id(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_nix_tm_node *parent, *child;\n+\tuint32_t child_hw_lvl, con_index_inc, i;\n+\n+\tfor (i = NIX_TXSCH_LVL_TL1; i > 0; i--) {\n+\t\tTAILQ_FOREACH(parent, &dev->node_list, node) {\n+\t\t\tchild_hw_lvl = parent->hw_lvl_id - 1;\n+\t\t\tif (parent->hw_lvl_id != i)\n+\t\t\t\tcontinue;\n+\t\t\tTAILQ_FOREACH(child, &dev->node_list, node) {\n+\t\t\t\tif (!child->parent)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tif (child->parent->id != parent->id)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tnix_tm_assign_id_to_node(dev, child, parent);\n+\t\t\t}\n+\n+\t\t\tcon_index_inc = parent->max_prio + 1;\n+\t\t\tdev->txschq_contig_index[child_hw_lvl] += con_index_inc;\n+\n+\t\t\t/*\n+\t\t\t * Explicitly assign id to parent node if it\n+\t\t\t * doesn't have a parent\n+\t\t\t */\n+\t\t\tif (parent->hw_lvl_id == dev->otx2_tm_root_lvl)\n+\t\t\t\tnix_tm_assign_id_to_node(dev, parent, NULL);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static uint8_t\n+nix_tm_count_req_schq(struct otx2_eth_dev *dev,\n+\t\t struct nix_txsch_alloc_req *req, uint8_t lvl)\n+{\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tuint8_t contig_count;\n+\n+\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\tif (lvl == tm_node->hw_lvl_id) {\n+\t\t\treq->schq[lvl - 1] += tm_node->rr_num;\n+\t\t\tif (tm_node->max_prio != UINT32_MAX) {\n+\t\t\t\tcontig_count = tm_node->max_prio + 1;\n+\t\t\t\treq->schq_contig[lvl - 1] += contig_count;\n+\t\t\t}\n+\t\t}\n+\t\tif (lvl == dev->otx2_tm_root_lvl &&\n+\t\t dev->otx2_tm_root_lvl && lvl == NIX_TXSCH_LVL_TL2 &&\n+\t\t tm_node->hw_lvl_id == dev->otx2_tm_root_lvl) {\n+\t\t\treq->schq_contig[dev->otx2_tm_root_lvl]++;\n+\t\t}\n+\t}\n+\n+\treq->schq[NIX_TXSCH_LVL_TL1] = 1;\n+\treq->schq_contig[NIX_TXSCH_LVL_TL1] = 0;\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_prepare_txschq_req(struct otx2_eth_dev *dev,\n+\t\t\t struct nix_txsch_alloc_req *req)\n+{\n+\tuint8_t i;\n+\n+\tfor (i = NIX_TXSCH_LVL_TL1; i > 0; i--)\n+\t\tnix_tm_count_req_schq(dev, req, i);\n+\n+\tfor (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {\n+\t\tdev->txschq_index[i] = 0;\n+\t\tdev->txschq_contig_index[i] = 0;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_send_txsch_alloc_msg(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_txsch_alloc_req *req;\n+\tstruct nix_txsch_alloc_rsp *rsp;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_nix_txsch_alloc(mbox);\n+\n+\trc = nix_tm_prepare_txschq_req(dev, req);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix_tm_copy_rsp_to_dev(dev, rsp);\n+\n+\tnix_tm_assign_hw_id(dev);\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc;\n+\n+\tRTE_SET_USED(xmit_enable);\n+\n+\tnix_tm_update_parent_info(dev);\n+\n+\trc = nix_tm_send_txsch_alloc_msg(dev);\n+\tif (rc) {\n+\t\totx2_err(\"TM failed to alloc tm resources=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n nix_tm_prepare_default_tree(struct rte_eth_dev *eth_dev)\n {\n@@ -226,6 +557,13 @@ int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n \tuint16_t sq_cnt = eth_dev->data->nb_tx_queues;\n \tint rc;\n \n+\t/* Free up all resources already held */\n+\trc = nix_tm_free_resources(dev, 0, 0, false);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to freeup existing resources,rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n \t/* Clear shaper profiles */\n \tnix_tm_clear_shaper_profiles(dev);\n \tdev->tm_flags = NIX_TM_DEFAULT_TREE;\n@@ -234,6 +572,9 @@ int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n \tif (rc != 0)\n \t\treturn rc;\n \n+\trc = nix_tm_alloc_resources(eth_dev, false);\n+\tif (rc != 0)\n+\t\treturn rc;\n \tdev->tm_leaf_cnt = sq_cnt;\n \n \treturn 0;\n@@ -243,6 +584,15 @@ int\n otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)\n {\n \tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc;\n+\n+\t/* Xmit is assumed to be disabled */\n+\t/* Free up resources already held */\n+\trc = nix_tm_free_resources(dev, 0, 0, false);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to freeup existing resources,rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n \n \t/* Clear shaper profiles */\n \tnix_tm_clear_shaper_profiles(dev);\n", "prefixes": [ "v2", "22/57" ] }