get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/55685/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55685,
    "url": "http://patches.dpdk.org/api/patches/55685/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-10-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190630180609.36705-10-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-10-jerinj@marvell.com",
    "date": "2019-06-30T18:05:21",
    "name": "[v2,09/57] net/octeontx2: add context debug utils",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "56b4919d516bfe5c1af4514c819eefb421b735f3",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-10-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5236,
            "url": "http://patches.dpdk.org/api/series/5236/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236",
            "date": "2019-06-30T18:05:12",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/5236/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55685/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/55685/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2E1171B9CB;\n\tSun, 30 Jun 2019 20:07:32 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 55F8D1B99C\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:07:03 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI6oes016863; Sun, 30 Jun 2019 11:07:02 -0700",
            "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2te7gm3y80-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 30 Jun 2019 11:07:02 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:07:00 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:07:00 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id BC92A3F703F;\n\tSun, 30 Jun 2019 11:06:58 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=JgmYYtReqhI9LdoLmGVQBAQ0+13sL5zjiFd+GNYJtOw=;\n\tb=LGsQcT9JVz/+I3WrVHK9nesTKuwMrEmFlMEWw0KqUxDJV0hWB1trR/OjvRj70B0iq5ej\n\tAu0yDLJwq2Is3a2LCU84hVyzBo/sotiG652Jw78c+9WdeAnk0beS8GUyCBm541y8SaRu\n\tGPtYZyd7Z2sC6WJTAp4d6h6T4KfdF8d1cVR/duq/51ECLhXrmfMLEg3X07ad39CVPtrG\n\t5pdLN7Y0U9KUli9r7ZnJf/YzIAjsnCQnlFgXgXis0wcY6rlFLBizfqIoguKMIsTrBolG\n\t8Fsu0ENwZbQyNqt6Bsp6ErL8+XfIJrsxeRbzzNO9oDCXN+A8mqEMKOgfP9Yggh5jyJJm\n\tsQ== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>",
        "CC": "Vivek Sharma <viveksharma@marvell.com>",
        "Date": "Sun, 30 Jun 2019 23:35:21 +0530",
        "Message-ID": "<20190630180609.36705-10-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v2 09/57] net/octeontx2: add context debug utils",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd RQ,SQ,CQ context and CQE structure dump utils.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vivek Sharma <viveksharma@marvell.com>\n---\n doc/guides/nics/octeontx2.rst             |   2 +-\n drivers/net/octeontx2/Makefile            |   1 +\n drivers/net/octeontx2/meson.build         |   1 +\n drivers/net/octeontx2/otx2_ethdev.h       |   4 +\n drivers/net/octeontx2/otx2_ethdev_debug.c | 272 ++++++++++++++++++++++\n drivers/net/octeontx2/otx2_ethdev_irq.c   |   6 +\n 6 files changed, 285 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/octeontx2/otx2_ethdev_debug.c",
    "diff": "diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex 50e825968..75d5746e8 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -18,7 +18,7 @@ Features of the OCTEON TX2 Ethdev PMD are:\n \n - SR-IOV VF\n - Lock-free Tx queue\n-- Debug utilities - error interrupt support\n+- Debug utilities - Context dump and error interrupt support\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 5083637e4..c6e24a535 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -32,6 +32,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_ethdev.c\t\\\n \totx2_ethdev_irq.c \\\n \totx2_ethdev_ops.c \\\n+\totx2_ethdev_debug.c \\\n \totx2_ethdev_devargs.c\n \n LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_eal\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex aa8417e3f..a06e1192c 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -7,6 +7,7 @@ sources = files(\n \t\t'otx2_ethdev.c',\n \t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_ops.c',\n+\t\t'otx2_ethdev_debug.c',\n \t\t'otx2_ethdev_devargs.c'\n \t\t)\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex d9cdd33b5..7c0bef28e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -174,6 +174,10 @@ int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);\n void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);\n \n+/* Debug */\n+int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n+void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n+\n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\nnew file mode 100644\nindex 000000000..39cda7637\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_ethdev_debug.c\n@@ -0,0 +1,272 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_ethdev.h\"\n+\n+#define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n+\n+static inline void\n+nix_lf_sq_dump(struct  nix_sq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: sqe_way_mask \\t\\t%d\\nW0: cq \\t\\t\\t\\t%d\",\n+\t\t ctx->sqe_way_mask, ctx->cq);\n+\tnix_dump(\"W0: sdp_mcast \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n+\t\t ctx->sdp_mcast, ctx->substream);\n+\tnix_dump(\"W0: qint_idx \\t\\t\\t%d\\nW0: ena \\t\\t\\t%d\\n\",\n+\t\t ctx->qint_idx, ctx->ena);\n+\n+\tnix_dump(\"W1: sqb_count \\t\\t\\t%d\\nW1: default_chan \\t\\t%d\",\n+\t\t ctx->sqb_count, ctx->default_chan);\n+\tnix_dump(\"W1: smq_rr_quantum \\t\\t%d\\nW1: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->smq_rr_quantum, ctx->sso_ena);\n+\tnix_dump(\"W1: xoff \\t\\t\\t%d\\nW1: cq_ena \\t\\t\\t%d\\nW1: smq\\t\\t\\t\\t%d\\n\",\n+\t\t ctx->xoff, ctx->cq_ena, ctx->smq);\n+\n+\tnix_dump(\"W2: sqe_stype \\t\\t\\t%d\\nW2: sq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->sqe_stype, ctx->sq_int_ena);\n+\tnix_dump(\"W2: sq_int  \\t\\t\\t%d\\nW2: sqb_aura \\t\\t\\t%d\",\n+\t\t ctx->sq_int, ctx->sqb_aura);\n+\tnix_dump(\"W2: smq_rr_count \\t\\t%d\\n\",  ctx->smq_rr_count);\n+\n+\tnix_dump(\"W3: smq_next_sq_vld\\t\\t%d\\nW3: smq_pend\\t\\t\\t%d\",\n+\t\t ctx->smq_next_sq_vld, ctx->smq_pend);\n+\tnix_dump(\"W3: smenq_next_sqb_vld  \\t%d\\nW3: head_offset\\t\\t\\t%d\",\n+\t\t ctx->smenq_next_sqb_vld, ctx->head_offset);\n+\tnix_dump(\"W3: smenq_offset\\t\\t%d\\nW3: tail_offset \\t\\t%d\",\n+\t\t ctx->smenq_offset, ctx->tail_offset);\n+\tnix_dump(\"W3: smq_lso_segnum \\t\\t%d\\nW3: smq_next_sq \\t\\t%d\",\n+\t\t ctx->smq_lso_segnum, ctx->smq_next_sq);\n+\tnix_dump(\"W3: mnq_dis \\t\\t\\t%d\\nW3: lmt_dis \\t\\t\\t%d\",\n+\t\t ctx->mnq_dis, ctx->lmt_dis);\n+\tnix_dump(\"W3: cq_limit\\t\\t\\t%d\\nW3: max_sqe_size\\t\\t%d\\n\",\n+\t\t ctx->cq_limit, ctx->max_sqe_size);\n+\n+\tnix_dump(\"W4: next_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->next_sqb);\n+\tnix_dump(\"W5: tail_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->tail_sqb);\n+\tnix_dump(\"W6: smenq_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->smenq_sqb);\n+\tnix_dump(\"W7: smenq_next_sqb \\t\\t0x%\" PRIx64 \"\", ctx->smenq_next_sqb);\n+\tnix_dump(\"W8: head_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->head_sqb);\n+\n+\tnix_dump(\"W9: vfi_lso_vld \\t\\t%d\\nW9: vfi_lso_vlan1_ins_ena\\t%d\",\n+\t\t ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);\n+\tnix_dump(\"W9: vfi_lso_vlan0_ins_ena\\t%d\\nW9: vfi_lso_mps\\t\\t\\t%d\",\n+\t\t ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);\n+\tnix_dump(\"W9: vfi_lso_sb \\t\\t\\t%d\\nW9: vfi_lso_sizem1\\t\\t%d\",\n+\t\t ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);\n+\tnix_dump(\"W9: vfi_lso_total\\t\\t%d\", ctx->vfi_lso_total);\n+\n+\tnix_dump(\"W10: scm_lso_rem \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->scm_lso_rem);\n+\tnix_dump(\"W11: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W12: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W14: dropped_octs \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W15: dropped_pkts \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_pkts);\n+}\n+\n+static inline void\n+nix_lf_rq_dump(struct  nix_rq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n+\t\t ctx->wqe_aura, ctx->substream);\n+\tnix_dump(\"W0: cq \\t\\t\\t\\t%d\\nW0: ena_wqwd \\t\\t\\t%d\",\n+\t\t ctx->cq, ctx->ena_wqwd);\n+\tnix_dump(\"W0: ipsech_ena \\t\\t\\t%d\\nW0: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->ipsech_ena, ctx->sso_ena);\n+\tnix_dump(\"W0: ena \\t\\t\\t%d\\n\", ctx->ena);\n+\n+\tnix_dump(\"W1: lpb_drop_ena \\t\\t%d\\nW1: spb_drop_ena \\t\\t%d\",\n+\t\t ctx->lpb_drop_ena, ctx->spb_drop_ena);\n+\tnix_dump(\"W1: xqe_drop_ena \\t\\t%d\\nW1: wqe_caching \\t\\t%d\",\n+\t\t ctx->xqe_drop_ena, ctx->wqe_caching);\n+\tnix_dump(\"W1: pb_caching \\t\\t\\t%d\\nW1: sso_tt \\t\\t\\t%d\",\n+\t\t ctx->pb_caching, ctx->sso_tt);\n+\tnix_dump(\"W1: sso_grp \\t\\t\\t%d\\nW1: lpb_aura \\t\\t\\t%d\",\n+\t\t ctx->sso_grp, ctx->lpb_aura);\n+\tnix_dump(\"W1: spb_aura \\t\\t\\t%d\\n\", ctx->spb_aura);\n+\n+\tnix_dump(\"W2: xqe_hdr_split \\t\\t%d\\nW2: xqe_imm_copy \\t\\t%d\",\n+\t\t ctx->xqe_hdr_split, ctx->xqe_imm_copy);\n+\tnix_dump(\"W2: xqe_imm_size \\t\\t%d\\nW2: later_skip \\t\\t\\t%d\",\n+\t\t ctx->xqe_imm_size, ctx->later_skip);\n+\tnix_dump(\"W2: first_skip \\t\\t\\t%d\\nW2: lpb_sizem1 \\t\\t\\t%d\",\n+\t\t ctx->first_skip, ctx->lpb_sizem1);\n+\tnix_dump(\"W2: spb_ena \\t\\t\\t%d\\nW2: wqe_skip \\t\\t\\t%d\",\n+\t\t ctx->spb_ena, ctx->wqe_skip);\n+\tnix_dump(\"W2: spb_sizem1 \\t\\t\\t%d\\n\", ctx->spb_sizem1);\n+\n+\tnix_dump(\"W3: spb_pool_pass \\t\\t%d\\nW3: spb_pool_drop \\t\\t%d\",\n+\t\t ctx->spb_pool_pass, ctx->spb_pool_drop);\n+\tnix_dump(\"W3: spb_aura_pass \\t\\t%d\\nW3: spb_aura_drop \\t\\t%d\",\n+\t\t ctx->spb_aura_pass, ctx->spb_aura_drop);\n+\tnix_dump(\"W3: wqe_pool_pass \\t\\t%d\\nW3: wqe_pool_drop \\t\\t%d\",\n+\t\t ctx->wqe_pool_pass, ctx->wqe_pool_drop);\n+\tnix_dump(\"W3: xqe_pass \\t\\t\\t%d\\nW3: xqe_drop \\t\\t\\t%d\\n\",\n+\t\t ctx->xqe_pass, ctx->xqe_drop);\n+\n+\tnix_dump(\"W4: qint_idx \\t\\t\\t%d\\nW4: rq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->qint_idx, ctx->rq_int_ena);\n+\tnix_dump(\"W4: rq_int \\t\\t\\t%d\\nW4: lpb_pool_pass \\t\\t%d\",\n+\t\t ctx->rq_int, ctx->lpb_pool_pass);\n+\tnix_dump(\"W4: lpb_pool_drop \\t\\t%d\\nW4: lpb_aura_pass \\t\\t%d\",\n+\t\t ctx->lpb_pool_drop, ctx->lpb_aura_pass);\n+\tnix_dump(\"W4: lpb_aura_drop \\t\\t%d\\n\", ctx->lpb_aura_drop);\n+\n+\tnix_dump(\"W5: flow_tagw \\t\\t\\t%d\\nW5: bad_utag \\t\\t\\t%d\",\n+\t\t ctx->flow_tagw, ctx->bad_utag);\n+\tnix_dump(\"W5: good_utag \\t\\t\\t%d\\nW5: ltag \\t\\t\\t%d\\n\",\n+\t\t ctx->good_utag, ctx->ltag);\n+\n+\tnix_dump(\"W6: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W7: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W8: drop_octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W9: drop_pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_pkts);\n+\tnix_dump(\"W10: re_pkts \\t\\t\\t0x%\" PRIx64 \"\\n\", (uint64_t)ctx->re_pkts);\n+}\n+\n+static inline void\n+nix_lf_cq_dump(struct nix_cq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: base \\t\\t\\t0x%\" PRIx64 \"\\n\", ctx->base);\n+\n+\tnix_dump(\"W1: wrptr \\t\\t\\t%\" PRIx64 \"\", (uint64_t)ctx->wrptr);\n+\tnix_dump(\"W1: avg_con \\t\\t\\t%d\\nW1: cint_idx \\t\\t\\t%d\",\n+\t\t ctx->avg_con, ctx->cint_idx);\n+\tnix_dump(\"W1: cq_err \\t\\t\\t%d\\nW1: qint_idx \\t\\t\\t%d\",\n+\t\t ctx->cq_err, ctx->qint_idx);\n+\tnix_dump(\"W1: bpid  \\t\\t\\t%d\\nW1: bp_ena \\t\\t\\t%d\\n\",\n+\t\t ctx->bpid, ctx->bp_ena);\n+\n+\tnix_dump(\"W2: update_time \\t\\t%d\\nW2: avg_level \\t\\t\\t%d\",\n+\t\t ctx->update_time, ctx->avg_level);\n+\tnix_dump(\"W2: head \\t\\t\\t%d\\nW2: tail \\t\\t\\t%d\\n\",\n+\t\t ctx->head, ctx->tail);\n+\n+\tnix_dump(\"W3: cq_err_int_ena \\t\\t%d\\nW3: cq_err_int \\t\\t\\t%d\",\n+\t\t ctx->cq_err_int_ena, ctx->cq_err_int);\n+\tnix_dump(\"W3: qsize \\t\\t\\t%d\\nW3: caching \\t\\t\\t%d\",\n+\t\t ctx->qsize, ctx->caching);\n+\tnix_dump(\"W3: substream \\t\\t\\t0x%03x\\nW3: ena \\t\\t\\t%d\",\n+\t\t ctx->substream, ctx->ena);\n+\tnix_dump(\"W3: drop_ena \\t\\t\\t%d\\nW3: drop \\t\\t\\t%d\",\n+\t\t ctx->drop_ena, ctx->drop);\n+\tnix_dump(\"W3: bp \\t\\t\\t\\t%d\\n\", ctx->bp);\n+}\n+\n+int\n+otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc, q, rq = eth_dev->data->nb_rx_queues;\n+\tint sq = eth_dev->data->nb_tx_queues;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tstruct nix_aq_enq_req *aq;\n+\n+\tfor (q = 0; q < rq; q++) {\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = q;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get cq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d cq=%d ===============\",\n+\t\t\t eth_dev->data->port_id, q);\n+\t\tnix_lf_cq_dump(&rsp->cq);\n+\t}\n+\n+\tfor (q = 0; q < rq; q++) {\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = q;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(mbox, (void **)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get rq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d rq=%d ===============\",\n+\t\t\t eth_dev->data->port_id, q);\n+\t\tnix_lf_rq_dump(&rsp->rq);\n+\t}\n+\tfor (q = 0; q < sq; q++) {\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = q;\n+\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get sq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d sq=%d ===============\",\n+\t\t\t eth_dev->data->port_id, q);\n+\t\tnix_lf_sq_dump(&rsp->sq);\n+\t}\n+\n+fail:\n+\treturn rc;\n+}\n+\n+/* Dumps struct nix_cqe_hdr_s and struct nix_rx_parse_s */\n+void\n+otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n+{\n+\tconst struct nix_rx_parse_s *rx =\n+\t\t (const struct nix_rx_parse_s *)((const uint64_t *)cq + 1);\n+\n+\tnix_dump(\"tag \\t\\t0x%x\\tq \\t\\t%d\\t\\tnode \\t\\t%d\\tcqe_type \\t%d\",\n+\t\t cq->tag, cq->q, cq->node, cq->cqe_type);\n+\n+\tnix_dump(\"W0: chan \\t%d\\t\\tdesc_sizem1 \\t%d\",\n+\t\t rx->chan, rx->desc_sizem1);\n+\tnix_dump(\"W0: imm_copy \\t%d\\t\\texpress \\t%d\",\n+\t\t rx->imm_copy, rx->express);\n+\tnix_dump(\"W0: wqwd \\t%d\\t\\terrlev \\t\\t%d\\t\\terrcode \\t%d\",\n+\t\t rx->wqwd, rx->errlev, rx->errcode);\n+\tnix_dump(\"W0: latype \\t%d\\t\\tlbtype \\t\\t%d\\t\\tlctype \\t\\t%d\",\n+\t\t rx->latype, rx->lbtype, rx->lctype);\n+\tnix_dump(\"W0: ldtype \\t%d\\t\\tletype \\t\\t%d\\t\\tlftype \\t\\t%d\",\n+\t\t rx->ldtype, rx->letype, rx->lftype);\n+\tnix_dump(\"W0: lgtype \\t%d \\t\\tlhtype \\t\\t%d\",\n+\t\t rx->lgtype, rx->lhtype);\n+\n+\tnix_dump(\"W1: pkt_lenm1 \\t%d\", rx->pkt_lenm1);\n+\tnix_dump(\"W1: l2m \\t%d\\t\\tl2b \\t\\t%d\\t\\tl3m \\t\\t%d\\tl3b \\t\\t%d\",\n+\t\t rx->l2m, rx->l2b, rx->l3m, rx->l3b);\n+\tnix_dump(\"W1: vtag0_valid %d\\t\\tvtag0_gone \\t%d\",\n+\t\t rx->vtag0_valid, rx->vtag0_gone);\n+\tnix_dump(\"W1: vtag1_valid %d\\t\\tvtag1_gone \\t%d\",\n+\t\t rx->vtag1_valid, rx->vtag1_gone);\n+\tnix_dump(\"W1: pkind \\t%d\", rx->pkind);\n+\tnix_dump(\"W1: vtag0_tci \\t%d\\t\\tvtag1_tci \\t%d\",\n+\t\t rx->vtag0_tci, rx->vtag1_tci);\n+\n+\tnix_dump(\"W2: laflags \\t%d\\t\\tlbflags\\t\\t%d\\t\\tlcflags \\t%d\",\n+\t\t rx->laflags, rx->lbflags, rx->lcflags);\n+\tnix_dump(\"W2: ldflags \\t%d\\t\\tleflags\\t\\t%d\\t\\tlfflags \\t%d\",\n+\t\t rx->ldflags, rx->leflags, rx->lfflags);\n+\tnix_dump(\"W2: lgflags \\t%d\\t\\tlhflags \\t%d\",\n+\t\t rx->lgflags, rx->lhflags);\n+\n+\tnix_dump(\"W3: eoh_ptr \\t%d\\t\\twqe_aura \\t%d\\t\\tpb_aura \\t%d\",\n+\t\t rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);\n+\tnix_dump(\"W3: match_id \\t%d\", rx->match_id);\n+\n+\tnix_dump(\"W4: laptr \\t%d\\t\\tlbptr \\t\\t%d\\t\\tlcptr \\t\\t%d\",\n+\t\t rx->laptr, rx->lbptr, rx->lcptr);\n+\tnix_dump(\"W4: ldptr \\t%d\\t\\tleptr \\t\\t%d\\t\\tlfptr \\t\\t%d\",\n+\t\t rx->ldptr, rx->leptr, rx->lfptr);\n+\tnix_dump(\"W4: lgptr \\t%d\\t\\tlhptr \\t\\t%d\", rx->lgptr, rx->lhptr);\n+\n+\tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n+\t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n+}\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\nindex 476c7ea78..fdebdef38 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_irq.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c\n@@ -23,6 +23,8 @@ nix_lf_err_irq(void *param)\n \n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_ERR_INT);\n+\n+\totx2_nix_queues_ctx_dump(eth_dev);\n }\n \n static int\n@@ -75,6 +77,8 @@ nix_lf_ras_irq(void *param)\n \n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_RAS);\n+\n+\totx2_nix_queues_ctx_dump(eth_dev);\n }\n \n static int\n@@ -232,6 +236,8 @@ nix_lf_q_irq(void *param)\n \n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));\n+\n+\totx2_nix_queues_ctx_dump(eth_dev);\n }\n \n int\n",
    "prefixes": [
        "v2",
        "09/57"
    ]
}