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GET /api/patches/55683/?format=api
{ "id": 55683, "url": "http://patches.dpdk.org/api/patches/55683/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-8-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-8-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-8-jerinj@marvell.com", "date": "2019-06-30T18:05:19", "name": "[v2,07/57] net/octeontx2: add device configure operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0e06253f059b8b3c2c4eb46585f22ea59fa54647", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-8-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55683/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/55683/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9AB191B9C7;\n\tSun, 30 Jun 2019 20:07:26 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D46961B9AF\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:06:56 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI6dmM028335 for <dev@dpdk.org>; Sun, 30 Jun 2019 11:06:56 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2te5bn4geb-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 11:06:56 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:06:54 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:06:54 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 35C3A3F7040;\n\tSun, 30 Jun 2019 11:06:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=fC0ggjr4Qm4/u3sI7oggJg9YFvqTwX8PoYlPOT49MSU=;\n\tb=G/9MfPqC7Iw7BcpkVdftCWCKzyJOCqUNaDLV62B7aqIrSQv1GWRJM7EXDimWkcq6HBhU\n\t46zOF7P0QQekbTdgwsgQKvMnYjjpCZz824bDpTjF8Ano2k0qp+k6NpIqoaOLeZ+p6doI\n\t3S+RSAoK0Tmf1IUV0Sw8B60u4LWHg7VEIT9BjlksgtuuPQmw2ZbtBpXVfQsyPisceh9d\n\tMQSD0ofR0q7KZl7g8/NYPJFZUDH/y5bU6lCdZCKMTHRxNqx2hAkwIkJ18QJVO5ewm67N\n\tEs/HXCpqm0WORjXwwvvZeTceOy2xseWFG7xSWgYC/+v4jKYs8JuANpKVpjNZs8U52llj\n\tFQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sun, 30 Jun 2019 23:35:19 +0530", "Message-ID": "<20190630180609.36705-8-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 07/57] net/octeontx2: add device configure\n\toperation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd device configure operation. This would call lf_alloc\nmailbox to allocate a NIX LF and upon return, AF will\nreturn the attributes for the select LF.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.c | 151 ++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_ethdev.h | 11 ++\n 2 files changed, 162 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 6e3c70559..65d72a47f 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -39,6 +39,52 @@ nix_get_tx_offload_capa(struct otx2_eth_dev *dev)\n \treturn NIX_TX_OFFLOAD_CAPA;\n }\n \n+static int\n+nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_lf_alloc_req *req;\n+\tstruct nix_lf_alloc_rsp *rsp;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);\n+\treq->rq_cnt = nb_rxq;\n+\treq->sq_cnt = nb_txq;\n+\treq->cq_cnt = nb_rxq;\n+\t/* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */\n+\tRTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);\n+\treq->xqe_sz = NIX_XQESZ_W16;\n+\treq->rss_sz = dev->rss_info.rss_size;\n+\treq->rss_grps = NIX_RSS_GRPS;\n+\treq->npa_func = otx2_npa_pf_func_get();\n+\treq->sso_func = otx2_sso_pf_func_get();\n+\treq->rx_cfg = BIT_ULL(35 /* DIS_APAD */);\n+\tif (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |\n+\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM)) {\n+\t\treq->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);\n+\t\treq->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);\n+\t}\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tdev->sqb_size = rsp->sqb_size;\n+\tdev->tx_chan_base = rsp->tx_chan_base;\n+\tdev->rx_chan_base = rsp->rx_chan_base;\n+\tdev->rx_chan_cnt = rsp->rx_chan_cnt;\n+\tdev->tx_chan_cnt = rsp->tx_chan_cnt;\n+\tdev->lso_tsov4_idx = rsp->lso_tsov4_idx;\n+\tdev->lso_tsov6_idx = rsp->lso_tsov6_idx;\n+\tdev->lf_tx_stats = rsp->lf_tx_stats;\n+\tdev->lf_rx_stats = rsp->lf_rx_stats;\n+\tdev->cints = rsp->cints;\n+\tdev->qints = rsp->qints;\n+\tdev->npc_flow.channel = dev->rx_chan_base;\n+\n+\treturn 0;\n+}\n+\n static int\n nix_lf_free(struct otx2_eth_dev *dev)\n {\n@@ -64,9 +110,114 @@ nix_lf_free(struct otx2_eth_dev *dev)\n \treturn otx2_mbox_process(mbox);\n }\n \n+static int\n+otx2_nix_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_eth_conf *conf = &data->dev_conf;\n+\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n+\tstruct rte_eth_txmode *txmode = &conf->txmode;\n+\tchar ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];\n+\tstruct rte_ether_addr *ea;\n+\tuint8_t nb_rxq, nb_txq;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\t/* Sanity checks */\n+\tif (rte_eal_has_hugepages() == 0) {\n+\t\totx2_err(\"Huge page is not configured\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (rte_eal_iova_mode() != RTE_IOVA_VA) {\n+\t\totx2_err(\"iova mode should be va\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (conf->link_speeds & ETH_LINK_SPEED_FIXED) {\n+\t\totx2_err(\"Setting link speed/duplex not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (conf->dcb_capability_en == 1) {\n+\t\totx2_err(\"dcb enable is not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {\n+\t\totx2_err(\"Flow director is not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (rxmode->mq_mode != ETH_MQ_RX_NONE &&\n+\t rxmode->mq_mode != ETH_MQ_RX_RSS) {\n+\t\totx2_err(\"Unsupported mq rx mode %d\", rxmode->mq_mode);\n+\t\tgoto fail;\n+\t}\n+\n+\tif (txmode->mq_mode != ETH_MQ_TX_NONE) {\n+\t\totx2_err(\"Unsupported mq tx mode %d\", txmode->mq_mode);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Free the resources allocated from the previous configure */\n+\tif (dev->configured == 1)\n+\t\tnix_lf_free(dev);\n+\n+\tif (otx2_dev_is_A0(dev) &&\n+\t (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&\n+\t ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||\n+\t (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {\n+\t\totx2_err(\"Outer IP and SCTP checksum unsupported\");\n+\t\trc = -EINVAL;\n+\t\tgoto fail;\n+\t}\n+\n+\tdev->rx_offloads = rxmode->offloads;\n+\tdev->tx_offloads = txmode->offloads;\n+\tdev->rss_info.rss_grps = NIX_RSS_GRPS;\n+\n+\tnb_rxq = RTE_MAX(data->nb_rx_queues, 1);\n+\tnb_txq = RTE_MAX(data->nb_tx_queues, 1);\n+\n+\t/* Alloc a nix lf */\n+\trc = nix_lf_alloc(dev, nb_rxq, nb_txq);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init nix_lf rc=%d\", rc);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Update the mac address */\n+\tea = eth_dev->data->mac_addrs;\n+\tmemcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n+\tif (rte_is_zero_ether_addr(ea))\n+\t\trte_eth_random_addr((uint8_t *)ea);\n+\n+\trte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);\n+\n+\totx2_nix_dbg(\"Configured port%d mac=%s nb_rxq=%d nb_txq=%d\"\n+\t\t\" rx_offloads=0x%\" PRIx64 \" tx_offloads=0x%\" PRIx64 \"\"\n+\t\t\" rx_flags=0x%x tx_flags=0x%x\",\n+\t\teth_dev->data->port_id, ea_fmt, nb_rxq,\n+\t\tnb_txq, dev->rx_offloads, dev->tx_offloads,\n+\t\tdev->rx_offload_flags, dev->tx_offload_flags);\n+\n+\t/* All good */\n+\tdev->configured = 1;\n+\tdev->configured_nb_rx_qs = data->nb_rx_queues;\n+\tdev->configured_nb_tx_qs = data->nb_tx_queues;\n+\treturn 0;\n+\n+fail:\n+\treturn rc;\n+}\n+\n /* Initialize and register driver with DPDK Application */\n static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.dev_infos_get = otx2_nix_info_get,\n+\t.dev_configure = otx2_nix_configure,\n };\n \n static inline int\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 666ceba91..c1528e2ac 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -59,11 +59,14 @@\n \n #define NIX_MAX_SQB\t\t\t512\n #define NIX_MIN_SQB\t\t\t32\n+/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/\n+#define NIX_RSS_GRPS\t\t\t8\n #define NIX_HASH_KEY_SIZE\t\t48 /* 352 Bits */\n #define NIX_RSS_RETA_SIZE\t\t64\n #define\tNIX_RX_MIN_DESC\t\t\t16\n #define NIX_RX_MIN_DESC_ALIGN\t\t16\n #define NIX_RX_NB_SEG_MAX\t\t6\n+#define NIX_CQ_ENTRY_SZ\t\t\t128\n \n /* If PTP is enabled additional SEND MEM DESC is required which\n * takes 2 words, hence max 7 iova address are possible\n@@ -105,9 +108,11 @@\n \n struct otx2_rss_info {\n \tuint16_t rss_size;\n+\tuint8_t rss_grps;\n };\n \n struct otx2_npc_flow_info {\n+\tuint16_t channel; /*rx channel */\n \tuint16_t flow_prealloc_size;\n \tuint16_t flow_max_priority;\n };\n@@ -124,7 +129,13 @@ struct otx2_eth_dev {\n \tuint8_t lso_tsov6_idx;\n \tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n \tuint8_t max_mac_entries;\n+\tuint8_t lf_tx_stats;\n+\tuint8_t lf_rx_stats;\n+\tuint16_t cints;\n+\tuint16_t qints;\n \tuint8_t configured;\n+\tuint8_t configured_nb_rx_qs;\n+\tuint8_t configured_nb_tx_qs;\n \tuint16_t nix_msixoff;\n \tuintptr_t base;\n \tuintptr_t lmt_addr;\n", "prefixes": [ "v2", "07/57" ] }