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GET /api/patches/55669/?format=api
{ "id": 55669, "url": "http://patches.dpdk.org/api/patches/55669/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1561911676-37718-2-git-send-email-gavin.hu@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1561911676-37718-2-git-send-email-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1561911676-37718-2-git-send-email-gavin.hu@arm.com", "date": "2019-06-30T16:21:12", "name": "[RFC,1/5] eal: add the APIs to wait until equal", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7bb82acc36aafbf1654b4726dc8b615bd21b26fa", "submitter": { "id": 1018, "url": "http://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1561911676-37718-2-git-send-email-gavin.hu@arm.com/mbox/", "series": [ { "id": 5234, "url": "http://patches.dpdk.org/api/series/5234/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5234", "date": "2019-06-30T16:21:11", "name": "use WFE for locks and ring on aarch64", "version": 1, "mbox": "http://patches.dpdk.org/series/5234/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55669/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55669/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2CB1D1B955;\n\tSun, 30 Jun 2019 18:21:45 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n\tby dpdk.org (Postfix) with ESMTP id 34DC91B945\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 18:21:42 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B06FCFC;\n\tSun, 30 Jun 2019 09:21:41 -0700 (PDT)", "from net-arm-thunderx2.shanghai.arm.com\n\t(net-arm-thunderx2.shanghai.arm.com [10.169.40.40])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t97B063F718; Sun, 30 Jun 2019 09:21:39 -0700 (PDT)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, jerinj@marvell.com, hemant.agrawal@nxp.com,\n\tbruce.richardson@intel.com, chaozhu@linux.vnet.ibm.com,\n\tHonnappa.Nagarahalli@arm.com, nd@arm.com, gavin.hu@arm.com", "Date": "Mon, 1 Jul 2019 00:21:12 +0800", "Message-Id": "<1561911676-37718-2-git-send-email-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1561911676-37718-1-git-send-email-gavin.hu@arm.com>", "References": "<1561911676-37718-1-git-send-email-gavin.hu@arm.com>", "Subject": "[dpdk-dev] [RFC 1/5] eal: add the APIs to wait until equal", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The rte_wait_until_equal_xxx APIs abstract the functionality of 'polling\nfor a memory location to become equal to a given value'.\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Steve Capper <steve.capper@arm.com>\nReviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n .../common/include/arch/arm/rte_pause_64.h | 143 +++++++++++++++++++++\n lib/librte_eal/common/include/generic/rte_pause.h | 20 +++\n 2 files changed, 163 insertions(+)", "diff": "diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h\nindex 93895d3..0095da6 100644\n--- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h\n+++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h\n@@ -17,6 +17,149 @@ static inline void rte_pause(void)\n \tasm volatile(\"yield\" ::: \"memory\");\n }\n \n+#ifdef RTE_USE_WFE\n+#define rte_wait_until_equal_relaxed(addr, expected) do {\\\n+\t\ttypeof(*addr) tmp; \\\n+\t\tif (__builtin_constant_p((expected))) \\\n+\t\t\tdo { \\\n+\t\t\t\tif (sizeof(*(addr)) == 16)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxrh %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 32)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxr %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 64)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxr %x0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%x0, %x2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\" (tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t} while (0); \\\n+\t\telse \\\n+\t\t\tdo { \\\n+\t\t\t\tif (sizeof(*(addr)) == 16)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxrh %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 32)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxr %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 64)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldxr %x0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%x0, %x2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\" (tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t} while (0); \\\n+} while (0)\n+\n+#define rte_wait_until_equal_acquire(addr, expected) do {\\\n+\t\ttypeof(*addr) tmp; \\\n+\t\tif (__builtin_constant_p((expected))) \\\n+\t\t\tdo { \\\n+\t\t\t\tif (sizeof(*(addr)) == 16)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxrh %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 32)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxr %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 64)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxr %x0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%x0, %x2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\" (tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"i\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t} while (0); \\\n+\t\telse \\\n+\t\t\tdo { \\\n+\t\t\t\tif (sizeof(*(addr)) == 16)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxrh %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 32)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxr %w0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%w0, %w2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\"(tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t\t\telse if (sizeof(*(addr)) == 64)\\\n+\t\t\t\t\tasm volatile( \\\n+\t\t\t\t\t\t\"sevl\\n\" \\\n+\t\t\t\t\t\t\"1:\t wfe\\n\" \\\n+\t\t\t\t\t\t\"ldaxr %x0, %1\\n\" \\\n+\t\t\t\t\t\t\"cmp\t%x0, %x2\\n\" \\\n+\t\t\t\t\t\t\"bne\t1b\\n\" \\\n+\t\t\t\t\t\t: \"=&r\" (tmp) \\\n+\t\t\t\t\t\t: \"Q\"(*addr), \"r\"(expected) \\\n+\t\t\t\t\t\t: \"cc\", \"memory\"); \\\n+\t\t} while (0); \\\n+} while (0)\n+\n+#endif\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/common/include/generic/rte_pause.h b/lib/librte_eal/common/include/generic/rte_pause.h\nindex 52bd4db..c115b61 100644\n--- a/lib/librte_eal/common/include/generic/rte_pause.h\n+++ b/lib/librte_eal/common/include/generic/rte_pause.h\n@@ -20,4 +20,24 @@\n */\n static inline void rte_pause(void);\n \n+#if !defined(RTE_USE_WFE)\n+#define rte_wait_until_equal_relaxed(addr, expected) do {\\\n+\t\trte_pause();\t\\\n+\t} while (*(addr) != (expected))\n+\n+#ifdef RTE_USE_C11_MEM_MODEL\n+#define rte_wait_until_equal_acquire(addr, expected) do {\\\n+\t\trte_pause();\t\\\n+\t} while (__atomic_load_n((addr), __ATOMIC_ACQUIRE) != (expected))\n+#else\n+#define rte_wait_until_equal_acquire(addr, expected) do {\\\n+\t\tdo {\\\n+\t\t\trte_pause(); \\\n+\t\t} while (*(addr) != (expected)); \\\n+\t\trte_smp_rmb(); \\\n+\t} while (0)\n+#endif\n+#endif\n+\n+\n #endif /* _RTE_PAUSE_H_ */\n", "prefixes": [ "RFC", "1/5" ] }