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GET /api/patches/55646/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55646,
    "url": "http://patches.dpdk.org/api/patches/55646/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-42-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-42-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-42-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:52",
    "name": "[v3,41/42] event/octeontx2: add devargs to limit timer adapters",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d261763f51811d73c8d667ff55913a84c812ae3e",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-42-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55646/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55646/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>",
        "CC": "<dev@dpdk.org>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=IIHD9eMYCE21VdzOWuuphp1+o2jigUHrOCeT7c9PvMQ=;\n\tb=WoG4nDa6hd3Tghb8oF8+R3ZMuYIAjLQd/cLRuURR0bbJ/A42gXVm1I+ywLhYmg5Rfsq7\n\tq1G0dXPdrnwY6s3k2qakmgqbpwuFUId9icvofkQ1r2yxhP4NqCEOWjO1W9g2eUl7INLs\n\tW7IuX4UktcJh3uFw2+qy6vFN3tpOdLeep1YxEhIR/4+Ne7e9o3krRFazgbgcyo0rCMe2\n\tFYidrNSlcCv0QvjfMDNM/AQ3E5E/sNid2GxoQJAVfeS5y1yyP4sQyKjnIxuj5d8tOC7u\n\tUSprEdWmzVO8nfSg5gtNV2RbeeWR58aYa5nQRZpU6BmzdI474PGXDijFD71pQ4sDYAsz\n\tOA== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 408DF1BBDE;\n\tFri, 28 Jun 2019 20:25:54 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 5D49C1BB3B\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:39 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIPEFp014540; Fri, 28 Jun 2019 11:25:38 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tdkg191nh-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:25:38 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:36 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:36 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 10EF03F7041;\n\tFri, 28 Jun 2019 11:25:33 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-42-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev] [PATCH v3 41/42] event/octeontx2: add devargs to limit\n\ttimer adapters",
        "Date": "Fri, 28 Jun 2019 23:53:52 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs to limit the max number of TIM rings reserved on probe.\nSince, TIM rings are HW resources we can avoid starving other\napplications by not grabbing all the rings.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_rings_lmt=2\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/octeontx2.rst       | 10 ++++++++++\n drivers/event/octeontx2/otx2_tim_evdev.c |  6 +++++-\n drivers/event/octeontx2/otx2_tim_evdev.h |  1 +\n 3 files changed, 16 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nindex bbc66558f..baa866a1e 100644\n--- a/doc/guides/eventdevs/octeontx2.rst\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -122,6 +122,16 @@ Runtime Config Options\n \n     --dev \"0002:0e:00.0,tim_stats_ena=1\"\n \n+- ``TIM limit max rings reserved``\n+\n+  The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM\n+  rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW\n+  resources we can avoid starving other applications by not grabbing all the\n+  rings.\n+  For example::\n+\n+    --dev \"0002:0e:00.0,tim_rings_lmt=5\"\n+\n Debugging Options\n ~~~~~~~~~~~~~~~~~\n \ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex cd9a679fb..c312bd541 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -527,6 +527,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n #define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n #define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n #define OTX2_TIM_STATS_ENA\t\"tim_stats_ena\"\n+#define OTX2_TIM_RINGS_LMT\t\"tim_rings_lmt\"\n \n static void\n tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n@@ -546,6 +547,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n \t\t\t   &parse_kvargs_value, &dev->chunk_slots);\n \trte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,\n \t\t\t   &dev->enable_stats);\n+\trte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value,\n+\t\t\t   &dev->min_ring_cnt);\n }\n \n void\n@@ -583,7 +586,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n-\tdev->nb_rings = rsrc_cnt->tim;\n+\tdev->nb_rings = dev->min_ring_cnt ?\n+\t\tRTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim;\n \n \tif (!dev->nb_rings) {\n \t\totx2_tim_dbg(\"No TIM Logical functions provisioned.\");\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex c8d16b03f..5af724ef9 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -121,6 +121,7 @@ struct otx2_tim_evdev {\n \t/* Dev args */\n \tuint8_t disable_npa;\n \tuint16_t chunk_slots;\n+\tuint16_t min_ring_cnt;\n \tuint8_t enable_stats;\n \t/* MSIX offsets */\n \tuint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];\n",
    "prefixes": [
        "v3",
        "41/42"
    ]
}