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GET /api/patches/55642/?format=api
{ "id": 55642, "url": "http://patches.dpdk.org/api/patches/55642/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-38-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-38-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-38-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:48", "name": "[v3,37/42] event/octeontx2: add event timer arm timeout burst", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "17b2a0bbecdb6c45dc9bb57403681352247930ea", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-38-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "http://patches.dpdk.org/api/series/5227/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "http://patches.dpdk.org/series/5227/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55642/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55642/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 16C541BB83;\n\tFri, 28 Jun 2019 20:25:48 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3BD841B9F3\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:28 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIPEFo014540 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:27 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tdkg191my-2\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:27 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:25 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:25 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id D1D153F7041;\n\tFri, 28 Jun 2019 11:25:23 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=001zopEcDJCVKugDwn0dHR2VJ5o01JQFwJ+JY624fPc=;\n\tb=dFRNNQSNGxQs7ZszKfw2OjG8OoxefjuBhKfXXfIUKQ57Ww8MYKD0vUUo8t7oBQ2fKjrW\n\tKS+W6U8bPExuxxj8Hamnv4ZQEK2Wj8RFG76ZR1Rl1IskIk/AOk8QcZ3iwEvZBAEJKXT4\n\tR6PPQj/xHvgfj3iiuJ4AplNpqS6jS9TgBypySfWC9BVXWxz4FVCil4OYTTyno4Df6UFk\n\tYxHIxkVRsYTO89AW+hiXHNuqYVPFEgAa6zQpYk0J8GagLyyp/m9iZ2tDTlKhZz9jfD6a\n\tpYquqgvK23YcQTvLkjrwktwgT7xZ9rMZNQNsVHSJlB0NUnkzibBit88ucUHDFbvuZvNQ\n\tUg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:48 +0530", "Message-ID": "<20190628182354.228-38-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 37/42] event/octeontx2: add event timer arm\n\ttimeout burst", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event timer arm timeout burst function.\nAll the timers requested to be armed have the same timeout.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 9 +++\n drivers/event/octeontx2/otx2_tim_evdev.h | 16 ++++\n drivers/event/octeontx2/otx2_tim_worker.c | 53 ++++++++++++\n drivers/event/octeontx2/otx2_tim_worker.h | 98 +++++++++++++++++++++++\n 4 files changed, 176 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex f4651c281..fabcd3d0a 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -42,8 +42,17 @@ TIM_ARM_FASTPATH_MODES\n #undef FP\n \t};\n \n+\tconst rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = {\n+#define FP(_name, _f2, _f1, flags) \\\n+\t\t[_f2][_f1] = otx2_tim_arm_tmo_tick_burst_ ## _name,\n+TIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\n+\t};\n+\n \totx2_tim_ops.arm_burst = arm_burst[tim_ring->optimized]\n \t\t\t\t[tim_ring->ena_dfb][prod_flag];\n+\totx2_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->optimized]\n+\t\t\t\t[tim_ring->ena_dfb];\n }\n \n static void\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 01b271507..751659719 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -66,6 +66,8 @@\n #define OTX2_TIM_MAX_BUCKETS\t\t(0xFFFFF)\n #define OTX2_TIM_RING_DEF_CHUNK_SZ\t(4096)\n #define OTX2_TIM_CHUNK_ALIGNMENT\t(16)\n+#define OTX2_TIM_MAX_BURST\t\t(RTE_CACHE_LINE_SIZE / \\\n+\t\t\t\t\t\tOTX2_TIM_CHUNK_ALIGNMENT)\n #define OTX2_TIM_NB_CHUNK_SLOTS(sz)\t(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)\n #define OTX2_TIM_MIN_CHUNK_SLOTS\t(0x1)\n #define OTX2_TIM_MAX_CHUNK_SLOTS\t(0x1FFE)\n@@ -175,6 +177,20 @@ uint16_t otx2_tim_arm_burst_ ## _name(\t\t\t\t\t \\\n TIM_ARM_FASTPATH_MODES\n #undef FP\n \n+#define TIM_ARM_TMO_FASTPATH_MODES\t\t\t\t\\\n+FP(mod, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB)\t\\\n+FP(mod_fb, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB)\t\t\\\n+FP(and, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB)\t\\\n+FP(and_fb, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB)\t\t\\\n+\n+#define FP(_name, _f2, _f1, flags)\t\t\t\t\t\\\n+uint16_t otx2_tim_arm_tmo_tick_burst_ ## _name(\t\t\t\t\\\n+\t\tconst struct rte_event_timer_adapter *adptr,\t\t\\\n+\t\tstruct rte_event_timer **tim,\t\t\t\t\\\n+\t\tconst uint64_t timeout_tick, const uint16_t nb_timers);\n+TIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\n+\n int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\t uint32_t *caps,\n \t\t const struct rte_event_timer_adapter_ops **ops);\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c\nindex 409575ec4..737b167d1 100644\n--- a/drivers/event/octeontx2/otx2_tim_worker.c\n+++ b/drivers/event/octeontx2/otx2_tim_worker.c\n@@ -72,6 +72,45 @@ tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,\n \treturn index;\n }\n \n+static __rte_always_inline uint16_t\n+tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,\n+\t\t struct rte_event_timer **tim,\n+\t\t const uint64_t timeout_tick,\n+\t\t const uint16_t nb_timers, const uint8_t flags)\n+{\n+\tstruct otx2_tim_ent entry[OTX2_TIM_MAX_BURST] __rte_cache_aligned;\n+\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n+\tuint16_t set_timers = 0;\n+\tuint16_t arr_idx = 0;\n+\tuint16_t idx;\n+\tint ret;\n+\n+\tif (unlikely(!timeout_tick || timeout_tick >= tim_ring->nb_bkts)) {\n+\t\tconst enum rte_event_timer_state state = timeout_tick ?\n+\t\t\tRTE_EVENT_TIMER_ERROR_TOOLATE :\n+\t\t\tRTE_EVENT_TIMER_ERROR_TOOEARLY;\n+\t\tfor (idx = 0; idx < nb_timers; idx++)\n+\t\t\ttim[idx]->state = state;\n+\n+\t\trte_errno = EINVAL;\n+\t\treturn 0;\n+\t}\n+\n+\twhile (arr_idx < nb_timers) {\n+\t\tfor (idx = 0; idx < OTX2_TIM_MAX_BURST && (arr_idx < nb_timers);\n+\t\t idx++, arr_idx++) {\n+\t\t\ttim_format_event(tim[arr_idx], &entry[idx]);\n+\t\t}\n+\t\tret = tim_add_entry_brst(tim_ring, timeout_tick,\n+\t\t\t\t\t &tim[set_timers], entry, idx, flags);\n+\t\tset_timers += ret;\n+\t\tif (ret != idx)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn set_timers;\n+}\n+\n #define FP(_name, _f3, _f2, _f1, _flags)\t\t\t\t \\\n uint16_t __rte_noinline\t\t\t\t\t\t\t \\\n otx2_tim_arm_burst_ ## _name(const struct rte_event_timer_adapter *adptr, \\\n@@ -82,3 +121,17 @@ otx2_tim_arm_burst_ ## _name(const struct rte_event_timer_adapter *adptr, \\\n }\n TIM_ARM_FASTPATH_MODES\n #undef FP\n+\n+#define FP(_name, _f2, _f1, _flags)\t\t\t\t\t\\\n+uint16_t __rte_noinline\t\t\t\t\t\t\t\\\n+otx2_tim_arm_tmo_tick_burst_ ## _name(\t\t\t\t\t\\\n+\t\t\tconst struct rte_event_timer_adapter *adptr,\t\\\n+\t\t\t\t struct rte_event_timer **tim,\t\\\n+\t\t\t\t const uint64_t timeout_tick,\t\\\n+\t\t\t\t const uint16_t nb_timers)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn tim_timer_arm_tmo_brst(adptr, tim, timeout_tick,\t\t\\\n+\t\t\tnb_timers, _flags);\t\t\t\t\\\n+}\n+TIM_ARM_TMO_FASTPATH_MODES\n+#undef FP\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.h b/drivers/event/octeontx2/otx2_tim_worker.h\nindex a5e0d56bc..da8c93ff2 100644\n--- a/drivers/event/octeontx2/otx2_tim_worker.h\n+++ b/drivers/event/octeontx2/otx2_tim_worker.h\n@@ -312,4 +312,102 @@ tim_add_entry_mp(struct otx2_tim_ring * const tim_ring,\n \treturn 0;\n }\n \n+static inline uint16_t\n+tim_cpy_wrk(uint16_t index, uint16_t cpy_lmt,\n+\t struct otx2_tim_ent *chunk,\n+\t struct rte_event_timer ** const tim,\n+\t const struct otx2_tim_ent * const ents,\n+\t const struct otx2_tim_bkt * const bkt)\n+{\n+\tfor (; index < cpy_lmt; index++) {\n+\t\t*chunk = *(ents + index);\n+\t\ttim[index]->impl_opaque[0] = (uintptr_t)chunk++;\n+\t\ttim[index]->impl_opaque[1] = (uintptr_t)bkt;\n+\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n+\t}\n+\n+\treturn index;\n+}\n+\n+/* Burst mode functions */\n+static inline int\n+tim_add_entry_brst(struct otx2_tim_ring * const tim_ring,\n+\t\t const uint16_t rel_bkt,\n+\t\t struct rte_event_timer ** const tim,\n+\t\t const struct otx2_tim_ent *ents,\n+\t\t const uint16_t nb_timers, const uint8_t flags)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\tstruct otx2_tim_bkt *bkt;\n+\tuint16_t chunk_remainder;\n+\tuint16_t index = 0;\n+\tuint64_t lock_sema;\n+\tint16_t rem, crem;\n+\tuint8_t lock_cnt;\n+\n+__retry:\n+\tbkt = tim_get_target_bucket(tim_ring, rel_bkt, flags);\n+\n+\t/* Only one thread beyond this. */\n+\tlock_sema = tim_bkt_inc_lock(bkt);\n+\tlock_cnt = (uint8_t)\n+\t\t((lock_sema >> TIM_BUCKET_W1_S_LOCK) & TIM_BUCKET_W1_M_LOCK);\n+\n+\tif (lock_cnt) {\n+\t\ttim_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t}\n+\n+\t/* Bucket related checks. */\n+\tif (unlikely(tim_bkt_get_hbt(lock_sema))) {\n+\t\ttim_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t}\n+\n+\tchunk_remainder = tim_bkt_fetch_rem(lock_sema);\n+\trem = chunk_remainder - nb_timers;\n+\tif (rem < 0) {\n+\t\tcrem = tim_ring->nb_chunk_slots - chunk_remainder;\n+\t\tif (chunk_remainder && crem) {\n+\t\t\tchunk = ((struct otx2_tim_ent *)\n+\t\t\t\t\t(uintptr_t)bkt->current_chunk) + crem;\n+\n+\t\t\tindex = tim_cpy_wrk(index, chunk_remainder, chunk, tim,\n+\t\t\t\t\t ents, bkt);\n+\t\t\ttim_bkt_sub_rem(bkt, chunk_remainder);\n+\t\t\ttim_bkt_add_nent(bkt, chunk_remainder);\n+\t\t}\n+\n+\t\tif (flags & OTX2_TIM_ENA_FB)\n+\t\t\tchunk = tim_refill_chunk(bkt, tim_ring);\n+\t\tif (flags & OTX2_TIM_ENA_DFB)\n+\t\t\tchunk = tim_insert_chunk(bkt, tim_ring);\n+\n+\t\tif (unlikely(chunk == NULL)) {\n+\t\t\ttim_bkt_dec_lock(bkt);\n+\t\t\trte_errno = ENOMEM;\n+\t\t\ttim[index]->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\treturn crem;\n+\t\t}\n+\t\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n+\t\tbkt->current_chunk = (uintptr_t)chunk;\n+\t\ttim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n+\n+\t\trem = nb_timers - chunk_remainder;\n+\t\ttim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - rem);\n+\t\ttim_bkt_add_nent(bkt, rem);\n+\t} else {\n+\t\tchunk = (struct otx2_tim_ent *)(uintptr_t)bkt->current_chunk;\n+\t\tchunk += (tim_ring->nb_chunk_slots - chunk_remainder);\n+\n+\t\ttim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n+\t\ttim_bkt_sub_rem(bkt, nb_timers);\n+\t\ttim_bkt_add_nent(bkt, nb_timers);\n+\t}\n+\n+\ttim_bkt_dec_lock(bkt);\n+\n+\treturn nb_timers;\n+}\n+\n #endif /* __OTX2_TIM_WORKER_H__ */\n", "prefixes": [ "v3", "37/42" ] }