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GET /api/patches/55635/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55635,
    "url": "http://patches.dpdk.org/api/patches/55635/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-31-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-31-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-31-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:41",
    "name": "[v3,30/42] event/octeontx2: add devargs to disable NPA",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "938adc6230e06a02b02a8538b8decc31bbcd9d6a",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-31-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55635/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55635/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>",
        "CC": "<dev@dpdk.org>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=suNgDg8Ad5QRsv65t8Lq2VYUiXlB2rtcABEormXwxzA=;\n\tb=cYKZ/rnfaaeiosSre/pAWYOL1GpQzc0XcHxZUUjvOTFjcKFQ5BupY5QIhUsS2v4jGAlM\n\t/h9O+hASlBJp+E77DCrcfBjIjLsc6ML1rCzcwUWUhroICvH+NY8gVbXjVKMNAamxYBpQ\n\tt5sKuITyDipmmp+7g9YvzL3H2qw8aV6MCn0VRuHLqryKj+MA+jcGoQQtlvnKLkz1SRd5\n\tvUC3wjrbonYYvaSoBBMM08mQZXsfgcpV96ewSpxckN1nqASYOxNaHJTPba/6pwcL/YY6\n\tS9U52uLw0/vCl8VH6ZSkIE6omOirNMLa1iWk/P+a84lwson2Qtquh9jot/n1v5+bk472\n\thg== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 92D1E1BB21;\n\tFri, 28 Jun 2019 20:25:34 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 516041B9FE\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:11 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SILDX3011345; Fri, 28 Jun 2019 11:25:10 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agpu-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:25:10 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:09 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:09 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 767523F7040;\n\tFri, 28 Jun 2019 11:25:07 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-31-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev] [PATCH v3 30/42] event/octeontx2: add devargs to disable\n\tNPA",
        "Date": "Fri, 28 Jun 2019 23:53:41 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nIf the chunks are allocated from NPA then TIM can automatically free\nthem when traversing the list of chunks.\nAdd devargs to disable NPA and use software mempool to manage chunks.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_disable_npa=1\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/octeontx2.rst       |  9 +++\n drivers/event/octeontx2/otx2_tim_evdev.c | 81 +++++++++++++++++-------\n drivers/event/octeontx2/otx2_tim_evdev.h |  3 +\n 3 files changed, 70 insertions(+), 23 deletions(-)",
    "diff": "diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nindex 98d0dfb6f..d24f81629 100644\n--- a/doc/guides/eventdevs/octeontx2.rst\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -94,6 +94,15 @@ Runtime Config Options\n \n     --dev \"0002:0e:00.0,selftest=1\"\n \n+- ``TIM disable NPA``\n+\n+  By default chunks are allocated from NPA then TIM can automatically free\n+  them when traversing the list of chunks. The ``tim_disable_npa`` devargs\n+  parameter disables NPA and uses software mempool to manage chunks\n+  For example::\n+\n+    --dev \"0002:0e:00.0,tim_disable_npa=1\"\n+\n Debugging Options\n ~~~~~~~~~~~~~~~~~\n \ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex a0953bb49..4b9816676 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -2,6 +2,7 @@\n  * Copyright(C) 2019 Marvell International Ltd.\n  */\n \n+#include <rte_kvargs.h>\n #include <rte_malloc.h>\n #include <rte_mbuf_pool_ops.h>\n \n@@ -77,33 +78,45 @@ tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,\n \tif (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)\n \t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n \n-\t/* NPA need not have cache as free is not visible to SW */\n-\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n-\t\t\t\t\t\t\ttim_ring->nb_chunks,\n-\t\t\t\t\t\t\ttim_ring->chunk_sz,\n-\t\t\t\t\t\t\t0, 0, rte_socket_id(),\n-\t\t\t\t\t\t\tmp_flags);\n+\tif (!tim_ring->disable_npa) {\n+\t\t/* NPA need not have cache as free is not visible to SW */\n+\t\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n+\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\t\t0, 0, rte_socket_id(), mp_flags);\n \n-\tif (tim_ring->chunk_pool == NULL) {\n-\t\totx2_err(\"Unable to create chunkpool.\");\n-\t\treturn -ENOMEM;\n-\t}\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\totx2_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n \n-\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n-\t\t\t\t\trte_mbuf_platform_mempool_ops(), NULL);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to set chunkpool ops\");\n-\t\tgoto free;\n-\t}\n+\t\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n+\t\t\t\t\t\trte_mbuf_platform_mempool_ops(),\n+\t\t\t\t\t\tNULL);\n+\t\tif (rc < 0) {\n+\t\t\totx2_err(\"Unable to set chunkpool ops\");\n+\t\t\tgoto free;\n+\t\t}\n \n-\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to set populate chunkpool.\");\n-\t\tgoto free;\n+\t\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n+\t\tif (rc < 0) {\n+\t\t\totx2_err(\"Unable to set populate chunkpool.\");\n+\t\t\tgoto free;\n+\t\t}\n+\t\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n+\t\t\t\ttim_ring->chunk_pool->pool_id);\n+\t\ttim_ring->ena_dfb = 0;\n+\t} else {\n+\t\ttim_ring->chunk_pool = rte_mempool_create(pool_name,\n+\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\t\tcache_sz, 0, NULL, NULL, NULL, NULL,\n+\t\t\t\trte_socket_id(),\n+\t\t\t\tmp_flags);\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\totx2_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\ttim_ring->ena_dfb = 1;\n \t}\n-\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n-\t\t\t\t\t\ttim_ring->chunk_pool->pool_id);\n-\ttim_ring->ena_dfb = 0;\n \n \treturn 0;\n \n@@ -229,6 +242,8 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n \ttim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;\n \tnb_timers = rcfg->nb_timers;\n+\ttim_ring->disable_npa = dev->disable_npa;\n+\n \ttim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(\n \t\t\t\t\t\t\ttim_ring->chunk_sz);\n \ttim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n@@ -339,6 +354,24 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \treturn 0;\n }\n \n+#define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n+\n+static void\n+tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\treturn;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\treturn;\n+\n+\trte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,\n+\t\t\t   &parse_kvargs_flag, &dev->disable_npa);\n+}\n+\n void\n otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n {\n@@ -364,6 +397,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \tdev->mbox = cmn_dev->mbox;\n \tdev->bar2 = cmn_dev->bar2;\n \n+\ttim_parse_devargs(pci_dev->device.devargs, dev);\n+\n \totx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n \trc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);\n \tif (rc < 0) {\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex fdd076ebd..0a0a0b4d8 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -55,6 +55,8 @@ struct otx2_tim_evdev {\n \tstruct otx2_mbox *mbox;\n \tuint16_t nb_rings;\n \tuintptr_t bar2;\n+\t/* Dev args */\n+\tuint8_t disable_npa;\n };\n \n struct otx2_tim_ring {\n@@ -65,6 +67,7 @@ struct otx2_tim_ring {\n \tstruct rte_mempool *chunk_pool;\n \tuint64_t tck_int;\n \tuint8_t prod_type_sp;\n+\tuint8_t disable_npa;\n \tuint8_t optimized;\n \tuint8_t ena_dfb;\n \tuint16_t ring_id;\n",
    "prefixes": [
        "v3",
        "30/42"
    ]
}