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GET /api/patches/55634/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55634,
    "url": "http://patches.dpdk.org/api/patches/55634/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-30-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-30-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-30-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:40",
    "name": "[v3,29/42] event/octeontx2: allow TIM to optimize config",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "8ec901b43a6cfa3d55404b0b5082a4a7ae6760e6",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-30-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55634/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55634/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "CC": "<dev@dpdk.org>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=mBekD5UTrCG27xzjYG0c9H8OeLt0NiHOB3FbOKcTARY=;\n\tb=Pu4oKcDyGvJ8V4eDqICBSt/B67KeEb9e14R/9YH3Y4VrXGCncSFnqQ9dcFvGsPGRb3P7\n\tzsP69CCiaFHWAt6+B1qhiJg1Exs+bvJWD3BLpPjYgSMD6rnNnirG5yHW9EFH8LIQh4Hu\n\tEMsuvM+ONT2/7gxOvdjwxQKBbBYERCRBJgIalA8T0ZaX0gQ9/LiV8Ph2UlAoO2WcYlxC\n\tHuJZvL1/QH0dGXIhLeXLNI8byhdjd5HloyRR04Q2ay9WVao7CPp09RzTkj6+NDhlSskI\n\tU0IBej/BVCLq9Xf7tuL6LzFuZHEbwceCMz/l8nrg35XqqErvFi3Xeh0d+cuPOFuUlxxa\n\tjQ== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3C80A1BB0C;\n\tFri, 28 Jun 2019 20:25:33 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id CD5B61B9F7\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:07 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKhtx010886 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:07 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agpj-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:06 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:05 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:05 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id CEF243F7040;\n\tFri, 28 Jun 2019 11:25:04 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-30-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev] [PATCH v3 29/42] event/octeontx2: allow TIM to optimize\n\tconfig",
        "Date": "Fri, 28 Jun 2019 23:53:40 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAllow TIM to optimize user supplied configuration based on\nRTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES flag.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.h     |  1 +\n drivers/event/octeontx2/otx2_tim_evdev.c | 62 +++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_tim_evdev.h |  3 ++\n 3 files changed, 64 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex fc8dde416..1e15b7e1c 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -76,6 +76,7 @@\n #define NSEC2USEC(__ns)\t\t\t((__ns) / 1E3)\n #define USEC2NSEC(__us)                 ((__us) * 1E3)\n #define NSEC2TICK(__ns, __freq)\t\t(((__ns) * (__freq)) / 1E9)\n+#define TICK2NSEC(__tck, __freq)\t(((__tck) * 1E9) / (__freq))\n \n enum otx2_sso_lf_type {\n \tSSO_LF_GGRP,\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex e24f7ce9e..a0953bb49 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -10,6 +10,51 @@\n \n static struct rte_event_timer_adapter_ops otx2_tim_ops;\n \n+static void\n+tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)\n+{\n+\tuint64_t tck_nsec;\n+\tuint32_t hbkts;\n+\tuint32_t lbkts;\n+\n+\thbkts = rte_align32pow2(tim_ring->nb_bkts);\n+\ttck_nsec = RTE_ALIGN_MUL_CEIL(tim_ring->max_tout / (hbkts - 1), 10);\n+\n+\tif ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,\n+\t\t\t\t  tim_ring->tenns_clk_freq) ||\n+\t    hbkts > OTX2_TIM_MAX_BUCKETS))\n+\t\thbkts = 0;\n+\n+\tlbkts = rte_align32prevpow2(tim_ring->nb_bkts);\n+\ttck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout / (lbkts - 1)), 10);\n+\n+\tif ((tck_nsec < TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,\n+\t\t\t\t  tim_ring->tenns_clk_freq) ||\n+\t    lbkts > OTX2_TIM_MAX_BUCKETS))\n+\t\tlbkts = 0;\n+\n+\tif (!hbkts && !lbkts)\n+\t\treturn;\n+\n+\tif (!hbkts) {\n+\t\ttim_ring->nb_bkts = lbkts;\n+\t\tgoto end;\n+\t} else if (!lbkts) {\n+\t\ttim_ring->nb_bkts = hbkts;\n+\t\tgoto end;\n+\t}\n+\n+\ttim_ring->nb_bkts = (hbkts - tim_ring->nb_bkts) <\n+\t\t(tim_ring->nb_bkts - lbkts) ? hbkts : lbkts;\n+end:\n+\ttim_ring->optimized = true;\n+\ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL((tim_ring->max_tout /\n+\t\t\t\t\t\t(tim_ring->nb_bkts - 1)), 10);\n+\totx2_tim_dbg(\"Optimized configured values\");\n+\totx2_tim_dbg(\"Nb_bkts  : %\" PRIu32 \"\", tim_ring->nb_bkts);\n+\totx2_tim_dbg(\"Tck_nsec : %\" PRIu64 \"\", tim_ring->tck_nsec);\n+}\n+\n static int\n tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,\n \t\t     struct rte_event_timer_adapter_conf *rcfg)\n@@ -159,8 +204,13 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \n \tif (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),\n \t\t      rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {\n-\t\trc = -ERANGE;\n-\t\tgoto rng_mem_err;\n+\t\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)\n+\t\t\trcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,\n+\t\t\t\t\trsp->tenns_clk);\n+\t\telse {\n+\t\t\trc = -ERANGE;\n+\t\t\tgoto rng_mem_err;\n+\t\t}\n \t}\n \n \ttim_ring = rte_zmalloc(\"otx2_tim_prv\", sizeof(struct otx2_tim_ring), 0);\n@@ -183,6 +233,14 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \t\t\t\t\t\t\ttim_ring->chunk_sz);\n \ttim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n \n+\t/* Try to optimize the bucket parameters. */\n+\tif ((rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)) {\n+\t\tif (rte_is_power_of_2(tim_ring->nb_bkts))\n+\t\t\ttim_ring->optimized = true;\n+\t\telse\n+\t\t\ttim_optimze_bkt_param(tim_ring);\n+\t}\n+\n \t/* Create buckets. */\n \ttim_ring->bkt = rte_zmalloc(\"otx2_tim_bucket\", (tim_ring->nb_bkts) *\n \t\t\t\t    sizeof(struct otx2_tim_bkt),\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex aaa4d93f5..fdd076ebd 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -17,6 +17,8 @@\n #define TIM_LF_RING_AURA\t\t(0x0)\n #define TIM_LF_RING_BASE\t\t(0x130)\n \n+#define OTX2_MAX_TIM_RINGS\t\t(256)\n+#define OTX2_TIM_MAX_BUCKETS\t\t(0xFFFFF)\n #define OTX2_TIM_RING_DEF_CHUNK_SZ\t(4096)\n #define OTX2_TIM_CHUNK_ALIGNMENT\t(16)\n #define OTX2_TIM_NB_CHUNK_SLOTS(sz)\t(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)\n@@ -63,6 +65,7 @@ struct otx2_tim_ring {\n \tstruct rte_mempool *chunk_pool;\n \tuint64_t tck_int;\n \tuint8_t prod_type_sp;\n+\tuint8_t optimized;\n \tuint8_t ena_dfb;\n \tuint16_t ring_id;\n \tuint32_t aura;\n",
    "prefixes": [
        "v3",
        "29/42"
    ]
}