get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/55628/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55628,
    "url": "http://patches.dpdk.org/api/patches/55628/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-24-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-24-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-24-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:34",
    "name": "[v3,23/42] event/octeontx2: add devargs to control SSO GGRP QoS",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "4e3aa7db6a540c32fbfbf07bb4cf8e8a691d5dce",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-24-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55628/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55628/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>",
        "CC": "<dev@dpdk.org>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=TfsKXRF4z3e2QW65RNrnGHghJhCYLOBzrk/dNKCX3Hw=;\n\tb=b5+hZUpxAgKwUlCvWZT1XIhlk+ewibMyJ9EFC/LW1irKT7sBPHDovhOewscPrhgp4mYr\n\tQl7ZFOCscPsnu49Zy29hzBe6aJo3K+IlWyRFLuaSlmp3XJcDcFxFdpd4AfrgLyZLcbTq\n\tWEe2G/kEWhdKZtILV+iU1k3LMcufUUkwNXbdgue1++1ziP/5O8mM4bTQFo5OnFlfNhNF\n\tLhhaxOYFb0SSnyCKAL38SmW7VeXmG7+2MSrMue1UTzkR/MbAF32RH7XsWibrdFZ9KClQ\n\tx2t6tCR7d30bSxskVbgepSGDLrTrxFpNNyfuyyncuTBIjFL72ARRM8+CWWfSmMGqXF3W\n\ttg== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 601141BA92;\n\tFri, 28 Jun 2019 20:25:21 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 11D141B9BA\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:54 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIOlWk013964; Fri, 28 Jun 2019 11:24:54 -0700",
            "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tdkg191jr-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:24:54 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:51 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:51 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id ECA5A3F7040;\n\tFri, 28 Jun 2019 11:24:49 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-24-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev] [PATCH v3 23/42] event/octeontx2: add devargs to control\n\tSSO GGRP QoS",
        "Date": "Fri, 28 Jun 2019 23:53:34 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nSSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\nevents. By default the buffers are assigned to the SSO GGRPs to\nsatisfy minimum HW requirements. SSO is free to assign the remaining\nbuffers to GGRPs based on a preconfigured threshold.\nWe can control the QoS of SSO GGRP by modifying the above mentioned\nthresholds. GGRPs that have higher importance can be assigned higher\nthresholds than the rest.\n\nExample:\n\t--dev \"0002:0e:00.0,qos=[1-50-50-50]\" // [Qx-XAQ-TAQ-IAQ]\n\nQx  -> Event queue Aka SSO GGRP.\nXAQ -> DRAM In-flights.\nTAQ & IAQ -> SRAM In-flights.\n\nThe values need to be expressed in terms of percentages, 0 represents\ndefault.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n doc/guides/eventdevs/octeontx2.rst   |  15 ++++\n drivers/event/octeontx2/otx2_evdev.c | 104 ++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h |   9 +++\n 3 files changed, 127 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nindex c864f39f9..9b235f236 100644\n--- a/doc/guides/eventdevs/octeontx2.rst\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -66,6 +66,21 @@ Runtime Config Options\n \n     --dev \"0002:0e:00.0,single_ws=1\"\n \n+- ``Event Group QoS support``\n+\n+  SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\n+  events. By default the buffers are assigned to the SSO GGRPs to\n+  satisfy minimum HW requirements. SSO is free to assign the remaining\n+  buffers to GGRPs based on a preconfigured threshold.\n+  We can control the QoS of SSO GGRP by modifying the above mentioned\n+  thresholds. GGRPs that have higher importance can be assigned higher\n+  thresholds than the rest. The dictionary format is as follows\n+  [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents\n+  default.\n+  For example::\n+\n+    --dev \"0002:0e:00.0,qos=[1-50-50-50]\"\n+\n Debugging Options\n ~~~~~~~~~~~~~~~~~\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex d6ddee1cd..786772ba9 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -934,6 +934,34 @@ otx2_handle_event(void *arg, struct rte_event event)\n \t\t\t\tevent, event_dev->data->dev_stop_flush_arg);\n }\n \n+static void\n+sso_qos_cfg(struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct sso_grp_qos_cfg *req;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->qos_queue_cnt; i++) {\n+\t\tuint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;\n+\t\tuint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;\n+\t\tuint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;\n+\n+\t\tif (dev->qos_parse_data[i].queue >= dev->nb_event_queues)\n+\t\t\tcontinue;\n+\n+\t\treq = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\treq->xaq_limit = (dev->nb_xaq_cfg *\n+\t\t\t\t  (xaq_prcnt ? xaq_prcnt : 100)) / 100;\n+\t\treq->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *\n+\t\t\t\t(iaq_prcnt ? iaq_prcnt : 100)) / 100;\n+\t\treq->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *\n+\t\t\t\t(taq_prcnt ? taq_prcnt : 100)) / 100;\n+\t}\n+\n+\tif (dev->qos_queue_cnt)\n+\t\totx2_mbox_process(dev->mbox);\n+}\n+\n static void\n sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)\n {\n@@ -1005,6 +1033,7 @@ static int\n otx2_sso_start(struct rte_eventdev *event_dev)\n {\n \tsso_func_trace();\n+\tsso_qos_cfg(event_dev);\n \tsso_cleanup(event_dev, 1);\n \tsso_fastpath_fns_set(event_dev);\n \n@@ -1035,6 +1064,76 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n #define OTX2_SSO_SINGLE_WS\t\"single_ws\"\n+#define OTX2_SSO_GGRP_QOS\t\"qos\"\n+\n+static void\n+parse_queue_param(char *value, void *opaque)\n+{\n+\tstruct otx2_sso_qos queue_qos = {0};\n+\tuint8_t *val = (uint8_t *)&queue_qos;\n+\tstruct otx2_sso_evdev *dev = opaque;\n+\tchar *tok = strtok(value, \"-\");\n+\n+\tif (!strlen(value))\n+\t\treturn;\n+\n+\twhile (tok != NULL) {\n+\t\t*val = atoi(tok);\n+\t\ttok = strtok(NULL, \"-\");\n+\t\tval++;\n+\t}\n+\n+\tif (val != (&queue_qos.iaq_prcnt + 1)) {\n+\t\totx2_err(\"Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]\");\n+\t\treturn;\n+\t}\n+\n+\tdev->qos_queue_cnt++;\n+\tdev->qos_parse_data = rte_realloc(dev->qos_parse_data,\n+\t\t\t\t\t  sizeof(struct otx2_sso_qos) *\n+\t\t\t\t\t  dev->qos_queue_cnt, 0);\n+\tdev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;\n+}\n+\n+static void\n+parse_qos_list(const char *value, void *opaque)\n+{\n+\tchar *s = strdup(value);\n+\tchar *start = NULL;\n+\tchar *end = NULL;\n+\tchar *f = s;\n+\n+\twhile (*s) {\n+\t\tif (*s == '[')\n+\t\t\tstart = s;\n+\t\telse if (*s == ']')\n+\t\t\tend = s;\n+\n+\t\tif (start < end && *start) {\n+\t\t\t*end = 0;\n+\t\t\tparse_queue_param(start + 1, opaque);\n+\t\t\ts = end;\n+\t\t\tstart = end;\n+\t\t}\n+\t\ts++;\n+\t}\n+\n+\tfree(f);\n+}\n+\n+static int\n+parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t/* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','\n+\t * isn't allowed. Everything is expressed in percentages, 0 represents\n+\t * default.\n+\t */\n+\tparse_qos_list(value, opaque);\n+\n+\treturn 0;\n+}\n \n static void\n sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n@@ -1052,6 +1151,8 @@ sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n \t\t\t   &dev->xae_cnt);\n \trte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,\n \t\t\t   &single_ws);\n+\trte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,\n+\t\t\t   dev);\n \n \tdev->dual_ws = !single_ws;\n \trte_kvargs_free(kvlist);\n@@ -1206,4 +1307,5 @@ RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\"\n-\t\t\t      OTX2_SSO_SINGLE_WS \"=1\");\n+\t\t\t      OTX2_SSO_SINGLE_WS \"=1\"\n+\t\t\t      OTX2_SSO_GGRP_QOS \"=<string>\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 4428abcfa..2aa742184 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -104,6 +104,13 @@ enum {\n \tSSO_SYNC_EMPTY\n };\n \n+struct otx2_sso_qos {\n+\tuint8_t queue;\n+\tuint8_t xaq_prcnt;\n+\tuint8_t taq_prcnt;\n+\tuint8_t iaq_prcnt;\n+};\n+\n struct otx2_sso_evdev {\n \tOTX2_DEV; /* Base class */\n \tuint8_t max_event_queues;\n@@ -124,6 +131,8 @@ struct otx2_sso_evdev {\n \t/* Dev args */\n \tuint8_t dual_ws;\n \tuint32_t xae_cnt;\n+\tuint8_t qos_queue_cnt;\n+\tstruct otx2_sso_qos *qos_parse_data;\n \t/* HW const */\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n",
    "prefixes": [
        "v3",
        "23/42"
    ]
}