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GET /api/patches/55627/?format=api
{ "id": 55627, "url": "http://patches.dpdk.org/api/patches/55627/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-23-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-23-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-23-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:33", "name": "[v3,22/42] event/octeontx2: add device start function", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f5ea4a39e2e88853f16e43383ac401b62605c8c6", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-23-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "http://patches.dpdk.org/api/series/5227/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "http://patches.dpdk.org/series/5227/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55627/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 920911BA5B;\n\tFri, 28 Jun 2019 20:25:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D58021B9C6\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:50 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKhtv010886; Fri, 28 Jun 2019 11:24:50 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agnb-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:24:50 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:48 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:48 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 934CB3F7040;\n\tFri, 28 Jun 2019 11:24:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=V6OvE3J3d9JyDpo9WEfe640OfE+V/xtZkH1QSyzxdXI=;\n\tb=IfhWACp/X2qEfZKZ17al3jJdBK0wq5PnnWK3T2KZtZhi5kc/+kt8XMsuJqlUZbrTmEyY\n\tTQZ4AAusay9Q98S/kiT+na5TKqS/FO8iULEOX1HGuS8VcH8RUtheoNMUYtgYn/+bGdcr\n\tm87EXElqRlxWIP5/OwaN1E1rnrEVe+5er1xeA+sEg9yyFsBLe4bpOhpTwEvgxXnTlBF3\n\tB0gWLGaCQfnJtD61KySKCBfVPa+++HhkVx5ipsjIG/+Y4yLE53p6K6X5oBMQJ3ipP5vW\n\tJ2RRxGQq1hxuKBQw20g27W2LAy1GsOdMkKXxdhtANu4gKyztxmtDTwp/iIANmpFdfdi2\n\t1Q== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n\t\"Anatoly Burakov\" <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:33 +0530", "Message-ID": "<20190628182354.228-23-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 22/42] event/octeontx2: add device start\n\tfunction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd eventdev start function along with few cleanup API's to maintain\nsanity.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 127 +++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 6 ++\n drivers/event/octeontx2/otx2_worker.c | 74 +++++++++++++++\n 3 files changed, 206 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 5dc39f029..d6ddee1cd 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -38,6 +38,41 @@ sso_get_msix_offsets(const struct rte_eventdev *event_dev)\n \treturn rc;\n }\n \n+void\n+sso_fastpath_fns_set(struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\n+\tevent_dev->enqueue\t\t\t= otx2_ssogws_enq;\n+\tevent_dev->enqueue_burst\t\t= otx2_ssogws_enq_burst;\n+\tevent_dev->enqueue_new_burst\t\t= otx2_ssogws_enq_new_burst;\n+\tevent_dev->enqueue_forward_burst\t= otx2_ssogws_enq_fwd_burst;\n+\n+\tevent_dev->dequeue\t\t\t= otx2_ssogws_deq;\n+\tevent_dev->dequeue_burst\t\t= otx2_ssogws_deq_burst;\n+\tif (dev->is_timeout_deq) {\n+\t\tevent_dev->dequeue\t\t= otx2_ssogws_deq_timeout;\n+\t\tevent_dev->dequeue_burst\t= otx2_ssogws_deq_timeout_burst;\n+\t}\n+\n+\tif (dev->dual_ws) {\n+\t\tevent_dev->enqueue\t\t= otx2_ssogws_dual_enq;\n+\t\tevent_dev->enqueue_burst\t= otx2_ssogws_dual_enq_burst;\n+\t\tevent_dev->enqueue_new_burst\t=\n+\t\t\t\t\totx2_ssogws_dual_enq_new_burst;\n+\t\tevent_dev->enqueue_forward_burst =\n+\t\t\t\t\totx2_ssogws_dual_enq_fwd_burst;\n+\t\tevent_dev->dequeue\t\t= otx2_ssogws_dual_deq;\n+\t\tevent_dev->dequeue_burst\t= otx2_ssogws_dual_deq_burst;\n+\t\tif (dev->is_timeout_deq) {\n+\t\t\tevent_dev->dequeue\t= otx2_ssogws_dual_deq_timeout;\n+\t\t\tevent_dev->dequeue_burst =\n+\t\t\t\t\totx2_ssogws_dual_deq_timeout_burst;\n+\t\t}\n+\t}\n+\trte_mb();\n+}\n+\n static void\n otx2_sso_info_get(struct rte_eventdev *event_dev,\n \t\t struct rte_event_dev_info *dev_info)\n@@ -889,6 +924,93 @@ otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)\n \t}\n }\n \n+static void\n+otx2_handle_event(void *arg, struct rte_event event)\n+{\n+\tstruct rte_eventdev *event_dev = arg;\n+\n+\tif (event_dev->dev_ops->dev_stop_flush != NULL)\n+\t\tevent_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,\n+\t\t\t\tevent, event_dev->data->dev_stop_flush_arg);\n+}\n+\n+static void\n+sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws;\n+\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\tssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);\n+\t\t\tssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);\n+\t\t\tws->swtag_req = 0;\n+\t\t\tws->vws = 0;\n+\t\t\tws->ws_state[0].cur_grp = 0;\n+\t\t\tws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;\n+\t\t\tws->ws_state[1].cur_grp = 0;\n+\t\t\tws->ws_state[1].cur_tt = SSO_SYNC_EMPTY;\n+\t\t} else {\n+\t\t\tstruct otx2_ssogws *ws;\n+\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\tssogws_reset(ws);\n+\t\t\tws->swtag_req = 0;\n+\t\t\tws->cur_grp = 0;\n+\t\t\tws->cur_tt = SSO_SYNC_EMPTY;\n+\t\t}\n+\t}\n+\n+\trte_mb();\n+\tif (dev->dual_ws) {\n+\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[0];\n+\t\tstruct otx2_ssogws temp_ws;\n+\n+\t\tmemcpy(&temp_ws, &ws->ws_state[0],\n+\t\t sizeof(struct otx2_ssogws_state));\n+\t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\t\t/* Consume all the events through HWS0 */\n+\t\t\tssogws_flush_events(&temp_ws, i, ws->grps_base[i],\n+\t\t\t\t\t otx2_handle_event, event_dev);\n+\t\t\t/* Enable/Disable SSO GGRP */\n+\t\t\totx2_write64(enable, ws->grps_base[i] +\n+\t\t\t\t SSO_LF_GGRP_QCTL);\n+\t\t}\n+\t\tws->ws_state[0].cur_grp = 0;\n+\t\tws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;\n+\t} else {\n+\t\tstruct otx2_ssogws *ws = event_dev->data->ports[0];\n+\n+\t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\t\t/* Consume all the events through HWS0 */\n+\t\t\tssogws_flush_events(ws, i, ws->grps_base[i],\n+\t\t\t\t\t otx2_handle_event, event_dev);\n+\t\t\t/* Enable/Disable SSO GGRP */\n+\t\t\totx2_write64(enable, ws->grps_base[i] +\n+\t\t\t\t SSO_LF_GGRP_QCTL);\n+\t\t}\n+\t\tws->cur_grp = 0;\n+\t\tws->cur_tt = SSO_SYNC_EMPTY;\n+\t}\n+\n+\t/* reset SSO GWS cache */\n+\totx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);\n+\totx2_mbox_process(dev->mbox);\n+}\n+\n+static int\n+otx2_sso_start(struct rte_eventdev *event_dev)\n+{\n+\tsso_func_trace();\n+\tsso_cleanup(event_dev, 1);\n+\tsso_fastpath_fns_set(event_dev);\n+\n+\treturn 0;\n+}\n+\n /* Initialize and register event driver with DPDK Application */\n static struct rte_eventdev_ops otx2_sso_ops = {\n \t.dev_infos_get = otx2_sso_info_get,\n@@ -908,6 +1030,7 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.xstats_get_names = otx2_sso_xstats_get_names,\n \n \t.dump = otx2_sso_dump,\n+\t.dev_start = otx2_sso_start,\n };\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n@@ -975,8 +1098,10 @@ otx2_sso_init(struct rte_eventdev *event_dev)\n \n \tevent_dev->dev_ops = &otx2_sso_ops;\n \t/* For secondary processes, the primary has done all the work */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\tsso_fastpath_fns_set(event_dev);\n \t\treturn 0;\n+\t}\n \n \tdev = sso_pmd_priv(event_dev);\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 8e614b109..4428abcfa 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -232,6 +232,12 @@ uint16_t otx2_ssogws_dual_deq_timeout(void *port, struct rte_event *ev,\n uint16_t otx2_ssogws_dual_deq_timeout_burst(void *port, struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events,\n \t\t\t\t\t uint64_t timeout_ticks);\n+void sso_fastpath_fns_set(struct rte_eventdev *event_dev);\n+/* Clean up API's */\n+typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);\n+void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,\n+\t\t\t uintptr_t base, otx2_handle_event_t fn, void *arg);\n+void ssogws_reset(struct otx2_ssogws *ws);\n /* Init and Fini API's */\n int otx2_sso_init(struct rte_eventdev *event_dev);\n int otx2_sso_fini(struct rte_eventdev *event_dev);\ndiff --git a/drivers/event/octeontx2/otx2_worker.c b/drivers/event/octeontx2/otx2_worker.c\nindex edc574673..7a6d4cad2 100644\n--- a/drivers/event/octeontx2/otx2_worker.c\n+++ b/drivers/event/octeontx2/otx2_worker.c\n@@ -194,3 +194,77 @@ otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n+\n+void\n+ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id, uintptr_t base,\n+\t\t otx2_handle_event_t fn, void *arg)\n+{\n+\tuint64_t cq_ds_cnt = 1;\n+\tuint64_t aq_cnt = 1;\n+\tuint64_t ds_cnt = 1;\n+\tstruct rte_event ev;\n+\tuint64_t enable;\n+\tuint64_t val;\n+\n+\tenable = otx2_read64(base + SSO_LF_GGRP_QCTL);\n+\tif (!enable)\n+\t\treturn;\n+\n+\tval = queue_id;\t/* GGRP ID */\n+\tval |= BIT_ULL(18);\t/* Grouped */\n+\tval |= BIT_ULL(16);\t/* WAIT */\n+\n+\taq_cnt = otx2_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\tds_cnt = otx2_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\tcq_ds_cnt = otx2_read64(base + SSO_LF_GGRP_INT_CNT);\n+\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\n+\twhile (aq_cnt || cq_ds_cnt || ds_cnt) {\n+\t\totx2_write64(val, ws->getwrk_op);\n+\t\totx2_ssogws_get_work_empty(ws, &ev);\n+\t\tif (fn != NULL && ev.u64 != 0)\n+\t\t\tfn(arg, ev);\n+\t\tif (ev.sched_type != SSO_TT_EMPTY)\n+\t\t\totx2_ssogws_swtag_flush(ws);\n+\t\trte_mb();\n+\t\taq_cnt = otx2_read64(base + SSO_LF_GGRP_AQ_CNT);\n+\t\tds_cnt = otx2_read64(base + SSO_LF_GGRP_MISC_CNT);\n+\t\tcq_ds_cnt = otx2_read64(base + SSO_LF_GGRP_INT_CNT);\n+\t\t/* Extract cq and ds count */\n+\t\tcq_ds_cnt &= 0x3FFF3FFF0000;\n+\t}\n+\n+\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n+\t\t SSOW_LF_GWS_OP_GWC_INVAL);\n+\trte_mb();\n+}\n+\n+void\n+ssogws_reset(struct otx2_ssogws *ws)\n+{\n+\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n+\tuint64_t pend_state;\n+\tuint8_t pend_tt;\n+\tuint64_t tag;\n+\n+\t/* Wait till getwork/swtp/waitw/desched completes. */\n+\tdo {\n+\t\tpend_state = otx2_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t\trte_mb();\n+\t} while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58)));\n+\n+\ttag = otx2_read64(base + SSOW_LF_GWS_TAG);\n+\tpend_tt = (tag >> 32) & 0x3;\n+\tif (pend_tt != SSO_TT_EMPTY) { /* Work was pending */\n+\t\tif (pend_tt == SSO_SYNC_ATOMIC || pend_tt == SSO_SYNC_ORDERED)\n+\t\t\totx2_ssogws_swtag_untag(ws);\n+\t\totx2_ssogws_desched(ws);\n+\t}\n+\trte_mb();\n+\n+\t/* Wait for desched to complete. */\n+\tdo {\n+\t\tpend_state = otx2_read64(base + SSOW_LF_GWS_PENDSTATE);\n+\t\trte_mb();\n+\t} while (pend_state & BIT_ULL(58));\n+}\n", "prefixes": [ "v3", "22/42" ] }