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GET /api/patches/55626/?format=api
{ "id": 55626, "url": "http://patches.dpdk.org/api/patches/55626/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-22-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-22-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-22-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:32", "name": "[v3,21/42] event/octeontx2: add devargs to force legacy mode", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3a83f0f8b3d3ad3275e990cad8ed220eab04a541", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-22-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "http://patches.dpdk.org/api/series/5227/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "http://patches.dpdk.org/series/5227/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55626/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55626/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 163B31BA46;\n\tFri, 28 Jun 2019 20:25:15 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 9308E1B9C1\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:48 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKhoR010889; Fri, 28 Jun 2019 11:24:47 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agn1-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:24:47 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:46 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:46 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 035F03F7040;\n\tFri, 28 Jun 2019 11:24:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=q+4fFQ/LFUwoUl9ZaL5pyb4suJMWuV5OyOa/6AwQmJ4=;\n\tb=yl3Q+yGZTJ6JMg4/2Z/RE78A5YAs7A9l7FR5XCCjGnQyKCx1nfHA6hJf7SkR222qM1DQ\n\tABGHLuKMEco9xba/62cfLgxcKeeHeJkxJ+iCnDO0hXAbdxOphbONXLWS7czY1roK4BhT\n\t7U5lwmLndYV9XpBwtICqEfcuG4O9XYv0j9EVn8NZT4xx/y6r6ZqyeVYb0gCsPomWRVek\n\t8jXBpOCGe6nV+gWLW1Dl9Jb5JNVfuRYbW9EHlmg2UdjIBMq24g77AldoSCg5nid+9mEi\n\tbSQfWomGeog2dQMMzU6LbrzvIFTAyLwdkmWGvN4nSHPlzR6kE9/bUmVn9idscalhLeTP\n\tWw== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:32 +0530", "Message-ID": "<20190628182354.228-22-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 21/42] event/octeontx2: add devargs to force\n\tlegacy mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nOcteontx2 SSO by default is set to use dual workslot mode.\nAdd devargs option to force legacy mode i.e. single workslot mode.\nExample:\n\t--dev \"0002:0e:00.0,single_ws=1\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/octeontx2.rst | 8 ++++++++\n drivers/event/octeontx2/otx2_evdev.c | 8 +++++++-\n drivers/event/octeontx2/otx2_evdev.h | 11 ++++++++++-\n 3 files changed, 25 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nindex f83cf1e9d..c864f39f9 100644\n--- a/doc/guides/eventdevs/octeontx2.rst\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -58,6 +58,14 @@ Runtime Config Options\n \n --dev \"0002:0e:00.0,xae_cnt=16384\"\n \n+- ``Force legacy mode``\n+\n+ The ``single_ws`` devargs parameter is introduced to force legacy mode i.e\n+ single workslot mode in SSO and disable the default dual workslot mode.\n+ For example::\n+\n+ --dev \"0002:0e:00.0,single_ws=1\"\n+\n Debugging Options\n ~~~~~~~~~~~~~~~~~\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 16d5e7dfa..5dc39f029 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -911,11 +911,13 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n };\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n+#define OTX2_SSO_SINGLE_WS\t\"single_ws\"\n \n static void\n sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n {\n \tstruct rte_kvargs *kvlist;\n+\tuint8_t single_ws = 0;\n \n \tif (devargs == NULL)\n \t\treturn;\n@@ -925,7 +927,10 @@ sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n \n \trte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,\n \t\t\t &dev->xae_cnt);\n+\trte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,\n+\t\t\t &single_ws);\n \n+\tdev->dual_ws = !single_ws;\n \trte_kvargs_free(kvlist);\n }\n \n@@ -1075,4 +1080,5 @@ otx2_sso_fini(struct rte_eventdev *event_dev)\n RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\"\n+\t\t\t OTX2_SSO_SINGLE_WS \"=1\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 30b5d2c32..8e614b109 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -121,8 +121,8 @@ struct otx2_sso_evdev {\n \tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n-\tuint8_t dual_ws;\n \t/* Dev args */\n+\tuint8_t dual_ws;\n \tuint32_t xae_cnt;\n \t/* HW const */\n \tuint32_t xae_waes;\n@@ -178,6 +178,15 @@ sso_pmd_priv(const struct rte_eventdev *event_dev)\n \treturn event_dev->data->dev_private;\n }\n \n+static inline int\n+parse_kvargs_flag(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint8_t *)opaque = !!atoi(value);\n+\treturn 0;\n+}\n+\n static inline int\n parse_kvargs_value(const char *key, const char *value, void *opaque)\n {\n", "prefixes": [ "v3", "21/42" ] }