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GET /api/patches/55619/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55619,
    "url": "http://patches.dpdk.org/api/patches/55619/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-15-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-15-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-15-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:25",
    "name": "[v3,14/42] event/octeontx2: add SSO HW device operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "8e61b136996701687e63d6b0177dee7fd92e3d38",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-15-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55619/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55619/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "CC": "<dev@dpdk.org>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=O2uTjBn0LQv+n9Ci9T81fVqWPnsITZQvQ4VfQx9xzLI=;\n\tb=DUvG3vJHHxpd2593ZSJVm0gfhg6H8YAyZEIhORP1EjYan/GLJfX5jsaL0FLXKzHZvh58\n\tnikI4uOTqHQejh6viVBbxpRPMX5qk3b2GdkoiTJMrHegZde4QQliu4Bp43CF8k90QJ4u\n\tziWyuK+ssAODutovegc0/GdXZiNzQoaLl0GNQo5Vhb37BTIj+ovGULnnhESXS0nlFyln\n\tvVQZFtf6W3OdUYJOOzWgQqJsYlvNtYMNyoFf4Y9OmoAipupv6AtRwyCSo7XnH1Su8LS7\n\tRKIKewlM9ZU7uvW1vovGBNnxEH//3aZdmsjdUfIqbrgPhavm6x5mwIWbENIuQaEuO0Kj\n\t3A== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4EA151B9E4;\n\tFri, 28 Jun 2019 20:24:55 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F18F21B9AA\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:32 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIMM3o012139 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:32 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agkg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:32 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:30 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:30 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 1D9613F7040;\n\tFri, 28 Jun 2019 11:24:28 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-15-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev] [PATCH v3 14/42] event/octeontx2: add SSO HW device\n\toperations",
        "Date": "Fri, 28 Jun 2019 23:53:25 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO HW device operations used for enqueue/dequeue.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/Makefile      |   1 +\n drivers/event/octeontx2/meson.build   |   3 +-\n drivers/event/octeontx2/otx2_evdev.h  |  22 +++\n drivers/event/octeontx2/otx2_worker.c |   5 +\n drivers/event/octeontx2/otx2_worker.h | 187 ++++++++++++++++++++++++++\n 5 files changed, 217 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/octeontx2/otx2_worker.c\n create mode 100644 drivers/event/octeontx2/otx2_worker.h",
    "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex 4f09c1fc8..a3de5ca23 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n \n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_worker.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c\n \ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex 5aa8113bd..1d2080b6d 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -2,7 +2,8 @@\n # Copyright(C) 2019 Marvell International Ltd.\n #\n \n-sources = files('otx2_evdev.c',\n+sources = files('otx2_worker.c',\n+\t\t'otx2_evdev.c',\n \t\t'otx2_evdev_irq.c',\n \t\t)\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex e1d2dcc69..cccce1dea 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -82,6 +82,28 @@ enum otx2_sso_lf_type {\n \tSSO_LF_GWS\n };\n \n+union otx2_sso_event {\n+\tuint64_t get_work0;\n+\tstruct {\n+\t\tuint32_t flow_id:20;\n+\t\tuint32_t sub_event_type:8;\n+\t\tuint32_t event_type:4;\n+\t\tuint8_t op:2;\n+\t\tuint8_t rsvd:4;\n+\t\tuint8_t sched_type:2;\n+\t\tuint8_t queue_id;\n+\t\tuint8_t priority;\n+\t\tuint8_t impl_opaque;\n+\t};\n+} __rte_aligned(64);\n+\n+enum {\n+\tSSO_SYNC_ORDERED,\n+\tSSO_SYNC_ATOMIC,\n+\tSSO_SYNC_UNTAGGED,\n+\tSSO_SYNC_EMPTY\n+};\n+\n struct otx2_sso_evdev {\n \tOTX2_DEV; /* Base class */\n \tuint8_t max_event_queues;\ndiff --git a/drivers/event/octeontx2/otx2_worker.c b/drivers/event/octeontx2/otx2_worker.c\nnew file mode 100644\nindex 000000000..83f535d05\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_worker.c\n@@ -0,0 +1,5 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_worker.h\"\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\nnew file mode 100644\nindex 000000000..f06ff064e\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_worker.h\n@@ -0,0 +1,187 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_WORKER_H__\n+#define __OTX2_WORKER_H__\n+\n+#include <rte_common.h>\n+#include <rte_branch_prediction.h>\n+\n+#include <otx2_common.h>\n+#include \"otx2_evdev.h\"\n+\n+/* SSO Operations */\n+\n+static __rte_always_inline uint16_t\n+otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev)\n+{\n+\tunion otx2_sso_event event;\n+\tuint64_t get_work1;\n+\n+\totx2_write64(BIT_ULL(16) | /* wait for work. */\n+\t\t     1, /* Use Mask set 0. */\n+\t\t     ws->getwrk_op);\n+\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(\n+\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t\t\"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n+\t\t\t\"\t\tsevl\t\t\t\t\\n\"\n+\t\t\t\"rty%=:\t\twfe\t\t\t\t\\n\"\n+\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t\t\"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n+\t\t\t\"done%=:\tdmb ld\t\t\t\t\\n\"\n+\t\t\t\"\t\tprfm pldl1keep, [%[wqp]]\t\\n\"\n+\t\t\t: [tag] \"=&r\" (event.get_work0),\n+\t\t\t  [wqp] \"=&r\" (get_work1)\n+\t\t\t: [tag_loc] \"r\" (ws->tag_op),\n+\t\t\t  [wqp_loc] \"r\" (ws->wqp_op)\n+\t\t\t);\n+#else\n+\tevent.get_work0 = otx2_read64(ws->tag_op);\n+\twhile ((BIT_ULL(63)) & event.get_work0)\n+\t\tevent.get_work0 = otx2_read64(ws->tag_op);\n+\n+\tget_work1 = otx2_read64(ws->wqp_op);\n+\trte_prefetch0((const void *)get_work1);\n+#endif\n+\n+\tevent.get_work0 = (event.get_work0 & (0x3ull << 32)) << 6 |\n+\t\t(event.get_work0 & (0x3FFull << 36)) << 4 |\n+\t\t(event.get_work0 & 0xffffffff);\n+\tws->cur_tt = event.sched_type;\n+\tws->cur_grp = event.queue_id;\n+\n+\n+\tev->event = event.get_work0;\n+\tev->u64 = get_work1;\n+\n+\treturn !!get_work1;\n+}\n+\n+/* Used in cleaning up workslot. */\n+static __rte_always_inline uint16_t\n+otx2_ssogws_get_work_empty(struct otx2_ssogws *ws, struct rte_event *ev)\n+{\n+\tunion otx2_sso_event event;\n+\tuint64_t get_work1;\n+\n+#ifdef RTE_ARCH_ARM64\n+\tasm volatile(\n+\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t\t\"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n+\t\t\t\"\t\tsevl\t\t\t\t\\n\"\n+\t\t\t\"rty%=:\t\twfe\t\t\t\t\\n\"\n+\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n+\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n+\t\t\t\"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n+\t\t\t\"done%=:\tdmb ld\t\t\t\t\\n\"\n+\t\t\t\"\t\tprfm pldl1keep, [%[wqp]]\t\\n\"\n+\t\t\t: [tag] \"=&r\" (event.get_work0),\n+\t\t\t  [wqp] \"=&r\" (get_work1)\n+\t\t\t: [tag_loc] \"r\" (ws->tag_op),\n+\t\t\t  [wqp_loc] \"r\" (ws->wqp_op)\n+\t\t\t);\n+#else\n+\tevent.get_work0 = otx2_read64(ws->tag_op);\n+\twhile ((BIT_ULL(63)) & event.get_work0)\n+\t\tevent.get_work0 = otx2_read64(ws->tag_op);\n+\n+\tget_work1 = otx2_read64(ws->wqp_op);\n+\trte_prefetch0((const void *)get_work1);\n+#endif\n+\n+\tevent.get_work0 = (event.get_work0 & (0x3ull << 32)) << 6 |\n+\t\t(event.get_work0 & (0x3FFull << 36)) << 4 |\n+\t\t(event.get_work0 & 0xffffffff);\n+\tws->cur_tt = event.sched_type;\n+\tws->cur_grp = event.queue_id;\n+\n+\tev->event = event.get_work0;\n+\tev->u64 = get_work1;\n+\n+\treturn !!get_work1;\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_add_work(struct otx2_ssogws *ws, const uint64_t event_ptr,\n+\t\t     const uint32_t tag, const uint8_t new_tt,\n+\t\t     const uint16_t grp)\n+{\n+\tuint64_t add_work0;\n+\n+\tadd_work0 = tag | ((uint64_t)(new_tt) << 32);\n+\totx2_store_pair(add_work0, event_ptr, ws->grps_base[grp]);\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_swtag_desched(struct otx2_ssogws *ws, uint32_t tag, uint8_t new_tt,\n+\t\t\t  uint16_t grp)\n+{\n+\tuint64_t val;\n+\n+\tval = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34);\n+\totx2_write64(val, ws->swtag_desched_op);\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_swtag_norm(struct otx2_ssogws *ws, uint32_t tag, uint8_t new_tt)\n+{\n+\tuint64_t val;\n+\n+\tval = tag | ((uint64_t)(new_tt & 0x3) << 32);\n+\totx2_write64(val, ws->swtag_norm_op);\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_swtag_untag(struct otx2_ssogws *ws)\n+{\n+\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n+\t\t     SSOW_LF_GWS_OP_SWTAG_UNTAG);\n+\tws->cur_tt = SSO_SYNC_UNTAGGED;\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_swtag_flush(struct otx2_ssogws *ws)\n+{\n+\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n+\t\t     SSOW_LF_GWS_OP_SWTAG_FLUSH);\n+\tws->cur_tt = SSO_SYNC_EMPTY;\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_desched(struct otx2_ssogws *ws)\n+{\n+\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n+\t\t     SSOW_LF_GWS_OP_DESCHED);\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_swtag_wait(struct otx2_ssogws *ws)\n+{\n+#ifdef RTE_ARCH_ARM64\n+\tuint64_t swtp;\n+\n+\tasm volatile (\n+\t\t\t\"\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t\t\"\tcbz %[swtb], done%=\t\t\\n\"\n+\t\t\t\"\tsevl\t\t\t\t\\n\"\n+\t\t\t\"rty%=:\twfe\t\t\t\t\\n\"\n+\t\t\t\"\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n+\t\t\t\"\tcbnz %[swtb], rty%=\t\t\\n\"\n+\t\t\t\"done%=:\t\t\t\t\\n\"\n+\t\t\t: [swtb] \"=&r\" (swtp)\n+\t\t\t: [swtp_loc] \"r\" (ws->swtp_op)\n+\t\t\t);\n+#else\n+\t/* Wait for the SWTAG/SWTAG_FULL operation */\n+\twhile (otx2_read64(ws->swtp_op))\n+\t\t;\n+#endif\n+}\n+\n+#endif\n",
    "prefixes": [
        "v3",
        "14/42"
    ]
}