get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/55618/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55618,
    "url": "http://patches.dpdk.org/api/patches/55618/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-14-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-14-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-14-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:24",
    "name": "[v3,13/42] event/octeontx2: add xstats support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "2e7af321e93e135c12ef5a0960313aea272f800b",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-14-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "http://patches.dpdk.org/api/series/5227/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55618/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55618/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "X-BeenThere": "dev@dpdk.org",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "MIME-Version": "1.0",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "CC": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=/f0WY+lEo1Kv/7gg2+sjut8SJajod1nRx/FgGMAMECY=;\n\tb=Cf361ROtslJiv01V+64yDa38gaVlchinvRLWjLFUZPrkII4G4dEmpB6eMOOh92sKUyPz\n\te5CfYoLGgAlhHu0nCRMlneqDcbdEA3EQNdV4YCm/QXxV1FkfZ9PCMFmalloXDHpXSoA0\n\tYjjzxhup5MCp9ZNQyTYB0RI42Lf1VZF9FiTnp2n9sf6e/t+0QF+MUkqJh1mpDW+Ek/AD\n\tVpuznAXIEP8Hk1IibooOhPk1BZb+m/uY38oN6VS5Z4U0hlJ8rSt9FwZgxLmIOQOL3pzW\n\te+CsmGhIhdvUOUaE6LP5PX5vJCcC7ky/x/WOzMBIqCKqmOSPT+5SF/ISUH4AJX9WWibG\n\t+g== ",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5385D1B9D8;\n\tFri, 28 Jun 2019 20:24:51 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 02B321B9B0\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:29 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SILDWl011345 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:29 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agka-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:29 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:28 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:28 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id ADA7E3F7040;\n\tFri, 28 Jun 2019 11:24:26 -0700 (PDT)"
        ],
        "X-Original-To": "patchwork@dpdk.org",
        "Content-Type": "text/plain",
        "Message-ID": "<20190628182354.228-14-pbhagavatula@marvell.com>",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Version": "2.1.15",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Subject": "[dpdk-dev]  [PATCH v3 13/42] event/octeontx2: add xstats support",
        "Date": "Fri, 28 Jun 2019 23:53:24 +0530",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Precedence": "list"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd support for retrieving statistics from SSO GWS and GGRP.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c       |   5 +\n drivers/event/octeontx2/otx2_evdev_stats.h | 242 +++++++++++++++++++++\n 2 files changed, 247 insertions(+)\n create mode 100644 drivers/event/octeontx2/otx2_evdev_stats.h",
    "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 6c37c5b5c..51220f447 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -12,6 +12,7 @@\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n+#include \"otx2_evdev_stats.h\"\n #include \"otx2_evdev.h\"\n #include \"otx2_irq.h\"\n \n@@ -763,6 +764,10 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.port_unlink      = otx2_sso_port_unlink,\n \t.timeout_ticks    = otx2_sso_timeout_ticks,\n \n+\t.xstats_get       = otx2_sso_xstats_get,\n+\t.xstats_reset     = otx2_sso_xstats_reset,\n+\t.xstats_get_names = otx2_sso_xstats_get_names,\n+\n \t.dump             = otx2_sso_dump,\n };\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev_stats.h b/drivers/event/octeontx2/otx2_evdev_stats.h\nnew file mode 100644\nindex 000000000..df76a1333\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev_stats.h\n@@ -0,0 +1,242 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_EVDEV_STATS_H__\n+#define __OTX2_EVDEV_STATS_H__\n+\n+#include \"otx2_evdev.h\"\n+\n+struct otx2_sso_xstats_name {\n+\tconst char name[RTE_EVENT_DEV_XSTATS_NAME_SIZE];\n+\tconst size_t offset;\n+\tconst uint64_t mask;\n+\tconst uint8_t shift;\n+\tuint64_t reset_snap[OTX2_SSO_MAX_VHGRP];\n+};\n+\n+static struct otx2_sso_xstats_name sso_hws_xstats[] = {\n+\t{\"last_grp_serviced\",\toffsetof(struct sso_hws_stats, arbitration),\n+\t\t\t\t0x3FF, 0, {0} },\n+\t{\"affinity_arbitration_credits\",\n+\t\t\t\toffsetof(struct sso_hws_stats, arbitration),\n+\t\t\t\t0xF, 16, {0} },\n+};\n+\n+static struct otx2_sso_xstats_name sso_grp_xstats[] = {\n+\t{\"wrk_sched\",\t\toffsetof(struct sso_grp_stats, ws_pc), ~0x0, 0,\n+\t\t\t\t{0} },\n+\t{\"xaq_dram\",\t\toffsetof(struct sso_grp_stats, ext_pc), ~0x0,\n+\t\t\t\t0, {0} },\n+\t{\"add_wrk\",\t\toffsetof(struct sso_grp_stats, wa_pc), ~0x0, 0,\n+\t\t\t\t{0} },\n+\t{\"tag_switch_req\",\toffsetof(struct sso_grp_stats, ts_pc), ~0x0, 0,\n+\t\t\t\t{0} },\n+\t{\"desched_req\",\t\toffsetof(struct sso_grp_stats, ds_pc), ~0x0, 0,\n+\t\t\t\t{0} },\n+\t{\"desched_wrk\",\t\toffsetof(struct sso_grp_stats, dq_pc), ~0x0, 0,\n+\t\t\t\t{0} },\n+\t{\"xaq_cached\",\t\toffsetof(struct sso_grp_stats, aw_status), 0x3,\n+\t\t\t\t0, {0} },\n+\t{\"work_inflight\",\toffsetof(struct sso_grp_stats, aw_status), 0x3F,\n+\t\t\t\t16, {0} },\n+\t{\"inuse_pages\",\t\toffsetof(struct sso_grp_stats, page_cnt),\n+\t\t\t\t0xFFFFFFFF, 0, {0} },\n+};\n+\n+#define OTX2_SSO_NUM_HWS_XSTATS RTE_DIM(sso_hws_xstats)\n+#define OTX2_SSO_NUM_GRP_XSTATS RTE_DIM(sso_grp_xstats)\n+\n+#define OTX2_SSO_NUM_XSTATS (OTX2_SSO_NUM_HWS_XSTATS + OTX2_SSO_NUM_GRP_XSTATS)\n+\n+static int\n+otx2_sso_xstats_get(const struct rte_eventdev *event_dev,\n+\t\t    enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n+\t\t    const unsigned int ids[], uint64_t values[], unsigned int n)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_sso_xstats_name *xstats;\n+\tstruct otx2_sso_xstats_name *xstat;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int i;\n+\tuint64_t value;\n+\tvoid *req_rsp;\n+\tint rc;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hws_xstats;\n+\n+\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n+\t\t\t((struct sso_info_req *)req_rsp)->hws = queue_port_id;\n+\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_grp_xstats;\n+\n+\t\treq_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);\n+\t\t\t((struct sso_info_req *)req_rsp)->grp = queue_port_id;\n+\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\totx2_err(\"Invalid mode received\");\n+\t\tgoto invalid_value;\n+\t};\n+\n+\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\txstat = &xstats[ids[i] - start_offset];\n+\t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n+\t\tvalue = (value >> xstat->shift) & xstat->mask;\n+\n+\t\tvalues[i] = value;\n+\t\tvalues[i] -= xstat->reset_snap[queue_port_id];\n+\t}\n+\n+\treturn i;\n+invalid_value:\n+\treturn -EINVAL;\n+}\n+\n+static int\n+otx2_sso_xstats_reset(struct rte_eventdev *event_dev,\n+\t\t      enum rte_event_dev_xstats_mode mode,\n+\t\t      int16_t queue_port_id, const uint32_t ids[], uint32_t n)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_sso_xstats_name *xstats;\n+\tstruct otx2_sso_xstats_name *xstat;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int i;\n+\tuint64_t value;\n+\tvoid *req_rsp;\n+\tint rc;\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\treturn 0;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_hws_xstats;\n+\n+\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n+\t\t((struct sso_info_req *)req_rsp)->hws = queue_port_id;\n+\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tgoto invalid_value;\n+\n+\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\txstats = sso_grp_xstats;\n+\n+\t\treq_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);\n+\t\t\t((struct sso_info_req *)req_rsp)->grp = queue_port_id;\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&req_rsp);\n+\t\tif (rc < 0)\n+\t\t\tgoto invalid_value;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\totx2_err(\"Invalid mode received\");\n+\t\tgoto invalid_value;\n+\t};\n+\n+\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\txstat = &xstats[ids[i] - start_offset];\n+\t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n+\t\tvalue = (value >> xstat->shift) & xstat->mask;\n+\n+\t\txstat->reset_snap[queue_port_id] =  value;\n+\t}\n+\treturn i;\n+invalid_value:\n+\treturn -EINVAL;\n+}\n+\n+static int\n+otx2_sso_xstats_get_names(const struct rte_eventdev *event_dev,\n+\t\t\t  enum rte_event_dev_xstats_mode mode,\n+\t\t\t  uint8_t queue_port_id,\n+\t\t\t  struct rte_event_dev_xstats_name *xstats_names,\n+\t\t\t  unsigned int *ids, unsigned int size)\n+{\n+\tstruct rte_event_dev_xstats_name xstats_names_copy[OTX2_SSO_NUM_XSTATS];\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuint32_t xstats_mode_count = 0;\n+\tuint32_t start_offset = 0;\n+\tunsigned int xidx = 0;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < OTX2_SSO_NUM_HWS_XSTATS; i++) {\n+\t\tsnprintf(xstats_names_copy[i].name,\n+\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n+\t\t\t sso_hws_xstats[i].name);\n+\t}\n+\n+\tfor (; i < OTX2_SSO_NUM_XSTATS; i++) {\n+\t\tsnprintf(xstats_names_copy[i].name,\n+\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n+\t\t\t sso_grp_xstats[i - OTX2_SSO_NUM_HWS_XSTATS].name);\n+\t}\n+\n+\tswitch (mode) {\n+\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_PORT:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n+\t\t\tbreak;\n+\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\tbreak;\n+\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n+\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n+\t\t\tbreak;\n+\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n+\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n+\t\tbreak;\n+\tdefault:\n+\t\totx2_err(\"Invalid mode received\");\n+\t\treturn -EINVAL;\n+\t};\n+\n+\tif (xstats_mode_count > size || !ids || !xstats_names)\n+\t\treturn xstats_mode_count;\n+\n+\tfor (i = 0; i < xstats_mode_count; i++) {\n+\t\txidx = i + start_offset;\n+\t\tstrncpy(xstats_names[i].name, xstats_names_copy[xidx].name,\n+\t\t\tsizeof(xstats_names[i].name));\n+\t\tids[i] = xidx;\n+\t}\n+\n+\treturn i;\n+}\n+\n+#endif\n",
    "prefixes": [
        "v3",
        "13/42"
    ]
}