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GET /api/patches/55577/?format=api
{ "id": 55577, "url": "http://patches.dpdk.org/api/patches/55577/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-43-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-43-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-43-pbhagavatula@marvell.com", "date": "2019-06-28T07:50:21", "name": "[v2,42/44] event/octeontx2: add devargs to limit timer adapters", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "65277cc74b55bd50f27bb486b1e19a2d093154c5", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-43-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55577/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55577/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0EC271BB6F;\n\tFri, 28 Jun 2019 09:52:58 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7BBE51B9AA\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:51:57 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7ofnx025743 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:56 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6mg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:56 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:51:55 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:51:54 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id D84233F7040;\n\tFri, 28 Jun 2019 00:51:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=a06FMPRrs5rQ09iAlIbcdZgd9UKrcpDt4G7UyMPRQYI=;\n\tb=DzmEWAnkiq91vB11AaXp3NqmxaSqxh6EiWz9rD7h3hf04BaDX7E/7xNmnvysXj/mkAKk\n\tmGWFhMXFwQ9WBr3XngB6cNNckP7a0ZYrpALt74+F6AMSkPbFrj4xJ9WXT273oeL47zQO\n\tQvEoKkZh//0/WCUO9DH3xuqWLNRd/JyQ6iN3Tsf/E8ZCgI+8Ls5OdU24Lr4sfbZrWky1\n\tnzKVU93emOGWMV3psMUSjqwT1fEI9H5Tq0r22HFwMXC3nyjfxcBNRqX0inA+ZzRzNdNS\n\tyYSPZR7EPDxaDfN3OfAkkjKEpqAzpacI5tgivUTFazFip+4nfyfC4mQBHAXODueT0B8E\n\t5Q== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:20:21 +0530", "Message-ID": "<20190628075024.404-43-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 42/44] event/octeontx2: add devargs to limit\n\ttimer adapters", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs to limit the max number of TIM rings reserved on probe.\nSince, TIM rings are HW resources we can avoid starving other\napplications by not grabbing all the rings.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_rings_lmt=2\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 6 +++++-\n drivers/event/octeontx2/otx2_tim_evdev.h | 1 +\n 2 files changed, 6 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex cd9a679fb..c312bd541 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -527,6 +527,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n #define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n #define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n #define OTX2_TIM_STATS_ENA\t\"tim_stats_ena\"\n+#define OTX2_TIM_RINGS_LMT\t\"tim_rings_lmt\"\n \n static void\n tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n@@ -546,6 +547,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n \t\t\t &parse_kvargs_value, &dev->chunk_slots);\n \trte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,\n \t\t\t &dev->enable_stats);\n+\trte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value,\n+\t\t\t &dev->min_ring_cnt);\n }\n \n void\n@@ -583,7 +586,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n-\tdev->nb_rings = rsrc_cnt->tim;\n+\tdev->nb_rings = dev->min_ring_cnt ?\n+\t\tRTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim;\n \n \tif (!dev->nb_rings) {\n \t\totx2_tim_dbg(\"No TIM Logical functions provisioned.\");\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex c8d16b03f..5af724ef9 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -121,6 +121,7 @@ struct otx2_tim_evdev {\n \t/* Dev args */\n \tuint8_t disable_npa;\n \tuint16_t chunk_slots;\n+\tuint16_t min_ring_cnt;\n \tuint8_t enable_stats;\n \t/* MSIX offsets */\n \tuint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];\n", "prefixes": [ "v2", "42/44" ] }