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GET /api/patches/55567/?format=api
{ "id": 55567, "url": "http://patches.dpdk.org/api/patches/55567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-33-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-33-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-33-pbhagavatula@marvell.com", "date": "2019-06-28T07:50:11", "name": "[v2,32/44] event/octeontx2: add devargs to modify chunk slots", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e4b715fd2a6ba3516db9c14d6cfb0551db2cdd1f", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-33-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55567/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 19DBD1BAA7;\n\tFri, 28 Jun 2019 09:52:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 44D065398\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:51:37 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7occP025662 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:36 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6kx-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:36 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:51:34 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:51:34 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id BF56B3F7040;\n\tFri, 28 Jun 2019 00:51:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=i4tJje4IX5Q4ipQTtjDIJ/HpTYNBGeAJ6rvGLXgs9ks=;\n\tb=jURxcGpYpNY9vEptk/BX+ycwZWm2sicZK3T5Z6BnI3NnAHbiCh6X72rRdqP4O8cfXLZc\n\t8wXWJ3vg+PXuGYiLvoePpPJO1oKKqyvu1KCF7c5Zl7ElConuKkedMoHY/I4O9ACEPThG\n\tdos0E8nPg7nSk3FIxO42PyxOFvtdoSIof6x5ExLPwkALEGE+7VVmjlop8NU5ktMsnINs\n\tEb3SfhLEb9aNNcuddfa5gq9ExmD/g2CfR47tZmyfgmXGRcsNLJO6MjjDvESARLCPIs55\n\tarfXfXrxKMJC7okWPwaWsHXe7o/zlIN0hJuJXlsfG/KC3VIHBmHFu+bI6xTeBH+zKVJW\n\tJA== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:20:11 +0530", "Message-ID": "<20190628075024.404-33-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 32/44] event/octeontx2: add devargs to modify\n\tchunk slots", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs support to modify number of chunk slots. Chunks are used to\nstore event timers, a chunk can be visualised as an array where the last\nelement points to the next chunk and rest of them are used to store\nevents. TIM traverses the list of chunks and enqueues the event timers\nto SSO.\nIf no argument is passed then a default value of 255 is taken.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_chnk_slots=511\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 14 +++++++++++++-\n drivers/event/octeontx2/otx2_tim_evdev.h | 4 ++++\n 2 files changed, 17 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex 4b9816676..c0a692bb5 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);\n \ttim_ring->max_tout = rcfg->max_tmo_ns;\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n-\ttim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;\n+\ttim_ring->chunk_sz = dev->chunk_sz;\n \tnb_timers = rcfg->nb_timers;\n \ttim_ring->disable_npa = dev->disable_npa;\n \n@@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n }\n \n #define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n+#define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n \n static void\n tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n@@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n \n \trte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,\n \t\t\t &parse_kvargs_flag, &dev->disable_npa);\n+\trte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,\n+\t\t\t &parse_kvargs_value, &dev->chunk_slots);\n }\n \n void\n@@ -423,6 +426,15 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n+\tif (dev->chunk_slots &&\n+\t dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&\n+\t dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {\n+\t\tdev->chunk_sz = (dev->chunk_slots + 1) *\n+\t\t\tOTX2_TIM_CHUNK_ALIGNMENT;\n+\t} else {\n+\t\tdev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;\n+\t}\n+\n \treturn;\n \n mz_free:\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 0a0a0b4d8..9636d8414 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -22,6 +22,8 @@\n #define OTX2_TIM_RING_DEF_CHUNK_SZ\t(4096)\n #define OTX2_TIM_CHUNK_ALIGNMENT\t(16)\n #define OTX2_TIM_NB_CHUNK_SLOTS(sz)\t(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)\n+#define OTX2_TIM_MIN_CHUNK_SLOTS\t(0x1)\n+#define OTX2_TIM_MAX_CHUNK_SLOTS\t(0x1FFE)\n #define OTX2_TIM_MIN_TMO_TKS\t\t(256)\n \n enum otx2_tim_clk_src {\n@@ -54,9 +56,11 @@ struct otx2_tim_evdev {\n \tstruct rte_eventdev *event_dev;\n \tstruct otx2_mbox *mbox;\n \tuint16_t nb_rings;\n+\tuint32_t chunk_sz;\n \tuintptr_t bar2;\n \t/* Dev args */\n \tuint8_t disable_npa;\n+\tuint16_t chunk_slots;\n };\n \n struct otx2_tim_ring {\n", "prefixes": [ "v2", "32/44" ] }