Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/55552/?format=api
{ "id": 55552, "url": "http://patches.dpdk.org/api/patches/55552/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-18-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-18-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-18-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:56", "name": "[v2,17/44] event/octeontx2: add octeontx2 SSO dual workslot mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "663f02bc1be26414f1573f90ec6d408500d824c3", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-18-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55552/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55552/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 31B771B9C5;\n\tFri, 28 Jun 2019 09:51:21 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 572C81B9CB\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:51:05 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7ngqp000482 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:04 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd778arr-2\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:51:04 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:51:02 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:51:02 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 9BEF73F7040;\n\tFri, 28 Jun 2019 00:51:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=8Am0ILCtdE3oj6/ChaA6Le2VTSz4VLIr6Bvg8SQNTYA=;\n\tb=Kiuy+nUoGVZfkJzyvq54BCxydbUqJnKtd8hFVnyUVcQXn/rwC63jPCDO140TNlxXfdnA\n\tXT1eTg6y2dKppxMLnI/OOPwcpAjkWzZAjGBYZKJeEBpAACAvU8mn0KpgTaL0IUmBAyQM\n\tbFoRtXh7PKpc0XvEvAQtIB7v6pEEr/BEcCHF3zcD0tEnQcXaNr9rWyqMVosVeiiwg044\n\tNDiO3ggiwO5q6pK2Y3ixX/slY+eo0Y6yyoQH1uf1EqwTtwy0Tcy383UONDoAI+5vHueF\n\tjSkJDjHiO1rkwaIdB6RJZcX/W2A0Kq9VPG9u4X7evF+3tvKQvCJAY/BFVVDdvtQA2nRW\n\tBg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:56 +0530", "Message-ID": "<20190628075024.404-18-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 17/44] event/octeontx2: add octeontx2 SSO dual\n\tworkslot mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nOcteonTx2 AP core SSO cache contains two entires each entry caches\nstate of an single GWS aka event port.\nAP core requests events from SSO by using following sequence :\n1. Write to SSOW_LF_GWS_OP_GET_WORK\n2. Wait for SSO to complete scheduling by polling on SSOW_LF_GWS_TAG[63]\n3. SSO notifies core by clearing SSOW_LF_GWS_TAG[63] and if work is\nvalid SSOW_LF_GWS_WQP is non-zero.\nThe above sequence uses only one in-core cache entry.\n\nIn dual workslot mode we try to use both the in-core cache entries by\ntriggering GET_WORK on a second workslot as soon as the above sequence\ncompletes. This effectively hides the schedule latency of SSO if there\nare enough events with unique flow_tags in-flight.\nThis mode reserves two SSO GWS lf's for each event port effectively\ndoubling single core performance.\nDual workslot mode is the default mode of operation in octeontx2.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 204 ++++++++++++++++++---\n drivers/event/octeontx2/otx2_evdev.h | 17 ++\n drivers/event/octeontx2/otx2_evdev_irq.c | 4 +-\n drivers/event/octeontx2/otx2_evdev_stats.h | 52 +++++-\n 4 files changed, 242 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 51220f447..16d5e7dfa 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -20,7 +20,7 @@ static inline int\n sso_get_msix_offsets(const struct rte_eventdev *event_dev)\n {\n \tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t nb_ports = dev->nb_event_ports;\n+\tuint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n \tstruct otx2_mbox *mbox = dev->mbox;\n \tstruct msix_offset_rsp *msix_rsp;\n \tint i, rc;\n@@ -82,16 +82,26 @@ otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,\n \t\t const uint8_t queues[], const uint8_t priorities[],\n \t\t uint16_t nb_links)\n {\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n \tuint8_t port_id = 0;\n \tuint16_t link;\n \n-\tRTE_SET_USED(event_dev);\n \tRTE_SET_USED(priorities);\n \tfor (link = 0; link < nb_links; link++) {\n-\t\tstruct otx2_ssogws *ws = port;\n-\n-\t\tport_id = ws->port;\n-\t\tsso_port_link_modify(ws, queues[link], true);\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws = port;\n+\n+\t\t\tport_id = ws->port;\n+\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t&ws->ws_state[0], queues[link], true);\n+\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t&ws->ws_state[1], queues[link], true);\n+\t\t} else {\n+\t\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\t\tport_id = ws->port;\n+\t\t\tsso_port_link_modify(ws, queues[link], true);\n+\t\t}\n \t}\n \tsso_func_trace(\"Port=%d nb_links=%d\", port_id, nb_links);\n \n@@ -102,15 +112,27 @@ static int\n otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n \t\t uint8_t queues[], uint16_t nb_unlinks)\n {\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n \tuint8_t port_id = 0;\n \tuint16_t unlink;\n \n-\tRTE_SET_USED(event_dev);\n \tfor (unlink = 0; unlink < nb_unlinks; unlink++) {\n-\t\tstruct otx2_ssogws *ws = port;\n-\n-\t\tport_id = ws->port;\n-\t\tsso_port_link_modify(ws, queues[unlink], false);\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws = port;\n+\n+\t\t\tport_id = ws->port;\n+\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t&ws->ws_state[0], queues[unlink],\n+\t\t\t\t\tfalse);\n+\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t&ws->ws_state[1], queues[unlink],\n+\t\t\t\t\tfalse);\n+\t\t} else {\n+\t\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\t\tport_id = ws->port;\n+\t\t\tsso_port_link_modify(ws, queues[unlink], false);\n+\t\t}\n \t}\n \tsso_func_trace(\"Port=%d nb_unlinks=%d\", port_id, nb_unlinks);\n \n@@ -242,11 +264,23 @@ sso_clr_links(const struct rte_eventdev *event_dev)\n \tint i, j;\n \n \tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tstruct otx2_ssogws *ws;\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws;\n \n-\t\tws = event_dev->data->ports[i];\n-\t\tfor (j = 0; j < dev->nb_event_queues; j++)\n-\t\t\tsso_port_link_modify(ws, j, false);\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\tfor (j = 0; j < dev->nb_event_queues; j++) {\n+\t\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t\t&ws->ws_state[0], j, false);\n+\t\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n+\t\t\t\t\t\t&ws->ws_state[1], j, false);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tstruct otx2_ssogws *ws;\n+\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\tfor (j = 0; j < dev->nb_event_queues; j++)\n+\t\t\t\tsso_port_link_modify(ws, j, false);\n+\t\t}\n \t}\n }\n \n@@ -261,6 +295,73 @@ sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)\n \tws->swtag_desched_op\t= base + SSOW_LF_GWS_OP_SWTAG_DESCHED;\n }\n \n+static int\n+sso_configure_dual_ports(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint8_t vws = 0;\n+\tuint8_t nb_lf;\n+\tint i, rc;\n+\n+\totx2_sso_dbg(\"Configuring event ports %d\", dev->nb_event_ports);\n+\n+\tnb_lf = dev->nb_event_ports * 2;\n+\t/* Ask AF to attach required LFs. */\n+\trc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to attach SSO GWS LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {\n+\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n+\t\totx2_err(\"Failed to init SSO GWS LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tstruct otx2_ssogws_dual *ws;\n+\t\tuintptr_t base;\n+\n+\t\t/* Free memory prior to re-allocation if needed */\n+\t\tif (event_dev->data->ports[i] != NULL) {\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\trte_free(ws);\n+\t\t\tws = NULL;\n+\t\t}\n+\n+\t\t/* Allocate event port memory */\n+\t\tws = rte_zmalloc_socket(\"otx2_sso_ws\",\n+\t\t\t\t\tsizeof(struct otx2_ssogws_dual),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\t\tevent_dev->data->socket_id);\n+\t\tif (ws == NULL) {\n+\t\t\totx2_err(\"Failed to alloc memory for port=%d\", i);\n+\t\t\trc = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tws->port = i;\n+\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);\n+\t\tsso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);\n+\t\tvws++;\n+\n+\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);\n+\t\tsso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);\n+\t\tvws++;\n+\n+\t\tevent_dev->data->ports[i] = ws;\n+\t}\n+\n+\tif (rc < 0) {\n+\t\tsso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);\n+\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n+\t}\n+\n+\treturn rc;\n+}\n+\n static int\n sso_configure_ports(const struct rte_eventdev *event_dev)\n {\n@@ -465,6 +566,7 @@ sso_lf_teardown(struct otx2_sso_evdev *dev,\n \t\tbreak;\n \tcase SSO_LF_GWS:\n \t\tnb_lf = dev->nb_event_ports;\n+\t\tnb_lf *= dev->dual_ws ? 2 : 1;\n \t\tbreak;\n \tdefault:\n \t\treturn;\n@@ -530,7 +632,12 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \tdev->nb_event_queues = conf->nb_event_queues;\n \tdev->nb_event_ports = conf->nb_event_ports;\n \n-\tif (sso_configure_ports(event_dev)) {\n+\tif (dev->dual_ws)\n+\t\trc = sso_configure_dual_ports(event_dev);\n+\telse\n+\t\trc = sso_configure_ports(event_dev);\n+\n+\tif (rc < 0) {\n \t\totx2_err(\"Failed to configure event ports\");\n \t\treturn -ENODEV;\n \t}\n@@ -660,14 +767,27 @@ otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n \t/* Set get_work timeout for HWS */\n \tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n \n-\tstruct otx2_ssogws *ws = event_dev->data->ports[port_id];\n-\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n-\n-\trte_memcpy(ws->grps_base, grps_base,\n-\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n-\tws->fc_mem = dev->fc_mem;\n-\tws->xaq_lmt = dev->xaq_lmt;\n-\totx2_write64(val, base + SSOW_LF_GWS_NW_TIM);\n+\tif (dev->dual_ws) {\n+\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];\n+\n+\t\trte_memcpy(ws->grps_base, grps_base,\n+\t\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n+\t\tws->fc_mem = dev->fc_mem;\n+\t\tws->xaq_lmt = dev->xaq_lmt;\n+\t\totx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(\n+\t\t\t ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);\n+\t\totx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(\n+\t\t\t ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);\n+\t} else {\n+\t\tstruct otx2_ssogws *ws = event_dev->data->ports[port_id];\n+\t\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n+\n+\t\trte_memcpy(ws->grps_base, grps_base,\n+\t\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n+\t\tws->fc_mem = dev->fc_mem;\n+\t\tws->xaq_lmt = dev->xaq_lmt;\n+\t\totx2_write64(val, base + SSOW_LF_GWS_NW_TIM);\n+\t}\n \n \totx2_sso_dbg(\"Port=%d ws=%p\", port_id, event_dev->data->ports[port_id]);\n \n@@ -735,18 +855,37 @@ otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)\n \tuint8_t queue;\n \tuint8_t port;\n \n+\tfprintf(f, \"[%s] SSO running in [%s] mode\\n\", __func__, dev->dual_ws ?\n+\t\t\"dual_ws\" : \"single_ws\");\n \t/* Dump SSOW registers */\n \tfor (port = 0; port < dev->nb_event_ports; port++) {\n-\t\tfprintf(f, \"[%s]SSO single workslot[%d] dump\\n\",\n-\t\t\t__func__, port);\n-\t\tssogws_dump(event_dev->data->ports[port], f);\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws =\n+\t\t\t\tevent_dev->data->ports[port];\n+\n+\t\t\tfprintf(f, \"[%s] SSO dual workslot[%d] vws[%d] dump\\n\",\n+\t\t\t\t__func__, port, 0);\n+\t\t\tssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);\n+\t\t\tfprintf(f, \"[%s]SSO dual workslot[%d] vws[%d] dump\\n\",\n+\t\t\t\t__func__, port, 1);\n+\t\t\tssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);\n+\t\t} else {\n+\t\t\tfprintf(f, \"[%s]SSO single workslot[%d] dump\\n\",\n+\t\t\t\t__func__, port);\n+\t\t\tssogws_dump(event_dev->data->ports[port], f);\n+\t\t}\n \t}\n \n \t/* Dump SSO registers */\n \tfor (queue = 0; queue < dev->nb_event_queues; queue++) {\n \t\tfprintf(f, \"[%s]SSO group[%d] dump\\n\", __func__, queue);\n-\t\tstruct otx2_ssogws *ws = event_dev->data->ports[0];\n-\t\tssoggrp_dump(ws->grps_base[queue], f);\n+\t\tif (dev->dual_ws) {\n+\t\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[0];\n+\t\t\tssoggrp_dump(ws->grps_base[queue], f);\n+\t\t} else {\n+\t\t\tstruct otx2_ssogws *ws = event_dev->data->ports[0];\n+\t\t\tssoggrp_dump(ws->grps_base[queue], f);\n+\t\t}\n \t}\n }\n \n@@ -879,7 +1018,14 @@ otx2_sso_init(struct rte_eventdev *event_dev)\n \t\tgoto otx2_npa_lf_uninit;\n \t}\n \n+\tdev->dual_ws = 1;\n \tsso_parse_devargs(dev, pci_dev->device.devargs);\n+\tif (dev->dual_ws) {\n+\t\totx2_sso_dbg(\"Using dual workslot mode\");\n+\t\tdev->max_event_ports = dev->max_event_ports / 2;\n+\t} else {\n+\t\totx2_sso_dbg(\"Using single workslot mode\");\n+\t}\n \n \totx2_sso_pf_func_set(dev->pf_func);\n \totx2_sso_dbg(\"Initializing %s max_queues=%d max_ports=%d\",\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 6f8d709b6..72de9ace5 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -121,6 +121,7 @@ struct otx2_sso_evdev {\n \tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n+\tuint8_t dual_ws;\n \t/* Dev args */\n \tuint32_t xae_cnt;\n \t/* HW const */\n@@ -155,6 +156,22 @@ struct otx2_ssogws {\n \tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP];\n } __rte_cache_aligned;\n \n+struct otx2_ssogws_state {\n+\tOTX2_SSOGWS_OPS;\n+};\n+\n+struct otx2_ssogws_dual {\n+\t/* Get Work Fastpath data */\n+\tstruct otx2_ssogws_state ws_state[2]; /* Ping and Pong */\n+\tuint8_t swtag_req;\n+\tuint8_t vws; /* Ping pong bit */\n+\tuint8_t port;\n+\t/* Add Work Fastpath data */\n+\tuint64_t xaq_lmt __rte_cache_aligned;\n+\tuint64_t *fc_mem;\n+\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP];\n+} __rte_cache_aligned;\n+\n static inline struct otx2_sso_evdev *\n sso_pmd_priv(const struct rte_eventdev *event_dev)\n {\ndiff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c\nindex 7df21cc24..7379bb17f 100644\n--- a/drivers/event/octeontx2/otx2_evdev_irq.c\n+++ b/drivers/event/octeontx2/otx2_evdev_irq.c\n@@ -117,7 +117,7 @@ sso_register_irqs(const struct rte_eventdev *event_dev)\n \tint i, rc = -EINVAL;\n \tuint8_t nb_ports;\n \n-\tnb_ports = dev->nb_event_ports;\n+\tnb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n \n \tfor (i = 0; i < dev->nb_event_queues; i++) {\n \t\tif (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {\n@@ -159,7 +159,7 @@ sso_unregister_irqs(const struct rte_eventdev *event_dev)\n \tuint8_t nb_ports;\n \tint i;\n \n-\tnb_ports = dev->nb_event_ports;\n+\tnb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n \n \tfor (i = 0; i < dev->nb_event_queues; i++) {\n \t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |\ndiff --git a/drivers/event/octeontx2/otx2_evdev_stats.h b/drivers/event/octeontx2/otx2_evdev_stats.h\nindex df76a1333..9d7c694ee 100644\n--- a/drivers/event/octeontx2/otx2_evdev_stats.h\n+++ b/drivers/event/octeontx2/otx2_evdev_stats.h\n@@ -76,11 +76,29 @@ otx2_sso_xstats_get(const struct rte_eventdev *event_dev,\n \t\txstats = sso_hws_xstats;\n \n \t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->hws = queue_port_id;\n+\t\t\t((struct sso_info_req *)req_rsp)->hws = dev->dual_ws ?\n+\t\t\t\t\t2 * queue_port_id : queue_port_id;\n \t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n \t\tif (rc < 0)\n \t\t\tgoto invalid_value;\n \n+\t\tif (dev->dual_ws) {\n+\t\t\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\t\t\txstat = &xstats[ids[i] - start_offset];\n+\t\t\t\tvalues[i] = *(uint64_t *)\n+\t\t\t\t\t((char *)req_rsp + xstat->offset);\n+\t\t\t\tvalues[i] = (values[i] >> xstat->shift) &\n+\t\t\t\t\txstat->mask;\n+\t\t\t}\n+\n+\t\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n+\t\t\t((struct sso_info_req *)req_rsp)->hws =\n+\t\t\t\t\t(2 * queue_port_id) + 1;\n+\t\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n+\t\t\tif (rc < 0)\n+\t\t\t\tgoto invalid_value;\n+\t\t}\n+\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n \t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n@@ -107,7 +125,11 @@ otx2_sso_xstats_get(const struct rte_eventdev *event_dev,\n \t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n \t\tvalue = (value >> xstat->shift) & xstat->mask;\n \n-\t\tvalues[i] = value;\n+\t\tif ((mode == RTE_EVENT_DEV_XSTATS_PORT) && dev->dual_ws)\n+\t\t\tvalues[i] += value;\n+\t\telse\n+\t\t\tvalues[i] = value;\n+\n \t\tvalues[i] -= xstat->reset_snap[queue_port_id];\n \t}\n \n@@ -143,11 +165,30 @@ otx2_sso_xstats_reset(struct rte_eventdev *event_dev,\n \t\txstats = sso_hws_xstats;\n \n \t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t((struct sso_info_req *)req_rsp)->hws = queue_port_id;\n+\t\t((struct sso_info_req *)req_rsp)->hws = dev->dual_ws ?\n+\t\t\t2 * queue_port_id : queue_port_id;\n \t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n \t\tif (rc < 0)\n \t\t\tgoto invalid_value;\n \n+\t\tif (dev->dual_ws) {\n+\t\t\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n+\t\t\t\txstat = &xstats[ids[i] - start_offset];\n+\t\t\t\txstat->reset_snap[queue_port_id] = *(uint64_t *)\n+\t\t\t\t\t((char *)req_rsp + xstat->offset);\n+\t\t\t\txstat->reset_snap[queue_port_id] =\n+\t\t\t\t\t(xstat->reset_snap[queue_port_id] >>\n+\t\t\t\t\t\txstat->shift) & xstat->mask;\n+\t\t\t}\n+\n+\t\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n+\t\t\t((struct sso_info_req *)req_rsp)->hws =\n+\t\t\t\t\t(2 * queue_port_id) + 1;\n+\t\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n+\t\t\tif (rc < 0)\n+\t\t\t\tgoto invalid_value;\n+\t\t}\n+\n \t\tbreak;\n \tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n \t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n@@ -174,7 +215,10 @@ otx2_sso_xstats_reset(struct rte_eventdev *event_dev,\n \t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n \t\tvalue = (value >> xstat->shift) & xstat->mask;\n \n-\t\txstat->reset_snap[queue_port_id] = value;\n+\t\tif ((mode == RTE_EVENT_DEV_XSTATS_PORT) && dev->dual_ws)\n+\t\t\txstat->reset_snap[queue_port_id] += value;\n+\t\telse\n+\t\t\txstat->reset_snap[queue_port_id] = value;\n \t}\n \treturn i;\n invalid_value:\n", "prefixes": [ "v2", "17/44" ] }