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GET /api/patches/55544/?format=api
{ "id": 55544, "url": "http://patches.dpdk.org/api/patches/55544/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-10-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-10-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-10-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:48", "name": "[v2,09/44] event/octeontx2: support linking queues to ports", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e183db105b70b63468cb03212d6f74ab51935ef9", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-10-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55544/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55544/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1BA2B1B9BB;\n\tFri, 28 Jun 2019 09:50:58 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DD7411B9AB\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:50:48 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7oUA3025385 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:48 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6hd-2\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:48 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:50:46 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:50:46 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 5000A3F7045;\n\tFri, 28 Jun 2019 00:50:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=ZoSLcc9zIitQGS/1B1rMShfsy044h9up2LKYtmenP/s=;\n\tb=ragTH/vtJlIW64aLSvh9I+NpJoJUzfbdqDjM/gxCYan87N/xlo+JsgBjDkIMqIIRL3RM\n\tLveHzz0FXAFudfAxqfXfFv8OjzdIFYtT6yq5MMg8qbo8eIJH6sHEhjVd0/DyTt2rUiTi\n\tVpjFvgN+TgOeLeDNabTPcyEPMQcNTG4D3/JB0wIbD4vYTqX+Bi2SaXZEDKxV//NqrtxL\n\tbNZkj07m6iUpRdIVQnkWX/S2z97hiKVRnpK1lqFAFPQ3i6vnu6W0mQLMMGIGYnk+w61Q\n\tS99vR+Yy0r/xrpHSb1lwNK5Uy9CJpFDf/z1iPs+utPN3+KjFkRClPU2rBF7ApZXNEVIf\n\tgg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:48 +0530", "Message-ID": "<20190628075024.404-10-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 09/44] event/octeontx2: support linking queues\n\tto ports", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nLinks between queues and ports are controlled by setting/clearing GGRP\nmembership in SSOW_LF_GWS_GRPMSK_CHG.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 73 ++++++++++++++++++++++++++++\n 1 file changed, 73 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex a6bf861fb..53e68902a 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -39,6 +39,60 @@ otx2_sso_info_get(struct rte_eventdev *event_dev,\n \t\t\t\t\tRTE_EVENT_DEV_CAP_NONSEQ_MODE;\n }\n \n+static void\n+sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)\n+{\n+\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n+\tuint64_t val;\n+\n+\tval = queue;\n+\tval |= 0ULL << 12; /* SET 0 */\n+\tval |= 0x8000800080000000; /* Dont modify rest of the masks */\n+\tval |= (uint64_t)enable << 14; /* Enable/Disable Membership. */\n+\n+\totx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);\n+}\n+\n+static int\n+otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,\n+\t\t const uint8_t queues[], const uint8_t priorities[],\n+\t\t uint16_t nb_links)\n+{\n+\tuint8_t port_id = 0;\n+\tuint16_t link;\n+\n+\tRTE_SET_USED(event_dev);\n+\tRTE_SET_USED(priorities);\n+\tfor (link = 0; link < nb_links; link++) {\n+\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\tport_id = ws->port;\n+\t\tsso_port_link_modify(ws, queues[link], true);\n+\t}\n+\tsso_func_trace(\"Port=%d nb_links=%d\", port_id, nb_links);\n+\n+\treturn (int)nb_links;\n+}\n+\n+static int\n+otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n+\t\t uint8_t queues[], uint16_t nb_unlinks)\n+{\n+\tuint8_t port_id = 0;\n+\tuint16_t unlink;\n+\n+\tRTE_SET_USED(event_dev);\n+\tfor (unlink = 0; unlink < nb_unlinks; unlink++) {\n+\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\tport_id = ws->port;\n+\t\tsso_port_link_modify(ws, queues[unlink], false);\n+\t}\n+\tsso_func_trace(\"Port=%d nb_unlinks=%d\", port_id, nb_unlinks);\n+\n+\treturn (int)nb_unlinks;\n+}\n+\n static int\n sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,\n \t uint16_t nb_lf, uint8_t attach)\n@@ -157,6 +211,21 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n \tRTE_SET_USED(queue_id);\n }\n \n+static void\n+sso_clr_links(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tint i, j;\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tstruct otx2_ssogws *ws;\n+\n+\t\tws = event_dev->data->ports[i];\n+\t\tfor (j = 0; j < dev->nb_event_queues; j++)\n+\t\t\tsso_port_link_modify(ws, j, false);\n+\t}\n+}\n+\n static void\n sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)\n {\n@@ -450,6 +519,8 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \t\tgoto teardown_hwggrp;\n \t}\n \n+\t/* Clear any prior port-queue mapping. */\n+\tsso_clr_links(event_dev);\n \trc = sso_ggrp_alloc_xaq(dev);\n \tif (rc < 0) {\n \t\totx2_err(\"Failed to alloc xaq to ggrp %d\", rc);\n@@ -574,6 +645,8 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.port_def_conf = otx2_sso_port_def_conf,\n \t.port_setup = otx2_sso_port_setup,\n \t.port_release = otx2_sso_port_release,\n+\t.port_link = otx2_sso_port_link,\n+\t.port_unlink = otx2_sso_port_unlink,\n };\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n", "prefixes": [ "v2", "09/44" ] }