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GET /api/patches/55542/?format=api
http://patches.dpdk.org/api/patches/55542/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-8-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-8-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-8-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:46", "name": "[v2,07/44] event/octeontx2: add devargs for inflight buffer count", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1d50867e261158b7614dcabe78164ef26ee5c99a", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-8-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55542/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55542/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C281D1B9AF;\n\tFri, 28 Jun 2019 09:50:51 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 5C17B1B99F\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:50:44 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7oJxp001536 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:43 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd778aq8-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:43 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:50:42 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:50:42 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 3D7593F7041;\n\tFri, 28 Jun 2019 00:50:41 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=BBr6WfzM1ZbAdzNGUga8pkWv2TixHh1o+7T68XZJn/w=;\n\tb=rZcqRcZ6RbB/tUJZ8xPhWUdTnnmCHHNh55PEGVPq0EehRBLYfZl8sc1SEQZ4jKWf/a20\n\tMueQ8/BHjkUsLWype/GcSu2/XhodXf6IwcthOMp3BgvzIPXizlnNmpoaqcmEwOWsoz8p\n\tjUQEJaOfn5k4LcvmWZKv9wyzjYF4uWQ075RTmTI5bS8viVyU89hEy2tMdNgTpjyG6oeR\n\tBFcGb3SmNfy3dNJqbK2UQebUbMtiXVim9SGX0RJlBsK9ezynRWOBZk/xJYOcmvpymzMr\n\ts1hwZfhx7katdgU7976RyHapzcNrsVDSpq7VM9dObz8KDB/qJtfYykxuehIEBgTjXZDR\n\tnw== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:46 +0530", "Message-ID": "<20190628075024.404-8-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 07/44] event/octeontx2: add devargs for\n\tinflight buffer count", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nThe number of events for a *open system* event device is specified\nas -1 as per the eventdev specification.\nSince, Octeontx2 SSO inflight events are only limited by DRAM size, the\nxae_cnt devargs parameter is introduced to provide upper limit for\nin-flight events.\n\nExample:\n\t--dev \"0002:0e:00.0,xae_cnt=8192\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/Makefile | 2 +-\n drivers/event/octeontx2/otx2_evdev.c | 28 +++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 11 +++++++++++\n 3 files changed, 39 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex b3c3beccb..58853e1b9 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -32,7 +32,7 @@ LIBABIVER := 1\n \n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n \n-LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci\n+LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs\n LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf\n LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex fc4dbda0a..94c97fc9e 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -8,6 +8,7 @@\n #include <rte_common.h>\n #include <rte_eal.h>\n #include <rte_eventdev_pmd_pci.h>\n+#include <rte_kvargs.h>\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n@@ -245,7 +246,10 @@ sso_xaq_allocate(struct otx2_sso_evdev *dev)\n \n \t/* Taken from HRM 14.3.3(4) */\n \txaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;\n-\txaq_cnt += (dev->iue / dev->xae_waes) +\n+\tif (dev->xae_cnt)\n+\t\txaq_cnt += dev->xae_cnt / dev->xae_waes;\n+\telse\n+\t\txaq_cnt += (dev->iue / dev->xae_waes) +\n \t\t\t(OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);\n \n \totx2_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n@@ -464,6 +468,25 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.queue_release = otx2_sso_queue_release,\n };\n \n+#define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n+\n+static void\n+sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\treturn;\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\treturn;\n+\n+\trte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,\n+\t\t\t &dev->xae_cnt);\n+\n+\trte_kvargs_free(kvlist);\n+}\n+\n static int\n otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n {\n@@ -553,6 +576,8 @@ otx2_sso_init(struct rte_eventdev *event_dev)\n \t\tgoto otx2_npa_lf_uninit;\n \t}\n \n+\tsso_parse_devargs(dev, pci_dev->device.devargs);\n+\n \totx2_sso_pf_func_set(dev->pf_func);\n \totx2_sso_dbg(\"Initializing %s max_queues=%d max_ports=%d\",\n \t\t event_dev->data->name, dev->max_event_queues,\n@@ -601,3 +626,4 @@ otx2_sso_fini(struct rte_eventdev *event_dev)\n RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 375640bca..acc8b6b3e 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -62,6 +62,8 @@ struct otx2_sso_evdev {\n \tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n+\t/* Dev args */\n+\tuint32_t xae_cnt;\n \t/* HW const */\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n@@ -74,6 +76,15 @@ sso_pmd_priv(const struct rte_eventdev *event_dev)\n \treturn event_dev->data->dev_private;\n }\n \n+static inline int\n+parse_kvargs_value(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint32_t *)opaque = (uint32_t)atoi(value);\n+\treturn 0;\n+}\n+\n /* Init and Fini API's */\n int otx2_sso_init(struct rte_eventdev *event_dev);\n int otx2_sso_fini(struct rte_eventdev *event_dev);\n", "prefixes": [ "v2", "07/44" ] }{ "id": 55542, "url": "