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GET /api/patches/55541/?format=api
{ "id": 55541, "url": "http://patches.dpdk.org/api/patches/55541/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-7-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-7-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-7-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:45", "name": "[v2,06/44] event/octeontx2: allocate event inflight buffers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "445ebebb8958ff87c752734193c271e22858c1a0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-7-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55541/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55541/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F0D621B9AD;\n\tFri, 28 Jun 2019 09:50:48 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 70A9D4CA9\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:50:42 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7niRu000486 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:41 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd778aq0-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:41 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:50:40 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:50:40 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 26FCC3F7041;\n\tFri, 28 Jun 2019 00:50:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=hby2vVojWRN1HzXIMQjlTnFmJqVJicPR6zvzw4tUfnI=;\n\tb=Y6HjicGAXHI159kdeUGlr+f5ZZaP69Fp+MqemwvKzEtwjIIv+0QAzavfOXcG/XpEmBIX\n\tJUOat9g4JS/FrZH/g2ea1tPmlgGh+aPQixNODxB+aFmy3ji5mMQKV7EM7vS+H/eF5cD9\n\tU8pUDjwMypOO6jiWL7LCW3Kdthy0qL6GFBBMMxXqjbj7Rp4B5jwzT7cAMmenmEL7EVQ6\n\t7pDfHxDUt+uvDTuXqeoftm1Jh93GVxtDcRGnGURyPaasAnoyiaF9tpm++p2TRUVVi1iX\n\tpjtOTcvtKrphl1pcZpMgDPkr2XkkMjtQhDuRUlRyEKyWcmvQOfL7aFEZLb+MKEEIxBas\n\tQQ== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:45 +0530", "Message-ID": "<20190628075024.404-7-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 06/44] event/octeontx2: allocate event\n\tinflight buffers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAllocate buffers in DRAM that hold inflight events.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/Makefile | 2 +-\n drivers/event/octeontx2/otx2_evdev.c | 116 ++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 8 ++\n 3 files changed, 124 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex 36f0b2b12..b3c3beccb 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -33,7 +33,7 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n \n LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci\n-LDLIBS += -lrte_eventdev\n+LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf\n LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 2290598d0..fc4dbda0a 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -8,6 +8,7 @@\n #include <rte_common.h>\n #include <rte_eal.h>\n #include <rte_eventdev_pmd_pci.h>\n+#include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n #include \"otx2_evdev.h\"\n@@ -203,6 +204,107 @@ sso_configure_queues(const struct rte_eventdev *event_dev)\n \treturn rc;\n }\n \n+static int\n+sso_xaq_allocate(struct otx2_sso_evdev *dev)\n+{\n+\tconst struct rte_memzone *mz;\n+\tstruct npa_aura_s *aura;\n+\tstatic int reconfig_cnt;\n+\tchar pool_name[RTE_MEMZONE_NAMESIZE];\n+\tuint32_t xaq_cnt;\n+\tint rc;\n+\n+\tif (dev->xaq_pool)\n+\t\trte_mempool_free(dev->xaq_pool);\n+\n+\t/*\n+\t * Allocate memory for Add work backpressure.\n+\t */\n+\tmz = rte_memzone_lookup(OTX2_SSO_FC_NAME);\n+\tif (mz == NULL)\n+\t\tmz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,\n+\t\t\t\t\t\t OTX2_ALIGN +\n+\t\t\t\t\t\t sizeof(struct npa_aura_s),\n+\t\t\t\t\t\t rte_socket_id(),\n+\t\t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG,\n+\t\t\t\t\t\t OTX2_ALIGN);\n+\tif (mz == NULL) {\n+\t\totx2_err(\"Failed to allocate mem for fcmem\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tdev->fc_iova = mz->iova;\n+\tdev->fc_mem = mz->addr;\n+\n+\taura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);\n+\tmemset(aura, 0, sizeof(struct npa_aura_s));\n+\n+\taura->fc_ena = 1;\n+\taura->fc_addr = dev->fc_iova;\n+\taura->fc_hyst_bits = 0; /* Store count on all updates */\n+\n+\t/* Taken from HRM 14.3.3(4) */\n+\txaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;\n+\txaq_cnt += (dev->iue / dev->xae_waes) +\n+\t\t\t(OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);\n+\n+\totx2_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n+\t/* Setup XAQ based on number of nb queues. */\n+\tsnprintf(pool_name, 30, \"otx2_xaq_buf_pool_%d\", reconfig_cnt);\n+\tdev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,\n+\t\t\txaq_cnt, dev->xaq_buf_size, 0, 0,\n+\t\t\trte_socket_id(), 0);\n+\n+\tif (dev->xaq_pool == NULL) {\n+\t\totx2_err(\"Unable to create empty mempool.\");\n+\t\trte_memzone_free(mz);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trc = rte_mempool_set_ops_byname(dev->xaq_pool,\n+\t\t\t\t\trte_mbuf_platform_mempool_ops(), aura);\n+\tif (rc != 0) {\n+\t\totx2_err(\"Unable to set xaqpool ops.\");\n+\t\tgoto alloc_fail;\n+\t}\n+\n+\trc = rte_mempool_populate_default(dev->xaq_pool);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Unable to set populate xaqpool.\");\n+\t\tgoto alloc_fail;\n+\t}\n+\treconfig_cnt++;\n+\t/* When SW does addwork (enqueue) check if there is space in XAQ by\n+\t * comparing fc_addr above against the xaq_lmt calculated below.\n+\t * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO\n+\t * to request XAQ to cache them even before enqueue is called.\n+\t */\n+\tdev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *\n+\t\t\t\t dev->nb_event_queues);\n+\tdev->nb_xaq_cfg = xaq_cnt;\n+\n+\treturn 0;\n+alloc_fail:\n+\trte_mempool_free(dev->xaq_pool);\n+\trte_memzone_free(mz);\n+\treturn rc;\n+}\n+\n+static int\n+sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct sso_hw_setconfig *req;\n+\n+\totx2_sso_dbg(\"Configuring XAQ for GGRPs\");\n+\treq = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);\n+\treq->npa_pf_func = otx2_npa_pf_func_get();\n+\treq->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);\n+\treq->hwgrps = dev->nb_event_queues;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n static void\n sso_lf_teardown(struct otx2_sso_evdev *dev,\n \t\tenum otx2_sso_lf_type lf_type)\n@@ -288,11 +390,23 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \t\tgoto teardown_hws;\n \t}\n \n+\tif (sso_xaq_allocate(dev) < 0) {\n+\t\trc = -ENOMEM;\n+\t\tgoto teardown_hwggrp;\n+\t}\n+\n+\trc = sso_ggrp_alloc_xaq(dev);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to alloc xaq to ggrp %d\", rc);\n+\t\tgoto teardown_hwggrp;\n+\t}\n+\n \tdev->configured = 1;\n \trte_mb();\n \n \treturn 0;\n-\n+teardown_hwggrp:\n+\tsso_lf_teardown(dev, SSO_LF_GGRP);\n teardown_hws:\n \tsso_lf_teardown(dev, SSO_LF_GWS);\n \tdev->nb_event_queues = 0;\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex b46402771..375640bca 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -17,6 +17,9 @@\n \n #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV\n #define OTX2_SSO_MAX_VHWS (UINT8_MAX)\n+#define OTX2_SSO_FC_NAME \"otx2_evdev_xaq_fc\"\n+#define OTX2_SSO_XAQ_SLACK (8)\n+#define OTX2_SSO_XAQ_CACHE_CNT (0x7)\n \n /* SSO LF register offsets (BAR2) */\n #define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)\n@@ -54,6 +57,11 @@ struct otx2_sso_evdev {\n \tuint32_t min_dequeue_timeout_ns;\n \tuint32_t max_dequeue_timeout_ns;\n \tint32_t max_num_events;\n+\tuint64_t *fc_mem;\n+\tuint64_t xaq_lmt;\n+\tuint64_t nb_xaq_cfg;\n+\trte_iova_t fc_iova;\n+\tstruct rte_mempool *xaq_pool;\n \t/* HW const */\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n", "prefixes": [ "v2", "06/44" ] }