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GET /api/patches/55540/?format=api
{ "id": 55540, "url": "http://patches.dpdk.org/api/patches/55540/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-5-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-5-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-5-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:43", "name": "[v2,04/44] event/octeontx2: add device configure function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e1f8ed6463079618e522a2600c6d36e63232f92d", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-5-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55540/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55540/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AE8FA1B99F;\n\tFri, 28 Jun 2019 09:50:45 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 4FA5D4C8B\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:50:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7obro025652 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:38 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6gu-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:38 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:50:36 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:50:36 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 1A4D23F7041;\n\tFri, 28 Jun 2019 00:50:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=ia40nH+gAUVSuh0AUCwGaM+6/TQQEJEYDR6kjsPzKqc=;\n\tb=rLaMLmyZdCrT1r+pUDyVr4x7e3Yw5PhNDHgZEkt6KaIcp/4o/jhWZfQWgglqXEsldwgq\n\tsPtaymJE5Si6TLDhqouOTVame9IaiTS1bjueW6S/AQE1bSW+rdeyh85/lt11uLH0f0B0\n\tr7dcFJhO3f1apR64ewGUy8rqDM4mITdXo6PU4RUC8ZWUhcXDFot+jlImjeZfXsD4qkNk\n\t2ZrybETZJS0pwObGG9OTnSAt5PWyz3J7GHw7QMrTiaP8YBY3Tnu3ngVC4KXFVFqJVSuZ\n\tOphVt0taulbsuA/f6gmrt1/2alYQ6eWMITF4ILAQHw/yUoBCYvylAcml5nPwlC9KCP9y\n\t6Q== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:43 +0530", "Message-ID": "<20190628075024.404-5-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 04/44] event/octeontx2: add device configure\n\tfunction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd the device configure function that attaches the requested number of\nSSO GWS(event ports) and GGRP(event queues) LF's to the PF.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 258 +++++++++++++++++++++++++++\n drivers/event/octeontx2/otx2_evdev.h | 10 ++\n 2 files changed, 268 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 839a5ccaa..00996578a 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -37,9 +37,267 @@ otx2_sso_info_get(struct rte_eventdev *event_dev,\n \t\t\t\t\tRTE_EVENT_DEV_CAP_NONSEQ_MODE;\n }\n \n+static int\n+sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,\n+\t uint16_t nb_lf, uint8_t attach)\n+{\n+\tif (attach) {\n+\t\tstruct rsrc_attach_req *req;\n+\n+\t\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n+\t\tswitch (type) {\n+\t\tcase SSO_LF_GGRP:\n+\t\t\treq->sso = nb_lf;\n+\t\t\tbreak;\n+\t\tcase SSO_LF_GWS:\n+\t\t\treq->ssow = nb_lf;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\treq->modify = true;\n+\t\tif (otx2_mbox_process(mbox) < 0)\n+\t\t\treturn -EIO;\n+\t} else {\n+\t\tstruct rsrc_detach_req *req;\n+\n+\t\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n+\t\tswitch (type) {\n+\t\tcase SSO_LF_GGRP:\n+\t\t\treq->sso = true;\n+\t\t\tbreak;\n+\t\tcase SSO_LF_GWS:\n+\t\t\treq->ssow = true;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\treq->partial = true;\n+\t\tif (otx2_mbox_process(mbox) < 0)\n+\t\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,\n+\t enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)\n+{\n+\tvoid *rsp;\n+\tint rc;\n+\n+\tif (alloc) {\n+\t\tswitch (type) {\n+\t\tcase SSO_LF_GGRP:\n+\t\t\t{\n+\t\t\tstruct sso_lf_alloc_req *req_ggrp;\n+\t\t\treq_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);\n+\t\t\treq_ggrp->hwgrps = nb_lf;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase SSO_LF_GWS:\n+\t\t\t{\n+\t\t\tstruct ssow_lf_alloc_req *req_hws;\n+\t\t\treq_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);\n+\t\t\treq_hws->hws = nb_lf;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\tswitch (type) {\n+\t\tcase SSO_LF_GGRP:\n+\t\t\t{\n+\t\t\tstruct sso_lf_free_req *req_ggrp;\n+\t\t\treq_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);\n+\t\t\treq_ggrp->hwgrps = nb_lf;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase SSO_LF_GWS:\n+\t\t\t{\n+\t\t\tstruct ssow_lf_free_req *req_hws;\n+\t\t\treq_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);\n+\t\t\treq_hws->hws = nb_lf;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\trc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tif (alloc && type == SSO_LF_GGRP) {\n+\t\tstruct sso_lf_alloc_rsp *rsp_ggrp = rsp;\n+\n+\t\tdev->xaq_buf_size = rsp_ggrp->xaq_buf_size;\n+\t\tdev->xae_waes = rsp_ggrp->xaq_wq_entries;\n+\t\tdev->iue = rsp_ggrp->in_unit_entries;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+sso_configure_ports(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint8_t nb_lf;\n+\tint rc;\n+\n+\totx2_sso_dbg(\"Configuring event ports %d\", dev->nb_event_ports);\n+\n+\tnb_lf = dev->nb_event_ports;\n+\t/* Ask AF to attach required LFs. */\n+\trc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to attach SSO GWS LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {\n+\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n+\t\totx2_err(\"Failed to init SSO GWS LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int\n+sso_configure_queues(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint8_t nb_lf;\n+\tint rc;\n+\n+\totx2_sso_dbg(\"Configuring event queues %d\", dev->nb_event_queues);\n+\n+\tnb_lf = dev->nb_event_queues;\n+\t/* Ask AF to attach required LFs. */\n+\trc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to attach SSO GGRP LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {\n+\t\tsso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);\n+\t\totx2_err(\"Failed to init SSO GGRP LF\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static void\n+sso_lf_teardown(struct otx2_sso_evdev *dev,\n+\t\tenum otx2_sso_lf_type lf_type)\n+{\n+\tuint8_t nb_lf;\n+\n+\tswitch (lf_type) {\n+\tcase SSO_LF_GGRP:\n+\t\tnb_lf = dev->nb_event_queues;\n+\t\tbreak;\n+\tcase SSO_LF_GWS:\n+\t\tnb_lf = dev->nb_event_ports;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tsso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);\n+\tsso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);\n+}\n+\n+static int\n+otx2_sso_configure(const struct rte_eventdev *event_dev)\n+{\n+\tstruct rte_event_dev_config *conf = &event_dev->data->dev_conf;\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuint32_t deq_tmo_ns;\n+\tint rc;\n+\n+\tsso_func_trace();\n+\tdeq_tmo_ns = conf->dequeue_timeout_ns;\n+\n+\tif (deq_tmo_ns == 0)\n+\t\tdeq_tmo_ns = dev->min_dequeue_timeout_ns;\n+\n+\tif (deq_tmo_ns < dev->min_dequeue_timeout_ns ||\n+\t deq_tmo_ns > dev->max_dequeue_timeout_ns) {\n+\t\totx2_err(\"Unsupported dequeue timeout requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)\n+\t\tdev->is_timeout_deq = 1;\n+\n+\tdev->deq_tmo_ns = deq_tmo_ns;\n+\n+\tif (conf->nb_event_ports > dev->max_event_ports ||\n+\t conf->nb_event_queues > dev->max_event_queues) {\n+\t\totx2_err(\"Unsupported event queues/ports requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->nb_event_port_dequeue_depth > 1) {\n+\t\totx2_err(\"Unsupported event port deq depth requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->nb_event_port_enqueue_depth > 1) {\n+\t\totx2_err(\"Unsupported event port enq depth requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (dev->nb_event_queues) {\n+\t\t/* Finit any previous queues. */\n+\t\tsso_lf_teardown(dev, SSO_LF_GGRP);\n+\t}\n+\tif (dev->nb_event_ports) {\n+\t\t/* Finit any previous ports. */\n+\t\tsso_lf_teardown(dev, SSO_LF_GWS);\n+\t}\n+\n+\tdev->nb_event_queues = conf->nb_event_queues;\n+\tdev->nb_event_ports = conf->nb_event_ports;\n+\n+\tif (sso_configure_ports(event_dev)) {\n+\t\totx2_err(\"Failed to configure event ports\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (sso_configure_queues(event_dev) < 0) {\n+\t\totx2_err(\"Failed to configure event queues\");\n+\t\trc = -ENODEV;\n+\t\tgoto teardown_hws;\n+\t}\n+\n+\tdev->configured = 1;\n+\trte_mb();\n+\n+\treturn 0;\n+\n+teardown_hws:\n+\tsso_lf_teardown(dev, SSO_LF_GWS);\n+\tdev->nb_event_queues = 0;\n+\tdev->nb_event_ports = 0;\n+\tdev->configured = 0;\n+\treturn rc;\n+}\n+\n /* Initialize and register event driver with DPDK Application */\n static struct rte_eventdev_ops otx2_sso_ops = {\n \t.dev_infos_get = otx2_sso_info_get,\n+\t.dev_configure = otx2_sso_configure,\n };\n \n static int\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 4427efcad..feb4ed6f4 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -20,6 +20,11 @@\n \n #define USEC2NSEC(__us) ((__us) * 1E3)\n \n+enum otx2_sso_lf_type {\n+\tSSO_LF_GGRP,\n+\tSSO_LF_GWS\n+};\n+\n struct otx2_sso_evdev {\n \tOTX2_DEV; /* Base class */\n \tuint8_t max_event_queues;\n@@ -27,10 +32,15 @@ struct otx2_sso_evdev {\n \tuint8_t is_timeout_deq;\n \tuint8_t nb_event_queues;\n \tuint8_t nb_event_ports;\n+\tuint8_t configured;\n \tuint32_t deq_tmo_ns;\n \tuint32_t min_dequeue_timeout_ns;\n \tuint32_t max_dequeue_timeout_ns;\n \tint32_t max_num_events;\n+\t/* HW const */\n+\tuint32_t xae_waes;\n+\tuint32_t xaq_buf_size;\n+\tuint32_t iue;\n } __rte_cache_aligned;\n \n static inline struct otx2_sso_evdev *\n", "prefixes": [ "v2", "04/44" ] }