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GET /api/patches/55539/?format=api
http://patches.dpdk.org/api/patches/55539/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-6-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628075024.404-6-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628075024.404-6-pbhagavatula@marvell.com", "date": "2019-06-28T07:49:44", "name": "[v2,05/44] event/octeontx2: add event queue config functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d7a9eee184d7dc0359d9508f4221b5ed767f38e7", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628075024.404-6-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5217, "url": "http://patches.dpdk.org/api/series/5217/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5217", "date": "2019-06-28T07:49:39", "name": "OCTEONTX2 event device driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5217/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55539/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55539/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 15C671B99C;\n\tFri, 28 Jun 2019 09:50:43 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DFAAB4CA9\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 09:50:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5S7ocJ8025655 for <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:40 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6gx-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 00:50:40 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 00:50:38 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 00:50:38 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255])\n\tby maili.marvell.com (Postfix) with ESMTP id 1A10F3F7041;\n\tFri, 28 Jun 2019 00:50:36 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=du1sAyKweZ7041tayY4hxO01V8utLvVR0D5QGBbEgTs=;\n\tb=Fhm/gMo7IzQ+aMz73wzKntgtQELu5Chg8gyWVZsc7zCRbmRyNXwMr6ESpB7dUXawnfJO\n\t6mEwUEVVJD4IWNjDaHUphQI8CzrUbZ9eDCbWOfjql++XnpL/knA4XScUfXqJ+OYH6xKz\n\tLY6g8Tg8yDdtxmrHaO+go5xhG2GljoWGh0mkR4VtoPceLl2o/qfGOKd7HPGsCdFrGX3P\n\tN2POcknZGshDXhjC+Mqh3nWiVP6CUax4nkHlbO1d0nslPT7LwwCkYDwbMs0rQPgySGgX\n\t7QwVHAp/GmEtrAC74yhcr+AoV/bFH/GUM0AoqzxFRnaYvVrtfjYMDlJaW7dlimPu+Kpx\n\tKw== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>", "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Fri, 28 Jun 2019 13:19:44 +0530", "Message-ID": "<20190628075024.404-6-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628075024.404-1-pbhagavatula@marvell.com>", "References": "<20190628075024.404-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 05/44] event/octeontx2: add event queue config\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd default config, setup and release functions for event queues i.e.\nSSO GGRPS.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 50 ++++++++++++++++++++++++++++\n drivers/event/octeontx2/otx2_evdev.h | 17 ++++++++++\n 2 files changed, 67 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 00996578a..2290598d0 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -142,6 +142,13 @@ sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,\n \treturn 0;\n }\n \n+static void\n+otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n+{\n+\tRTE_SET_USED(event_dev);\n+\tRTE_SET_USED(queue_id);\n+}\n+\n static int\n sso_configure_ports(const struct rte_eventdev *event_dev)\n {\n@@ -294,10 +301,53 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \treturn rc;\n }\n \n+static void\n+otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,\n+\t\t\tstruct rte_event_queue_conf *queue_conf)\n+{\n+\tRTE_SET_USED(event_dev);\n+\tRTE_SET_USED(queue_id);\n+\n+\tqueue_conf->nb_atomic_flows = (1ULL << 20);\n+\tqueue_conf->nb_atomic_order_sequences = (1ULL << 20);\n+\tqueue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n+\tqueue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;\n+}\n+\n+static int\n+otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,\n+\t\t const struct rte_event_queue_conf *queue_conf)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct sso_grp_priority *req;\n+\tint rc;\n+\n+\tsso_func_trace(\"Queue=%d prio=%d\", queue_id, queue_conf->priority);\n+\n+\treq = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);\n+\treq->grp = queue_id;\n+\treq->weight = 0xFF;\n+\treq->affinity = 0xFF;\n+\t/* Normalize <0-255> to <0-7> */\n+\treq->priority = queue_conf->priority / 32;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to set priority queue=%d\", queue_id);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Initialize and register event driver with DPDK Application */\n static struct rte_eventdev_ops otx2_sso_ops = {\n \t.dev_infos_get = otx2_sso_info_get,\n \t.dev_configure = otx2_sso_configure,\n+\t.queue_def_conf = otx2_sso_queue_def_conf,\n+\t.queue_setup = otx2_sso_queue_setup,\n+\t.queue_release = otx2_sso_queue_release,\n };\n \n static int\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex feb4ed6f4..b46402771 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -18,6 +18,23 @@\n #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV\n #define OTX2_SSO_MAX_VHWS (UINT8_MAX)\n \n+/* SSO LF register offsets (BAR2) */\n+#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)\n+#define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)\n+\n+#define SSO_LF_GGRP_QCTL (0x20ull)\n+#define SSO_LF_GGRP_EXE_DIS (0x80ull)\n+#define SSO_LF_GGRP_INT (0x100ull)\n+#define SSO_LF_GGRP_INT_W1S (0x108ull)\n+#define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)\n+#define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)\n+#define SSO_LF_GGRP_INT_THR (0x140ull)\n+#define SSO_LF_GGRP_INT_CNT (0x180ull)\n+#define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)\n+#define SSO_LF_GGRP_AQ_CNT (0x1c0ull)\n+#define SSO_LF_GGRP_AQ_THR (0x1e0ull)\n+#define SSO_LF_GGRP_MISC_CNT (0x200ull)\n+\n #define USEC2NSEC(__us) ((__us) * 1E3)\n \n enum otx2_sso_lf_type {\n", "prefixes": [ "v2", "05/44" ] }{ "id": 55539, "url": "