Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/55448/?format=api
{ "id": 55448, "url": "http://patches.dpdk.org/api/patches/55448/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/ca4e21cc72295dcb76771f525cff4585018edfcb.1561620219.git.xuanziyang2@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<ca4e21cc72295dcb76771f525cff4585018edfcb.1561620219.git.xuanziyang2@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/ca4e21cc72295dcb76771f525cff4585018edfcb.1561620219.git.xuanziyang2@huawei.com", "date": "2019-06-27T08:17:45", "name": "[v6,10/15] net/hinic/base: add various headers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "12a61dfc59d20578d45db2223011f4d4093e90c7", "submitter": { "id": 1321, "url": "http://patches.dpdk.org/api/people/1321/?format=api", "name": "Ziyang Xuan", "email": "xuanziyang2@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/ca4e21cc72295dcb76771f525cff4585018edfcb.1561620219.git.xuanziyang2@huawei.com/mbox/", "series": [ { "id": 5191, "url": "http://patches.dpdk.org/api/series/5191/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5191", "date": "2019-06-27T08:10:12", "name": "A new net PMD - hinic", "version": 6, "mbox": "http://patches.dpdk.org/series/5191/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55448/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55448/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EDFF72BEA;\n\tThu, 27 Jun 2019 10:06:03 +0200 (CEST)", "from huawei.com (szxga04-in.huawei.com [45.249.212.190])\n\tby dpdk.org (Postfix) with ESMTP id 17AA925D9\n\tfor <dev@dpdk.org>; Thu, 27 Jun 2019 10:06:02 +0200 (CEST)", "from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id A370CCCE7E3612E92B28\n\tfor <dev@dpdk.org>; Thu, 27 Jun 2019 16:06:00 +0800 (CST)", "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP\n\tServer id 14.3.439.0; Thu, 27 Jun 2019 16:05:53 +0800" ], "From": "Ziyang Xuan <xuanziyang2@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<shahar.belkar@huawei.com>, <luoxianjun@huawei.com>,\n\t<tanya.brokhman@huawei.com>, Ziyang Xuan <xuanziyang2@huawei.com>", "Date": "Thu, 27 Jun 2019 16:17:45 +0800", "Message-ID": "<ca4e21cc72295dcb76771f525cff4585018edfcb.1561620219.git.xuanziyang2@huawei.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<cover.1561620219.git.xuanziyang2@huawei.com>", "References": "<cover.1561620219.git.xuanziyang2@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.175.119.39]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v6 10/15] net/hinic/base: add various headers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add various headers that define mgmt commands, cmdq commands\nand basic defines for use in the code.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/base/hinic_compat.h | 256 ++++++++++++++\n drivers/net/hinic/base/hinic_pmd_cmd.h | 453 +++++++++++++++++++++++++\n 2 files changed, 709 insertions(+)\n create mode 100644 drivers/net/hinic/base/hinic_compat.h\n create mode 100644 drivers/net/hinic/base/hinic_pmd_cmd.h", "diff": "diff --git a/drivers/net/hinic/base/hinic_compat.h b/drivers/net/hinic/base/hinic_compat.h\nnew file mode 100644\nindex 000000000..48643c8d2\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_compat.h\n@@ -0,0 +1,256 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_COMPAT_H_\n+#define _HINIC_COMPAT_H_\n+\n+#include <stdint.h>\n+#include <sys/time.h>\n+#include <rte_common.h>\n+#include <rte_byteorder.h>\n+#include <rte_memzone.h>\n+#include <rte_memcpy.h>\n+#include <rte_malloc.h>\n+#include <rte_atomic.h>\n+#include <rte_spinlock.h>\n+#include <rte_cycles.h>\n+#include <rte_log.h>\n+#include <rte_config.h>\n+\n+typedef uint8_t u8;\n+typedef int8_t s8;\n+typedef uint16_t u16;\n+typedef uint32_t u32;\n+typedef int32_t s32;\n+typedef uint64_t u64;\n+\n+#ifndef dma_addr_t\n+typedef uint64_t dma_addr_t;\n+#endif\n+\n+#ifndef gfp_t\n+#define gfp_t unsigned\n+#endif\n+\n+#ifndef bool\n+#define bool int\n+#endif\n+\n+#ifndef FALSE\n+#define FALSE\t(0)\n+#endif\n+\n+#ifndef TRUE\n+#define TRUE\t(1)\n+#endif\n+\n+#ifndef false\n+#define false\t(0)\n+#endif\n+\n+#ifndef true\n+#define true\t(1)\n+#endif\n+\n+#ifndef NULL\n+#define NULL ((void *)0)\n+#endif\n+\n+#define HINIC_ERROR\t(-1)\n+#define HINIC_OK\t(0)\n+\n+#ifndef BIT\n+#define BIT(n) (1 << (n))\n+#endif\n+\n+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n+#define lower_32_bits(n) ((u32)(n))\n+\n+/* Returns X / Y, rounding up. X must be nonnegative to round correctly. */\n+#define DIV_ROUND_UP(X, Y) (((X) + ((Y) - 1)) / (Y))\n+\n+/* Returns X rounded up to the nearest multiple of Y. */\n+#define ROUND_UP(X, Y) (DIV_ROUND_UP(X, Y) * (Y))\n+\n+#undef ALIGN\n+#define ALIGN(x, a) RTE_ALIGN(x, a)\n+\n+#define PTR_ALIGN(p, a)\t\t((typeof(p))ALIGN((unsigned long)(p), (a)))\n+\n+/* Reported driver name. */\n+#define HINIC_DRIVER_NAME \"net_hinic\"\n+\n+extern int hinic_logtype;\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, hinic_logtype, \\\n+\t\tHINIC_DRIVER_NAME\": \" fmt \"\\n\", ##args)\n+\n+/* common definition */\n+#ifndef ETH_ALEN\n+#define ETH_ALEN\t\t6\n+#endif\n+#define ETH_HLEN\t\t14\n+#define ETH_CRC_LEN\t\t4\n+#define VLAN_PRIO_SHIFT\t\t13\n+#define VLAN_N_VID\t\t4096\n+\n+/* bit order interface */\n+#define cpu_to_be16(o) rte_cpu_to_be_16(o)\n+#define cpu_to_be32(o) rte_cpu_to_be_32(o)\n+#define cpu_to_be64(o) rte_cpu_to_be_64(o)\n+#define cpu_to_le32(o) rte_cpu_to_le_32(o)\n+#define be16_to_cpu(o) rte_be_to_cpu_16(o)\n+#define be32_to_cpu(o) rte_be_to_cpu_32(o)\n+#define be64_to_cpu(o) rte_be_to_cpu_64(o)\n+#define le32_to_cpu(o) rte_le_to_cpu_32(o)\n+\n+/* virt memory and dma phy memory */\n+#define __iomem\n+#define GFP_KERNEL\t\tRTE_MEMZONE_IOVA_CONTIG\n+#define HINIC_PAGE_SHIFT\t12\n+#define HINIC_PAGE_SIZE\t\tRTE_PGSIZE_4K\n+#define HINIC_MEM_ALLOC_ALIGNE_MIN\t8\n+\n+#define HINIC_PAGE_SIZE_DPDK\t6\n+\n+static inline int hinic_test_bit(int nr, volatile unsigned long *addr)\n+{\n+\tint res;\n+\n+\trte_mb();\n+\tres = ((*addr) & (1UL << nr)) != 0;\n+\trte_mb();\n+\treturn res;\n+}\n+\n+static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_or(addr, (1UL << nr));\n+}\n+\n+static inline void hinic_clear_bit(int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_and(addr, ~(1UL << nr));\n+}\n+\n+static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr)\n+{\n+\tunsigned long mask = (1UL << nr);\n+\n+\treturn __sync_fetch_and_and(addr, ~mask) & mask;\n+}\n+\n+static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr)\n+{\n+\tunsigned long mask = (1UL << nr);\n+\n+\treturn __sync_fetch_and_or(addr, mask) & mask;\n+}\n+\n+void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle,\n+\t\t\t gfp_t flag);\n+void *dma_zalloc_coherent_aligned(void *dev, size_t size,\n+\t\t\t\tdma_addr_t *dma_handle, gfp_t flag);\n+void *dma_zalloc_coherent_aligned256k(void *dev, size_t size,\n+\t\t\t\tdma_addr_t *dma_handle, gfp_t flag);\n+void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys);\n+\n+/* dma pool alloc and free */\n+#define\tpci_pool dma_pool\n+#define\tpci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)\n+#define\tpci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)\n+\n+struct dma_pool *dma_pool_create(const char *name, void *dev, size_t size,\n+\t\t\t\tsize_t align, size_t boundary);\n+void dma_pool_destroy(struct dma_pool *pool);\n+void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr);\n+void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma);\n+\n+#define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGNE_MIN)\n+#define kzalloc_aligned(size, flag) rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE)\n+#define kfree(ptr) rte_free(ptr)\n+\n+/* mmio interface */\n+static inline void writel(u32 value, volatile void *addr)\n+{\n+\t*(volatile u32 *)addr = value;\n+}\n+\n+static inline u32 readl(const volatile void *addr)\n+{\n+\treturn *(const volatile u32 *)addr;\n+}\n+\n+#define __raw_writel(value, reg) writel((value), (reg))\n+#define __raw_readl(reg) readl((reg))\n+\n+/* Spinlock related interface */\n+#define hinic_spinlock_t rte_spinlock_t\n+\n+#define spinlock_t rte_spinlock_t\n+#define spin_lock_init(spinlock_prt)\trte_spinlock_init(spinlock_prt)\n+#define spin_lock_deinit(lock)\n+#define spin_lock(spinlock_prt)\t\trte_spinlock_lock(spinlock_prt)\n+#define spin_unlock(spinlock_prt)\trte_spinlock_unlock(spinlock_prt)\n+\n+static inline unsigned long get_timeofday_ms(void)\n+{\n+\tstruct timeval tv;\n+\n+\t(void)gettimeofday(&tv, NULL);\n+\n+\treturn (unsigned long)tv.tv_sec * 1000 + tv.tv_usec / 1000;\n+}\n+\n+#define jiffies\tget_timeofday_ms()\n+#define msecs_to_jiffies(ms)\t(ms)\n+#define time_before(now, end)\t((now) < (end))\n+\n+/* misc kernel utils */\n+static inline u16 ilog2(u32 n)\n+{\n+\tu16 res = 0;\n+\n+\twhile (n > 1) {\n+\t\tn >>= 1;\n+\t\tres++;\n+\t}\n+\n+\treturn res;\n+}\n+\n+/**\n+ * hinic_cpu_to_be32 - convert data to big endian 32 bit format\n+ * @data: the data to convert\n+ * @len: length of data to convert, must be Multiple of 4B\n+ **/\n+static inline void hinic_cpu_to_be32(void *data, u32 len)\n+{\n+\tu32 i;\n+\tu32 *mem = (u32 *)data;\n+\n+\tfor (i = 0; i < (len >> 2); i++) {\n+\t\t*mem = cpu_to_be32(*mem);\n+\t\tmem++;\n+\t}\n+}\n+\n+/**\n+ * hinic_be32_to_cpu - convert data from big endian 32 bit format\n+ * @data: the data to convert\n+ * @len: length of data to convert, must be Multiple of 4B\n+ **/\n+static inline void hinic_be32_to_cpu(void *data, u32 len)\n+{\n+\tu32 i;\n+\tu32 *mem = (u32 *)data;\n+\n+\tfor (i = 0; i < (len >> 2); i++) {\n+\t\t*mem = be32_to_cpu(*mem);\n+\t\tmem++;\n+\t}\n+}\n+\n+#endif /* _HINIC_COMPAT_H_ */\ndiff --git a/drivers/net/hinic/base/hinic_pmd_cmd.h b/drivers/net/hinic/base/hinic_pmd_cmd.h\nnew file mode 100644\nindex 000000000..7a9e9f636\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_pmd_cmd.h\n@@ -0,0 +1,453 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PORT_CMD_H_\n+#define _HINIC_PORT_CMD_H_\n+\n+enum hinic_eq_type {\n+\tHINIC_AEQ,\n+\tHINIC_CEQ\n+};\n+\n+enum hinic_resp_aeq_num {\n+\tHINIC_AEQ0 = 0,\n+\tHINIC_AEQ1 = 1,\n+\tHINIC_AEQ2 = 2,\n+\tHINIC_AEQ3 = 3,\n+};\n+\n+enum hinic_mod_type {\n+\tHINIC_MOD_COMM = 0,\t/* HW communication module */\n+\tHINIC_MOD_L2NIC = 1,\t/* L2NIC module */\n+\tHINIC_MOD_CFGM = 7,\t/* Configuration module */\n+\tHINIC_MOD_HILINK = 14,\n+\tHINIC_MOD_MAX\t= 15\n+};\n+\n+/* cmd of mgmt CPU message for NIC module */\n+enum hinic_port_cmd {\n+\tHINIC_PORT_CMD_MGMT_RESET\t\t= 0x0,\n+\n+\tHINIC_PORT_CMD_CHANGE_MTU\t\t= 0x2,\n+\n+\tHINIC_PORT_CMD_ADD_VLAN\t\t\t= 0x3,\n+\tHINIC_PORT_CMD_DEL_VLAN,\n+\n+\tHINIC_PORT_CMD_SET_ETS\t\t\t= 0x7,\n+\tHINIC_PORT_CMD_GET_ETS,\n+\n+\tHINIC_PORT_CMD_SET_MAC\t\t\t= 0x9,\n+\tHINIC_PORT_CMD_GET_MAC,\n+\tHINIC_PORT_CMD_DEL_MAC,\n+\n+\tHINIC_PORT_CMD_SET_RX_MODE\t\t= 0xc,\n+\tHINIC_PORT_CMD_SET_ANTI_ATTACK_RATE\t= 0xd,\n+\n+\tHINIC_PORT_CMD_GET_PAUSE_INFO\t\t= 0x14,\n+\tHINIC_PORT_CMD_SET_PAUSE_INFO,\n+\n+\tHINIC_PORT_CMD_GET_LINK_STATE\t\t= 0x18,\n+\tHINIC_PORT_CMD_SET_LRO\t\t\t= 0x19,\n+\tHINIC_PORT_CMD_SET_RX_CSUM\t\t= 0x1a,\n+\tHINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD\t= 0x1b,\n+\n+\tHINIC_PORT_CMD_GET_PORT_STATISTICS\t= 0x1c,\n+\tHINIC_PORT_CMD_CLEAR_PORT_STATISTICS,\n+\tHINIC_PORT_CMD_GET_VPORT_STAT,\n+\tHINIC_PORT_CMD_CLEAN_VPORT_STAT,\n+\n+\tHINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,\n+\tHINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,\n+\n+\tHINIC_PORT_CMD_SET_PORT_ENABLE\t\t= 0x29,\n+\tHINIC_PORT_CMD_GET_PORT_ENABLE,\n+\n+\tHINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL\t= 0x2b,\n+\tHINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,\n+\tHINIC_PORT_CMD_SET_RSS_HASH_ENGINE,\n+\tHINIC_PORT_CMD_GET_RSS_HASH_ENGINE,\n+\tHINIC_PORT_CMD_GET_RSS_CTX_TBL,\n+\tHINIC_PORT_CMD_SET_RSS_CTX_TBL,\n+\tHINIC_PORT_CMD_RSS_TEMP_MGR,\n+\n+\tHINIC_PORT_CMD_RSS_CFG\t\t\t= 0x42,\n+\n+\tHINIC_PORT_CMD_GET_PHY_TYPE\t\t= 0x44,\n+\tHINIC_PORT_CMD_INIT_FUNC\t\t= 0x45,\n+\n+\tHINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE\t= 0x4a,\n+\tHINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,\n+\n+\tHINIC_PORT_CMD_GET_PORT_TYPE\t\t= 0x5b,\n+\n+\tHINIC_PORT_CMD_GET_VPORT_ENABLE\t\t= 0x5c,\n+\tHINIC_PORT_CMD_SET_VPORT_ENABLE,\n+\n+\tHINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID\t= 0x5e,\n+\n+\tHINIC_PORT_CMD_GET_LRO\t\t\t= 0x63,\n+\n+\tHINIC_PORT_CMD_GET_DMA_CS\t\t= 0x64,\n+\tHINIC_PORT_CMD_SET_DMA_CS,\n+\n+\tHINIC_PORT_CMD_GET_GLOBAL_QPN\t\t= 0x66,\n+\n+\tHINIC_PORT_CMD_SET_PFC_MISC\t\t= 0x67,\n+\tHINIC_PORT_CMD_GET_PFC_MISC,\n+\n+\tHINIC_PORT_CMD_SET_VF_RATE\t\t= 0x69,\n+\tHINIC_PORT_CMD_SET_VF_VLAN,\n+\tHINIC_PORT_CMD_CLR_VF_VLAN,\n+\n+\tHINIC_PORT_CMD_SET_RQ_IQ_MAP\t\t= 0x73,\n+\tHINIC_PORT_CMD_SET_PFC_THD\t\t= 0x75,\n+\n+\tHINIC_PORT_CMD_LINK_STATUS_REPORT\t= 0xa0,\n+\n+\tHINIC_PORT_CMD_SET_LOSSLESS_ETH\t\t= 0xa3,\n+\tHINIC_PORT_CMD_UPDATE_MAC\t\t= 0xa4,\n+\n+\tHINIC_PORT_CMD_GET_PORT_INFO\t\t= 0xaa,\n+\n+\tHINIC_PORT_CMD_SET_IPSU_MAC\t\t= 0xcb,\n+\tHINIC_PORT_CMD_GET_IPSU_MAC\t\t= 0xcc,\n+\n+\tHINIC_PORT_CMD_GET_LINK_MODE\t\t= 0xD9,\n+\tHINIC_PORT_CMD_SET_SPEED\t\t= 0xDA,\n+\tHINIC_PORT_CMD_SET_AUTONEG\t\t= 0xDB,\n+\n+\tHINIC_PORT_CMD_CLEAR_QP_RES\t\t= 0xDD,\n+\tHINIC_PORT_CMD_SET_SUPER_CQE\t\t= 0xDE,\n+\tHINIC_PORT_CMD_SET_VF_COS\t\t= 0xDF,\n+\tHINIC_PORT_CMD_GET_VF_COS\t\t= 0xE1,\n+\n+\tHINIC_PORT_CMD_CABLE_PLUG_EVENT\t\t= 0xE5,\n+\tHINIC_PORT_CMD_LINK_ERR_EVENT\t\t= 0xE6,\n+\n+\tHINIC_PORT_CMD_SET_COS_UP_MAP\t\t= 0xE8,\n+\n+\tHINIC_PORT_CMD_RESET_LINK_CFG\t\t= 0xEB,\n+\n+\tHINIC_PORT_CMD_FORCE_PKT_DROP\t\t= 0xF3,\n+\tHINIC_PORT_CMD_SET_LRO_TIMER\t\t= 0xF4,\n+\n+\tHINIC_PORT_CMD_SET_VHD_CFG\t\t= 0xF7,\n+\tHINIC_PORT_CMD_SET_LINK_FOLLOW\t\t= 0xF8,\n+};\n+\n+/* cmd of mgmt CPU message for HW module */\n+enum hinic_mgmt_cmd {\n+\tHINIC_MGMT_CMD_RESET_MGMT\t\t= 0x0,\n+\tHINIC_MGMT_CMD_START_FLR\t\t= 0x1,\n+\tHINIC_MGMT_CMD_FLUSH_DOORBELL\t\t= 0x2,\n+\tHINIC_MGMT_CMD_GET_IO_STATUS\t\t= 0x3,\n+\tHINIC_MGMT_CMD_DMA_ATTR_SET\t\t= 0x4,\n+\n+\tHINIC_MGMT_CMD_CMDQ_CTXT_SET\t\t= 0x10,\n+\tHINIC_MGMT_CMD_CMDQ_CTXT_GET,\n+\n+\tHINIC_MGMT_CMD_VAT_SET\t\t\t= 0x12,\n+\tHINIC_MGMT_CMD_VAT_GET,\n+\n+\tHINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET\t= 0x14,\n+\tHINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,\n+\n+\tHINIC_MGMT_CMD_PPF_HT_GPA_SET\t\t= 0x23,\n+\tHINIC_MGMT_CMD_RES_STATE_SET\t\t= 0x24,\n+\tHINIC_MGMT_CMD_FUNC_CACHE_OUT\t\t= 0x25,\n+\tHINIC_MGMT_CMD_FFM_SET\t\t\t= 0x26,\n+\n+\tHINIC_MGMT_CMD_FUNC_RES_CLEAR\t\t= 0x29,\n+\n+\tHINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP\t= 0x33,\n+\tHINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,\n+\tHINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,\n+\n+\tHINIC_MGMT_CMD_VF_RANDOM_ID_SET\t\t= 0x36,\n+\tHINIC_MGMT_CMD_FAULT_REPORT\t\t= 0x37,\n+\n+\tHINIC_MGMT_CMD_VPD_SET\t\t\t= 0x40,\n+\tHINIC_MGMT_CMD_VPD_GET,\n+\tHINIC_MGMT_CMD_LABEL_SET,\n+\tHINIC_MGMT_CMD_LABEL_GET,\n+\tHINIC_MGMT_CMD_SATIC_MAC_SET,\n+\tHINIC_MGMT_CMD_SATIC_MAC_GET,\n+\tHINIC_MGMT_CMD_SYNC_TIME\t\t= 0x46,\n+\tHINIC_MGMT_CMD_SET_LED_STATUS\t\t= 0x4A,\n+\tHINIC_MGMT_CMD_L2NIC_RESET\t\t= 0x4b,\n+\tHINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET\t= 0x4d,\n+\tHINIC_MGMT_CMD_BIOS_NV_DATA_MGMT\t= 0x4E,\n+\tHINIC_MGMT_CMD_ACTIVATE_FW\t\t= 0x4F,\n+\tHINIC_MGMT_CMD_PAGESIZE_SET\t\t= 0x50,\n+\tHINIC_MGMT_CMD_PAGESIZE_GET\t\t= 0x51,\n+\tHINIC_MGMT_CMD_GET_BOARD_INFO\t\t= 0x52,\n+\tHINIC_MGMT_CMD_WATCHDOG_INFO\t\t= 0x56,\n+\tHINIC_MGMT_CMD_FMW_ACT_NTC\t\t= 0x57,\n+\tHINIC_MGMT_CMD_SET_VF_RANDOM_ID\t\t= 0x61,\n+\tHINIC_MGMT_CMD_GET_PPF_STATE\t\t= 0x63,\n+\tHINIC_MGMT_CMD_PCIE_DFX_NTC\t\t= 0x65,\n+\tHINIC_MGMT_CMD_PCIE_DFX_GET\t\t= 0x66,\n+};\n+\n+/* cmd of mgmt CPU message for HILINK module */\n+enum hinic_hilink_cmd {\n+\tHINIC_HILINK_CMD_GET_LINK_INFO\t\t= 0x3,\n+\tHINIC_HILINK_CMD_SET_LINK_SETTINGS\t= 0x8,\n+};\n+\n+/* uCode related commands */\n+enum hinic_ucode_cmd {\n+\tHINIC_UCODE_CMD_MDY_QUEUE_CONTEXT\t= 0,\n+\tHINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,\n+\tHINIC_UCODE_CMD_ARM_SQ,\n+\tHINIC_UCODE_CMD_ARM_RQ,\n+\tHINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,\n+\tHINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,\n+\tHINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,\n+\tHINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,\n+\tHINIC_UCODE_CMD_SET_IQ_ENABLE,\n+\tHINIC_UCODE_CMD_SET_RQ_FLUSH\t\t= 10\n+};\n+\n+enum cfg_sub_cmd {\n+\t/* PPF(PF) <-> FW */\n+\tHINIC_CFG_NIC_CAP = 0,\n+\tCFG_FW_VERSION,\n+\tCFG_UCODE_VERSION,\n+\tHINIC_CFG_MBOX_CAP = 6\n+};\n+\n+enum hinic_ack_type {\n+\tHINIC_ACK_TYPE_CMDQ,\n+\tHINIC_ACK_TYPE_SHARE_CQN,\n+\tHINIC_ACK_TYPE_APP_CQN,\n+\n+\tHINIC_MOD_ACK_MAX = 15,\n+};\n+\n+enum sq_l4offload_type {\n+\tOFFLOAD_DISABLE = 0,\n+\tTCP_OFFLOAD_ENABLE = 1,\n+\tSCTP_OFFLOAD_ENABLE = 2,\n+\tUDP_OFFLOAD_ENABLE = 3,\n+};\n+\n+enum sq_vlan_offload_flag {\n+\tVLAN_OFFLOAD_DISABLE = 0,\n+\tVLAN_OFFLOAD_ENABLE = 1,\n+};\n+\n+enum sq_pkt_parsed_flag {\n+\tPKT_NOT_PARSED = 0,\n+\tPKT_PARSED = 1,\n+};\n+\n+enum sq_l3_type {\n+\tUNKNOWN_L3TYPE = 0,\n+\tIPV6_PKT = 1,\n+\tIPV4_PKT_NO_CHKSUM_OFFLOAD = 2,\n+\tIPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,\n+};\n+\n+enum sq_md_type {\n+\tUNKNOWN_MD_TYPE = 0,\n+};\n+\n+enum sq_l2type {\n+\tETHERNET = 0,\n+};\n+\n+enum sq_tunnel_l4_type {\n+\tNOT_TUNNEL,\n+\tTUNNEL_UDP_NO_CSUM,\n+\tTUNNEL_UDP_CSUM,\n+};\n+\n+#define NIC_RSS_CMD_TEMP_ALLOC 0x01\n+#define NIC_RSS_CMD_TEMP_FREE 0x02\n+\n+#define HINIC_RSS_TYPE_VALID_SHIFT\t\t\t23\n+#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT\t\t24\n+#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT\t\t\t25\n+#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT\t\t\t26\n+#define HINIC_RSS_TYPE_IPV6_SHIFT\t\t\t27\n+#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT\t\t\t28\n+#define HINIC_RSS_TYPE_IPV4_SHIFT\t\t\t29\n+#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT\t\t\t30\n+#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT\t\t\t31\n+\n+#define HINIC_RSS_TYPE_SET(val, member)\t\t\\\n+\t\t(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)\n+\n+#define HINIC_RSS_TYPE_GET(val, member)\t\t\\\n+\t\t(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)\n+\n+enum hinic_speed {\n+\tHINIC_SPEED_10MB_LINK = 0,\n+\tHINIC_SPEED_100MB_LINK,\n+\tHINIC_SPEED_1000MB_LINK,\n+\tHINIC_SPEED_10GB_LINK,\n+\tHINIC_SPEED_25GB_LINK,\n+\tHINIC_SPEED_40GB_LINK,\n+\tHINIC_SPEED_100GB_LINK,\n+\tHINIC_SPEED_UNKNOWN = 0xFF,\n+};\n+\n+enum {\n+\tHINIC_IFLA_VF_LINK_STATE_AUTO,\t/* link state of the uplink */\n+\tHINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */\n+\tHINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */\n+};\n+\n+#define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT\t\t0\n+#define HINIC_AF0_P2P_IDX_SHIFT\t\t\t10\n+#define HINIC_AF0_PCI_INTF_IDX_SHIFT\t\t14\n+#define HINIC_AF0_VF_IN_PF_SHIFT\t\t16\n+#define HINIC_AF0_FUNC_TYPE_SHIFT\t\t24\n+\n+#define HINIC_AF0_FUNC_GLOBAL_IDX_MASK\t\t0x3FF\n+#define HINIC_AF0_P2P_IDX_MASK\t\t\t0xF\n+#define HINIC_AF0_PCI_INTF_IDX_MASK\t\t0x3\n+#define HINIC_AF0_VF_IN_PF_MASK\t\t\t0xFF\n+#define HINIC_AF0_FUNC_TYPE_MASK\t\t0x1\n+\n+#define HINIC_AF0_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)\n+\n+#define HINIC_AF1_PPF_IDX_SHIFT\t\t\t0\n+#define HINIC_AF1_AEQS_PER_FUNC_SHIFT\t\t8\n+#define HINIC_AF1_CEQS_PER_FUNC_SHIFT\t\t12\n+#define HINIC_AF1_IRQS_PER_FUNC_SHIFT\t\t20\n+#define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT\t24\n+#define HINIC_AF1_MGMT_INIT_STATUS_SHIFT\t30\n+#define HINIC_AF1_PF_INIT_STATUS_SHIFT\t\t31\n+\n+#define HINIC_AF1_PPF_IDX_MASK\t\t\t0x1F\n+#define HINIC_AF1_AEQS_PER_FUNC_MASK\t\t0x3\n+#define HINIC_AF1_CEQS_PER_FUNC_MASK\t\t0x7\n+#define HINIC_AF1_IRQS_PER_FUNC_MASK\t\t0xF\n+#define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK\t0x7\n+#define HINIC_AF1_MGMT_INIT_STATUS_MASK\t\t0x1\n+#define HINIC_AF1_PF_INIT_STATUS_MASK\t\t0x1\n+\n+#define HINIC_AF1_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)\n+\n+#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT\t16\n+#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK\t0x3FF\n+\n+#define HINIC_AF2_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)\n+\n+#define HINIC_AF4_OUTBOUND_CTRL_SHIFT\t\t0\n+#define HINIC_AF4_DOORBELL_CTRL_SHIFT\t\t1\n+#define HINIC_AF4_OUTBOUND_CTRL_MASK\t\t0x1\n+#define HINIC_AF4_DOORBELL_CTRL_MASK\t\t0x1\n+\n+#define HINIC_AF4_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)\n+\n+#define HINIC_AF4_SET(val, member)\t\t\t\t\\\n+\t(((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)\n+\n+#define HINIC_AF4_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(HINIC_AF4_##member##_MASK <<\t\t\\\n+\tHINIC_AF4_##member##_SHIFT)))\n+\n+#define HINIC_AF5_PF_STATUS_SHIFT\t\t0\n+#define HINIC_AF5_PF_STATUS_MASK\t\t0xFFFF\n+\n+#define HINIC_AF5_SET(val, member)\t\t\t\t\\\n+\t(((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)\n+\n+#define HINIC_AF5_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)\n+\n+#define HINIC_AF5_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(HINIC_AF5_##member##_MASK <<\t\t\\\n+\tHINIC_AF5_##member##_SHIFT)))\n+\n+#define HINIC_PPF_ELECTION_IDX_SHIFT\t\t0\n+\n+#define HINIC_PPF_ELECTION_IDX_MASK\t\t0x1F\n+\n+#define HINIC_PPF_ELECTION_SET(val, member)\t\t\t\\\n+\t(((val) & HINIC_PPF_ELECTION_##member##_MASK) <<\t\\\n+\t\tHINIC_PPF_ELECTION_##member##_SHIFT)\n+\n+#define HINIC_PPF_ELECTION_GET(val, member)\t\t\t\\\n+\t(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &\t\\\n+\t\tHINIC_PPF_ELECTION_##member##_MASK)\n+\n+#define HINIC_PPF_ELECTION_CLEAR(val, member)\t\t\t\\\n+\t((val) & (~(HINIC_PPF_ELECTION_##member##_MASK\t\\\n+\t\t<< HINIC_PPF_ELECTION_##member##_SHIFT)))\n+\n+#define DB_IDX(db, db_base)\t\\\n+\t((u32)(((unsigned long)(db) - (unsigned long)(db_base)) /\t\\\n+\tHINIC_DB_PAGE_SIZE))\n+\n+enum hinic_pcie_nosnoop {\n+\tHINIC_PCIE_SNOOP = 0,\n+\tHINIC_PCIE_NO_SNOOP = 1,\n+};\n+\n+enum hinic_pcie_tph {\n+\tHINIC_PCIE_TPH_DISABLE = 0,\n+\tHINIC_PCIE_TPH_ENABLE = 1,\n+};\n+\n+enum hinic_outbound_ctrl {\n+\tENABLE_OUTBOUND = 0x0,\n+\tDISABLE_OUTBOUND = 0x1,\n+};\n+\n+enum hinic_doorbell_ctrl {\n+\tENABLE_DOORBELL = 0x0,\n+\tDISABLE_DOORBELL = 0x1,\n+};\n+\n+enum hinic_pf_status {\n+\tHINIC_PF_STATUS_INIT = 0X0,\n+\tHINIC_PF_STATUS_ACTIVE_FLAG = 0x11,\n+\tHINIC_PF_STATUS_FLR_START_FLAG = 0x12,\n+\tHINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,\n+};\n+\n+/* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */\n+#define HINIC_DB_DWQE_SIZE 0x00080000\n+\n+/* db/dwqe page size: 4K */\n+#define HINIC_DB_PAGE_SIZE\t\t0x00001000ULL\n+\n+#define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)\n+\n+#define HINIC_PCI_MSIX_ENTRY_SIZE\t\t\t16\n+#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL\t\t12\n+#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT\t\t1\n+\n+struct hinic_mgmt_msg_head {\n+\tu8\tstatus;\n+\tu8\tversion;\n+\tu8\tresp_aeq_num;\n+\tu8\trsvd0[5];\n+};\n+\n+struct hinic_root_ctxt {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_idx;\n+\tu16\trsvd1;\n+\tu8\tset_cmdq_depth;\n+\tu8\tcmdq_depth;\n+\tu8\tlro_en;\n+\tu8\trsvd2;\n+\tu8\tppf_idx;\n+\tu8\trsvd3;\n+\tu16\trq_depth;\n+\tu16\trx_buf_sz;\n+\tu16\tsq_depth;\n+};\n+\n+#endif /* _HINIC_PORT_CMD_H_ */\n", "prefixes": [ "v6", "10/15" ] }