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Update a patch.

GET /api/patches/55350/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55350,
    "url": "http://patches.dpdk.org/api/patches/55350/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-27-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190625153217.24301-27-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190625153217.24301-27-jasvinder.singh@intel.com",
    "date": "2019-06-25T15:32:15",
    "name": "[v2,26/28] examples/ip_pipeline: update ip pipeline sample app",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "875db06d78c8f77b099dfd9e94910a2f262c157a",
    "submitter": {
        "id": 285,
        "url": "http://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "http://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-27-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 5160,
            "url": "http://patches.dpdk.org/api/series/5160/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5160",
            "date": "2019-06-25T15:31:49",
            "name": "sched: feature enhancements",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/5160/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55350/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55350/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DC7D91BC0B;\n\tTue, 25 Jun 2019 17:33:00 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id A7F471BB32\n\tfor <dev@dpdk.org>; Tue, 25 Jun 2019 17:32:38 +0200 (CEST)",
            "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jun 2019 08:32:38 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga006.jf.intel.com with ESMTP; 25 Jun 2019 08:32:36 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.63,416,1557212400\"; d=\"scan'208\";a=\"166711710\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com, Abraham Tovar <abrahamx.tovar@intel.com>, \n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>",
        "Date": "Tue, 25 Jun 2019 16:32:15 +0100",
        "Message-Id": "<20190625153217.24301-27-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "References": "<20190528120553.2992-2-lukaszx.krakowiak@intel.com>\n\t<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 26/28] examples/ip_pipeline: update ip\n\tpipeline sample app",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update ip pipeline sample app to allow configuration flexiblity\nfor pipe traffic classes and queues, and subport level configuration\nof the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n examples/ip_pipeline/cli.c             | 85 +++++++++++++-------------\n examples/ip_pipeline/tmgr.c            | 22 +++----\n examples/ip_pipeline/tmgr.h            |  3 -\n lib/librte_pipeline/rte_table_action.c |  1 -\n lib/librte_pipeline/rte_table_action.h |  4 +-\n 5 files changed, 54 insertions(+), 61 deletions(-)",
    "diff": "diff --git a/examples/ip_pipeline/cli.c b/examples/ip_pipeline/cli.c\nindex 309b2936e..1c19d0e21 100644\n--- a/examples/ip_pipeline/cli.c\n+++ b/examples/ip_pipeline/cli.c\n@@ -377,8 +377,11 @@ cmd_swq(char **tokens,\n static const char cmd_tmgr_subport_profile_help[] =\n \"tmgr subport profile\\n\"\n \"   <tb_rate> <tb_size>\\n\"\n-\"   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>\\n\"\n-\"   <tc_period>\\n\";\n+\"   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>\"\n+\"        <tc4_rate> <tc5_rate> <tc6_rate> <tc7_rate> <tc8_rate>\\n\"\n+\"   <tc_period>\\n\"\n+\"   pps <n_pipes_per_subport>\\n\"\n+\"   qsize <qsize_q0..15>\";\n \n static void\n cmd_tmgr_subport_profile(char **tokens,\n@@ -389,7 +392,7 @@ cmd_tmgr_subport_profile(char **tokens,\n \tstruct rte_sched_subport_params p;\n \tint status, i;\n \n-\tif (n_tokens != 10) {\n+\tif (n_tokens != 34) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -410,11 +413,32 @@ cmd_tmgr_subport_profile(char **tokens,\n \t\t\treturn;\n \t\t}\n \n-\tif (parser_read_uint32(&p.tc_period, tokens[9]) != 0) {\n+\tif (parser_read_uint32(&p.tc_period, tokens[14]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tc_period\");\n \t\treturn;\n \t}\n \n+\tif (strcmp(tokens[15], \"pps\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pps\");\n+\t\treturn;\n+\t}\n+\n+\tif (parser_read_uint32(&p.n_subport_pipes, tokens[16]) != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_subport_pipes\");\n+\t\treturn;\n+\t}\n+\n+\tif (strcmp(tokens[17], \"qsize\") != 0) {\n+\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"qsize\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++)\n+\t\tif (parser_read_uint16(&p.qsize[i], tokens[18 + i]) != 0) {\n+\t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"qsize\");\n+\t\t\treturn;\n+\t\t}\n+\n \tstatus = tmgr_subport_profile_add(&p);\n \tif (status != 0) {\n \t\tsnprintf(out, out_size, MSG_CMD_FAIL, tokens[0]);\n@@ -425,10 +449,11 @@ cmd_tmgr_subport_profile(char **tokens,\n static const char cmd_tmgr_pipe_profile_help[] =\n \"tmgr pipe profile\\n\"\n \"   <tb_rate> <tb_size>\\n\"\n-\"   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>\\n\"\n+\"   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>\"\n+\"     <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>\\n\"\n \"   <tc_period>\\n\"\n \"   <tc_ov_weight>\\n\"\n-\"   <wrr_weight0..15>\\n\";\n+\"   <wrr_weight0..7>\\n\";\n \n static void\n cmd_tmgr_pipe_profile(char **tokens,\n@@ -439,7 +464,7 @@ cmd_tmgr_pipe_profile(char **tokens,\n \tstruct rte_sched_pipe_params p;\n \tint status, i;\n \n-\tif (n_tokens != 27) {\n+\tif (n_tokens != 24) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -460,20 +485,20 @@ cmd_tmgr_pipe_profile(char **tokens,\n \t\t\treturn;\n \t\t}\n \n-\tif (parser_read_uint32(&p.tc_period, tokens[9]) != 0) {\n+\tif (parser_read_uint32(&p.tc_period, tokens[14]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tc_period\");\n \t\treturn;\n \t}\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n-\tif (parser_read_uint8(&p.tc_ov_weight, tokens[10]) != 0) {\n+\tif (parser_read_uint8(&p.tc_ov_weight, tokens[15]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"tc_ov_weight\");\n \t\treturn;\n \t}\n #endif\n \n-\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++)\n-\t\tif (parser_read_uint8(&p.wrr_weights[i], tokens[11 + i]) != 0) {\n+\tfor (i = 0; i < RTE_SCHED_BE_QUEUES_PER_PIPE; i++)\n+\t\tif (parser_read_uint8(&p.wrr_weights[i], tokens[16 + i]) != 0) {\n \t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"wrr_weights\");\n \t\t\treturn;\n \t\t}\n@@ -489,8 +514,6 @@ static const char cmd_tmgr_help[] =\n \"tmgr <tmgr_name>\\n\"\n \"   rate <rate>\\n\"\n \"   spp <n_subports_per_port>\\n\"\n-\"   pps <n_pipes_per_subport>\\n\"\n-\"   qsize <qsize_tc0> <qsize_tc1> <qsize_tc2> <qsize_tc3>\\n\"\n \"   fo <frame_overhead>\\n\"\n \"   mtu <mtu>\\n\"\n \"   cpu <cpu_id>\\n\";\n@@ -504,9 +527,8 @@ cmd_tmgr(char **tokens,\n \tstruct tmgr_port_params p;\n \tchar *name;\n \tstruct tmgr_port *tmgr_port;\n-\tint i;\n \n-\tif (n_tokens != 19) {\n+\tif (n_tokens != 12) {\n \t\tsnprintf(out, out_size, MSG_ARG_MISMATCH, tokens[0]);\n \t\treturn;\n \t}\n@@ -533,53 +555,32 @@ cmd_tmgr(char **tokens,\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[6], \"pps\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"pps\");\n-\t\treturn;\n-\t}\n-\n-\tif (parser_read_uint32(&p.n_pipes_per_subport, tokens[7]) != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"n_pipes_per_subport\");\n-\t\treturn;\n-\t}\n-\n-\tif (strcmp(tokens[8], \"qsize\") != 0) {\n-\t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"qsize\");\n-\t\treturn;\n-\t}\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tif (parser_read_uint16(&p.qsize[i], tokens[9 + i]) != 0) {\n-\t\t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"qsize\");\n-\t\t\treturn;\n-\t\t}\n-\n-\tif (strcmp(tokens[13], \"fo\") != 0) {\n+\tif (strcmp(tokens[6], \"fo\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"fo\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.frame_overhead, tokens[14]) != 0) {\n+\tif (parser_read_uint32(&p.frame_overhead, tokens[7]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"frame_overhead\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[15], \"mtu\") != 0) {\n+\tif (strcmp(tokens[8], \"mtu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.mtu, tokens[16]) != 0) {\n+\tif (parser_read_uint32(&p.mtu, tokens[9]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"mtu\");\n \t\treturn;\n \t}\n \n-\tif (strcmp(tokens[17], \"cpu\") != 0) {\n+\tif (strcmp(tokens[10], \"cpu\") != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_NOT_FOUND, \"cpu\");\n \t\treturn;\n \t}\n \n-\tif (parser_read_uint32(&p.cpu_id, tokens[18]) != 0) {\n+\tif (parser_read_uint32(&p.cpu_id, tokens[11]) != 0) {\n \t\tsnprintf(out, out_size, MSG_ARG_INVALID, \"cpu_id\");\n \t\treturn;\n \t}\ndiff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c\nindex 40cbf1d0a..5e55e8ef1 100644\n--- a/examples/ip_pipeline/tmgr.c\n+++ b/examples/ip_pipeline/tmgr.c\n@@ -47,7 +47,8 @@ int\n tmgr_subport_profile_add(struct rte_sched_subport_params *p)\n {\n \t/* Check input params */\n-\tif (p == NULL)\n+\tif (p == NULL ||\n+\t\tp->n_subport_pipes == 0)\n \t\treturn -1;\n \n \t/* Save profile */\n@@ -90,7 +91,6 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\ttmgr_port_find(name) ||\n \t\t(params == NULL) ||\n \t\t(params->n_subports_per_port == 0) ||\n-\t\t(params->n_pipes_per_subport == 0) ||\n \t\t(params->cpu_id >= RTE_MAX_NUMA_NODES) ||\n \t\t(n_subport_profiles == 0) ||\n \t\t(n_pipe_profiles == 0))\n@@ -103,18 +103,15 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tp.mtu = params->mtu;\n \tp.frame_overhead = params->frame_overhead;\n \tp.n_subports_per_port = params->n_subports_per_port;\n-\tp.n_pipes_per_subport = params->n_pipes_per_subport;\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tp.qsize[i] = params->qsize[i];\n-\n-\tp.pipe_profiles = pipe_profile;\n-\tp.n_pipe_profiles = n_pipe_profiles;\n \n \ts = rte_sched_port_config(&p);\n \tif (s == NULL)\n \t\treturn NULL;\n \n+\tsubport_profile[0].pipe_profiles = pipe_profile;\n+\tsubport_profile[0].n_pipe_profiles = n_pipe_profiles;\n+\tsubport_profile[0].n_max_pipe_profiles = TMGR_PIPE_PROFILE_MAX;\n+\n \tfor (i = 0; i < params->n_subports_per_port; i++) {\n \t\tint status;\n \n@@ -128,7 +125,7 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \t\t\treturn NULL;\n \t\t}\n \n-\t\tfor (j = 0; j < params->n_pipes_per_subport; j++) {\n+\t\tfor (j = 0; j < subport_profile[0].n_subport_pipes; j++) {\n \t\t\tstatus = rte_sched_pipe_config(\n \t\t\t\ts,\n \t\t\t\ti,\n@@ -153,7 +150,6 @@ tmgr_port_create(const char *name, struct tmgr_port_params *params)\n \tstrlcpy(tmgr_port->name, name, sizeof(tmgr_port->name));\n \ttmgr_port->s = s;\n \ttmgr_port->n_subports_per_port = params->n_subports_per_port;\n-\ttmgr_port->n_pipes_per_subport = params->n_pipes_per_subport;\n \n \t/* Node add to list */\n \tTAILQ_INSERT_TAIL(&tmgr_port_list, tmgr_port, node);\n@@ -205,8 +201,8 @@ tmgr_pipe_config(const char *port_name,\n \tport = tmgr_port_find(port_name);\n \tif ((port == NULL) ||\n \t\t(subport_id >= port->n_subports_per_port) ||\n-\t\t(pipe_id_first >= port->n_pipes_per_subport) ||\n-\t\t(pipe_id_last >= port->n_pipes_per_subport) ||\n+\t\t(pipe_id_first >= subport_profile[0].n_subport_pipes) ||\n+\t\t(pipe_id_last >= subport_profile[0].n_subport_pipes) ||\n \t\t(pipe_id_first > pipe_id_last) ||\n \t\t(pipe_profile_id >= n_pipe_profiles))\n \t\treturn -1;\ndiff --git a/examples/ip_pipeline/tmgr.h b/examples/ip_pipeline/tmgr.h\nindex 0b497e795..3a958492c 100644\n--- a/examples/ip_pipeline/tmgr.h\n+++ b/examples/ip_pipeline/tmgr.h\n@@ -25,7 +25,6 @@ struct tmgr_port {\n \tchar name[NAME_SIZE];\n \tstruct rte_sched_port *s;\n \tuint32_t n_subports_per_port;\n-\tuint32_t n_pipes_per_subport;\n };\n \n TAILQ_HEAD(tmgr_port_list, tmgr_port);\n@@ -39,8 +38,6 @@ tmgr_port_find(const char *name);\n struct tmgr_port_params {\n \tuint32_t rate;\n \tuint32_t n_subports_per_port;\n-\tuint32_t n_pipes_per_subport;\n-\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint32_t frame_overhead;\n \tuint32_t mtu;\n \tuint32_t cpu_id;\ndiff --git a/lib/librte_pipeline/rte_table_action.c b/lib/librte_pipeline/rte_table_action.c\nindex a54ec46bc..47d7efbc1 100644\n--- a/lib/librte_pipeline/rte_table_action.c\n+++ b/lib/librte_pipeline/rte_table_action.c\n@@ -401,7 +401,6 @@ pkt_work_tm(struct rte_mbuf *mbuf,\n {\n \tstruct dscp_table_entry_data *dscp_entry = &dscp_table->entry[dscp];\n \tuint32_t queue_id = data->queue_id |\n-\t\t\t\t(dscp_entry->tc << 2) |\n \t\t\t\tdscp_entry->tc_queue;\n \trte_mbuf_sched_set(mbuf, queue_id, dscp_entry->tc,\n \t\t\t\t(uint8_t)dscp_entry->color);\ndiff --git a/lib/librte_pipeline/rte_table_action.h b/lib/librte_pipeline/rte_table_action.h\nindex ef45a3023..4a68deb2e 100644\n--- a/lib/librte_pipeline/rte_table_action.h\n+++ b/lib/librte_pipeline/rte_table_action.h\n@@ -181,10 +181,10 @@ struct rte_table_action_lb_params {\n  * RTE_TABLE_ACTION_MTR\n  */\n /** Max number of traffic classes (TCs). */\n-#define RTE_TABLE_ACTION_TC_MAX                                  4\n+#define RTE_TABLE_ACTION_TC_MAX                                  16\n \n /** Max number of queues per traffic class. */\n-#define RTE_TABLE_ACTION_TC_QUEUE_MAX                            4\n+#define RTE_TABLE_ACTION_TC_QUEUE_MAX                            16\n \n /** Differentiated Services Code Point (DSCP) translation table entry. */\n struct rte_table_action_dscp_table_entry {\n",
    "prefixes": [
        "v2",
        "26/28"
    ]
}