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{
    "id": 55330,
    "url": "http://patches.dpdk.org/api/patches/55330/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-7-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190625153217.24301-7-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190625153217.24301-7-jasvinder.singh@intel.com",
    "date": "2019-06-25T15:31:55",
    "name": "[v2,06/28] sched: update subport config API",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "7a2848d7d8183d5e204a3cf3502d5630990342e9",
    "submitter": {
        "id": 285,
        "url": "http://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "http://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-7-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 5160,
            "url": "http://patches.dpdk.org/api/series/5160/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5160",
            "date": "2019-06-25T15:31:49",
            "name": "sched: feature enhancements",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/5160/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55330/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55330/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E011A1BACE;\n\tTue, 25 Jun 2019 17:32:17 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id ECC3F1BA5D\n\tfor <dev@dpdk.org>; Tue, 25 Jun 2019 17:32:08 +0200 (CEST)",
            "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jun 2019 08:32:08 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga006.jf.intel.com with ESMTP; 25 Jun 2019 08:32:06 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.63,416,1557212400\"; d=\"scan'208\";a=\"166711451\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com, Abraham Tovar <abrahamx.tovar@intel.com>, \n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>",
        "Date": "Tue, 25 Jun 2019 16:31:55 +0100",
        "Message-Id": "<20190625153217.24301-7-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "References": "<20190528120553.2992-2-lukaszx.krakowiak@intel.com>\n\t<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 06/28] sched: update subport config API",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update suport configuration api implementation to allow\nconfiguration flexiblity for pipe traffic classes and queues,\nand subport level configuration of the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 603 +++++++++++++++++++++++++++++------\n lib/librte_sched/rte_sched.h |   3 +\n 2 files changed, 507 insertions(+), 99 deletions(-)",
    "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 22db212ed..46a98ad63 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -343,44 +343,49 @@ rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)\n \n static int\n pipe_profile_check(struct rte_sched_pipe_params *params,\n-\tuint32_t rate)\n+\tuint32_t rate, uint16_t *qsize)\n {\n \tuint32_t i;\n \n \t/* Pipe parameters */\n \tif (params == NULL)\n-\t\treturn -10;\n+\t\treturn -11;\n \n \t/* TB rate: non-zero, not greater than port rate */\n \tif (params->tb_rate == 0 ||\n \t\tparams->tb_rate > rate)\n-\t\treturn -11;\n+\t\treturn -12;\n \n \t/* TB size: non-zero */\n \tif (params->tb_size == 0)\n-\t\treturn -12;\n+\t\treturn -13;\n \n \t/* TC rate: non-zero, less than pipe rate */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (params->tc_rate[i] == 0 ||\n-\t\t\tparams->tc_rate[i] > params->tb_rate)\n-\t\t\treturn -13;\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASS_BE; i++) {\n+\t\tif ((qsize[i] == 0 && params->tc_rate[i] != 0) ||\n+\t\t\t(qsize[i] != 0 && (params->tc_rate[i] == 0 ||\n+\t\t\tparams->tc_rate[i] > params->tb_rate)))\n+\t\t\treturn -14;\n \t}\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0)\n+\t\treturn -15;\n \n \t/* TC period: non-zero */\n \tif (params->tc_period == 0)\n-\t\treturn -14;\n+\t\treturn -16;\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \t/* TC3 oversubscription weight: non-zero */\n \tif (params->tc_ov_weight == 0)\n-\t\treturn -15;\n+\t\treturn -17;\n #endif\n \n \t/* Queue WRR weights: non-zero */\n-\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n-\t\tif (params->wrr_weights[i] == 0)\n-\t\t\treturn -16;\n+\tfor (i = 0; i < RTE_SCHED_BE_QUEUES_PER_PIPE; i++) {\n+\t\tuint32_t qindex = RTE_SCHED_TRAFFIC_CLASS_BE + i;\n+\t\tif ((qsize[qindex] != 0 && params->wrr_weights[i] == 0) ||\n+\t\t\t(qsize[qindex] == 0 && params->wrr_weights[i] != 0))\n+\t\t\treturn -18;\n \t}\n \n \treturn 0;\n@@ -487,36 +492,181 @@ rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sch\n \treturn base;\n }\n \n-uint32_t\n-rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+static uint32_t\n+rte_sched_subport_get_array_base(struct rte_sched_subport_params *params,\n+\tenum rte_sched_subport_array array)\n {\n-\tuint32_t size0, size1;\n-\tint status;\n+\tuint32_t n_subport_pipes = params->n_subport_pipes;\n+\tuint32_t n_subport_queues = RTE_SCHED_QUEUES_PER_PIPE * n_subport_pipes;\n \n-\tstatus = rte_sched_port_check_params(params);\n-\tif (status != 0) {\n-\t\tRTE_LOG(NOTICE, SCHED,\n-\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\tuint32_t size_pipe = n_subport_pipes * sizeof(struct rte_sched_pipe);\n+\tuint32_t size_queue = n_subport_queues * sizeof(struct rte_sched_queue);\n+\tuint32_t size_queue_extra\n+\t\t= n_subport_queues * sizeof(struct rte_sched_queue_extra);\n+\tuint32_t size_pipe_profiles = params->n_max_pipe_profiles *\n+\t\tsizeof(struct rte_sched_pipe_profile);\n+\tuint32_t size_bmp_array =\n+\t\trte_bitmap_get_memory_footprint(n_subport_queues);\n+\tuint32_t size_per_pipe_queue_array, size_queue_array;\n \n-\t\treturn 0;\n+\tuint32_t base, i;\n+\n+\tsize_per_pipe_queue_array = 0;\n+\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n+\t\tsize_per_pipe_queue_array += params->qsize[i] * sizeof(struct rte_mbuf *);\n \t}\n+\tsize_queue_array = n_subport_pipes * size_per_pipe_queue_array;\n \n-\tsize0 = sizeof(struct rte_sched_port);\n-\tsize1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\tbase = 0;\n \n-\treturn size0 + size1;\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_array);\n+\n+\treturn base;\n+}\n+\n+static void\n+rte_sched_pipe_wrr_queues_config(struct rte_sched_pipe_params *src,\n+\tstruct rte_sched_pipe_profile *dst)\n+{\n+\tuint32_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+\n+\tif (dst->n_be_queues == 1) {\n+\t\tdst->wrr_cost[0] = (uint8_t) src->wrr_weights[0];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 2) {\n+\t\tuint32_t lcd;\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\n+\t\tlcd = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\n+\t\twrr_cost[0] = lcd / wrr_cost[0];\n+\t\twrr_cost[1] = lcd / wrr_cost[1];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 4) {\n+\t\tuint32_t lcd, lcd1, lcd2;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\t\twrr_cost[2] = src->wrr_weights[2];\n+\t\twrr_cost[3] = src->wrr_weights[3];\n+\n+\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n+\t\tlcd = rte_get_lcd(lcd1, lcd2);\n+\n+\t\twrr_cost[0] = lcd / wrr_cost[0];\n+\t\twrr_cost[1] = lcd / wrr_cost[1];\n+\t\twrr_cost[2] = lcd / wrr_cost[2];\n+\t\twrr_cost[3] = lcd / wrr_cost[3];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t\tdst->wrr_cost[2] = (uint8_t) wrr_cost[2];\n+\t\tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 8) {\n+\t\tuint32_t lcd1, lcd2, lcd3, lcd4, lcd5, lcd6, lcd7;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\t\twrr_cost[2] = src->wrr_weights[2];\n+\t\twrr_cost[3] = src->wrr_weights[3];\n+\t\twrr_cost[4] = src->wrr_weights[4];\n+\t\twrr_cost[5] = src->wrr_weights[5];\n+\t\twrr_cost[6] = src->wrr_weights[6];\n+\t\twrr_cost[7] = src->wrr_weights[7];\n+\n+\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n+\t\tlcd3 = rte_get_lcd(wrr_cost[4], wrr_cost[5]);\n+\t\tlcd4 = rte_get_lcd(wrr_cost[6], wrr_cost[7]);\n+\n+\t\tlcd5 = rte_get_lcd(lcd1, lcd2);\n+\t\tlcd6 = rte_get_lcd(lcd3, lcd4);\n+\n+\t\tlcd7 = rte_get_lcd(lcd5, lcd6);\n+\n+\t\twrr_cost[0] = lcd7 / wrr_cost[0];\n+\t\twrr_cost[1] = lcd7 / wrr_cost[1];\n+\t\twrr_cost[2] = lcd7 / wrr_cost[2];\n+\t\twrr_cost[3] = lcd7 / wrr_cost[3];\n+\t\twrr_cost[4] = lcd7 / wrr_cost[4];\n+\t\twrr_cost[5] = lcd7 / wrr_cost[5];\n+\t\twrr_cost[6] = lcd7 / wrr_cost[6];\n+\t\twrr_cost[7] = lcd7 / wrr_cost[7];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t\tdst->wrr_cost[2] = (uint8_t) wrr_cost[2];\n+\t\tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n+\t\tdst->wrr_cost[4] = (uint8_t) wrr_cost[4];\n+\t\tdst->wrr_cost[5] = (uint8_t) wrr_cost[5];\n+\t\tdst->wrr_cost[6] = (uint8_t) wrr_cost[6];\n+\t\tdst->wrr_cost[7] = (uint8_t) wrr_cost[7];\n+\n+\t\treturn;\n+\t}\n+}\n+\n+static void\n+rte_sched_subport_config_qsize(struct rte_sched_subport *subport)\n+{\n+\tuint32_t i;\n+\n+\tsubport->qsize_add[0] = 0;\n+\n+\tfor (i = 1; i < RTE_SCHED_QUEUES_PER_PIPE; i++)\n+\t\tsubport->qsize_add[i] =\n+\t\t\tsubport->qsize_add[i-1] + subport->qsize[i-1];\n+\n+\tsubport->qsize_sum = subport->qsize_add[15] + subport->qsize[15];\n }\n \n static void\n-rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n+rte_sched_port_log_pipe_profile(struct rte_sched_subport *subport, uint32_t i)\n {\n-\tstruct rte_sched_pipe_profile *p = port->pipe_profiles + i;\n+\tstruct rte_sched_pipe_profile *p = subport->pipe_profiles + i;\n \n \tRTE_LOG(DEBUG, SCHED, \"Low level config for pipe profile %u:\\n\"\n \t\t\"    Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n-\t\t\"    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n-\t\t\"    Traffic class 3 oversubscription: weight = %hhu\\n\"\n-\t\t\"    WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu],\\n\",\n+\t\t\"    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u, %u, %u, %u, %u, %u]\\n\"\n+\t\t\"    Traffic class BE oversubscription: weight = %hhu\\n\"\n+\t\t\"    WRR cost: [%hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu]\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -530,6 +680,11 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\tp->tc_credits_per_period[1],\n \t\tp->tc_credits_per_period[2],\n \t\tp->tc_credits_per_period[3],\n+\t\tp->tc_credits_per_period[4],\n+\t\tp->tc_credits_per_period[5],\n+\t\tp->tc_credits_per_period[6],\n+\t\tp->tc_credits_per_period[7],\n+\t\tp->tc_credits_per_period[8],\n \n \t\t/* Traffic class 3 oversubscription */\n \t\tp->tc_ov_weight,\n@@ -550,7 +705,8 @@ rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)\n }\n \n static void\n-rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n+rte_sched_pipe_profile_convert(struct rte_sched_subport *subport,\n+\tstruct rte_sched_pipe_params *src,\n \tstruct rte_sched_pipe_profile *dst,\n \tuint32_t rate)\n {\n@@ -576,43 +732,193 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \t\t\t\t\t\trate);\n \n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tdst->tc_credits_per_period[i]\n-\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n-\t\t\t\tsrc->tc_rate[i]);\n+\t\tif (subport->qsize[i])\n+\t\t\tdst->tc_credits_per_period[i]\n+\t\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n+\t\t\t\t\tsrc->tc_rate[i]);\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \tdst->tc_ov_weight = src->tc_ov_weight;\n #endif\n \n-\t/* WRR */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\t\tuint32_t lcd, lcd1, lcd2;\n-\t\tuint32_t qindex;\n+\t/* WRR queues */\n+\tfor (i = 0; i < RTE_SCHED_BE_QUEUES_PER_PIPE; i++)\n+\t\tif (subport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE + i])\n+\t\t\tdst->n_be_queues++;\n \n-\t\tqindex = i * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;\n+\trte_sched_pipe_wrr_queues_config(src, dst);\n+}\n \n-\t\twrr_cost[0] = src->wrr_weights[qindex];\n-\t\twrr_cost[1] = src->wrr_weights[qindex + 1];\n-\t\twrr_cost[2] = src->wrr_weights[qindex + 2];\n-\t\twrr_cost[3] = src->wrr_weights[qindex + 3];\n+static void\n+rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n+\tstruct rte_sched_subport_params *params, uint32_t rate)\n+{\n+\tuint32_t i;\n \n-\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n-\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n-\t\tlcd = rte_get_lcd(lcd1, lcd2);\n+\tfor (i = 0; i < subport->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n+\t\tstruct rte_sched_pipe_profile *dst = subport->pipe_profiles + i;\n \n-\t\twrr_cost[0] = lcd / wrr_cost[0];\n-\t\twrr_cost[1] = lcd / wrr_cost[1];\n-\t\twrr_cost[2] = lcd / wrr_cost[2];\n-\t\twrr_cost[3] = lcd / wrr_cost[3];\n+\t\trte_sched_pipe_profile_convert(subport, src, dst, rate);\n+\t\trte_sched_port_log_pipe_profile(subport, i);\n+\t}\n+\n+\tsubport->pipe_tc_be_rate_max = 0;\n+\tfor (i = 0; i < subport->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n+\t\tuint32_t pipe_tc_be_rate = src->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE];\n \n-\t\tdst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];\n-\t\tdst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];\n-\t\tdst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];\n-\t\tdst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];\n+\t\tif (subport->pipe_tc_be_rate_max < pipe_tc_be_rate)\n+\t\t\tsubport->pipe_tc_be_rate_max = pipe_tc_be_rate;\n \t}\n }\n \n+static int\n+rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n+\tuint32_t rate)\n+{\n+\tuint32_t i, j;\n+\n+\t/* Check user parameters */\n+\tif (params == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for parameter params \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_rate == 0 || params->tb_rate > rate) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tb rate \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_size == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tb size \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tif (params->tc_rate[i] > params->tb_rate) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Incorrect value for tc rate \\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\tif (params->tc_period == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tc period \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* n_subport_pipes: non-zero, power of 2 */\n+\tif (params->n_subport_pipes == 0 ||\n+\t    !rte_is_power_of_2(params->n_subport_pipes)) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for pipes number \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* qsize: power of 2, if non-zero\n+\t * no bigger than 32K (due to 16-bit read/write pointers)\n+\t */\n+\tfor (i = 0, j = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n+\t\tuint32_t tc_rate = params->tc_rate[j];\n+\t\tuint16_t qsize = params->qsize[i];\n+\n+\t\tif (((qsize == 0) &&\n+\t\t\t((tc_rate != 0) && (j != RTE_SCHED_TRAFFIC_CLASS_BE))) ||\n+\t\t\t((qsize != 0) &&\n+\t\t\t((tc_rate == 0) || !rte_is_power_of_2(qsize)))) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Incorrect value for tc rate \\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (j < RTE_SCHED_TRAFFIC_CLASS_BE)\n+\t\t\tj++;\n+\t}\n+\n+\t/* WRR queues : 1, 4, 8 */\n+\tuint32_t wrr_queues = 0;\n+\tfor (i = 0; i < RTE_SCHED_BE_QUEUES_PER_PIPE; i++) {\n+\t\tif (params->qsize[RTE_SCHED_TRAFFIC_CLASS_BE + i])\n+\t\t\twrr_queues++;\n+\t}\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] &&\n+\t\t(wrr_queues != 1 && wrr_queues != 2 &&\n+\t\twrr_queues != 4 && wrr_queues != 8)) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for wrr weights \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* pipe_profiles and n_pipe_profiles */\n+\tif (params->pipe_profiles == NULL ||\n+\t    params->n_pipe_profiles == 0 ||\n+\t\t params->n_pipe_profiles > params->n_max_pipe_profiles) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for number of pipe profiles \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static uint32_t\n+rte_sched_subport_get_memory_footprint(struct rte_sched_port *port,\n+\tuint32_t subport_id, struct rte_sched_subport_params *params)\n+{\n+\tuint32_t size0, size1;\n+\tint status;\n+\n+\tif (port == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for parameter port \\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\n+\tif (subport_id >= port->n_subports_per_port) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for subport id \\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\n+\tstatus = rte_sched_subport_check_params(params, port->rate);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_subport);\n+\tsize1 = rte_sched_subport_get_array_base(params,\n+\t\t\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL);\n+\n+\treturn size0 + size1;\n+}\n+\n+uint32_t\n+rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+{\n+\tuint32_t size0, size1;\n+\tint status;\n+\n+\tstatus = rte_sched_port_check_params(params);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_port);\n+\tsize1 = rte_sched_port_get_array_base(params,\n+\t\t\te_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\n+\treturn size0 + size1;\n+}\n+\n struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n@@ -710,12 +1016,12 @@ rte_sched_port_free(struct rte_sched_port *port)\n static void\n rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n {\n-\tstruct rte_sched_subport *s = port->subport + i;\n+\tstruct rte_sched_subport *s = port->subports[i];\n \n \tRTE_LOG(DEBUG, SCHED, \"Low level config for subport %u:\\n\"\n \t\t\"    Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n-\t\t\"    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n-\t\t\"    Traffic class 3 oversubscription: wm min = %u, wm max = %u\\n\",\n+\t\t\"    Traffic classes: period = %u, credits per period = [%u, %u, %u, %u, %u, %u, %u, %u, %u]\\n\"\n+\t\t\"    Traffic class BE oversubscription: wm min = %u, wm max = %u\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -729,8 +1035,13 @@ rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n \t\ts->tc_credits_per_period[1],\n \t\ts->tc_credits_per_period[2],\n \t\ts->tc_credits_per_period[3],\n+\t\ts->tc_credits_per_period[4],\n+\t\ts->tc_credits_per_period[5],\n+\t\ts->tc_credits_per_period[6],\n+\t\ts->tc_credits_per_period[7],\n+\t\ts->tc_credits_per_period[8],\n \n-\t\t/* Traffic class 3 oversubscription */\n+\t\t/* Traffic class BE oversubscription */\n \t\ts->tc_ov_wm_min,\n \t\ts->tc_ov_wm_max);\n }\n@@ -740,31 +1051,26 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \tuint32_t subport_id,\n \tstruct rte_sched_subport_params *params)\n {\n-\tstruct rte_sched_subport *s;\n-\tuint32_t i;\n+\tstruct rte_sched_subport *s = NULL;\n+\tuint32_t mem_size, bmp_mem_size, n_subport_queues, n_subport_pipes_log2, i;\n \n-\t/* Check user parameters */\n-\tif (port == NULL ||\n-\t    subport_id >= port->n_subports_per_port ||\n-\t    params == NULL)\n-\t\treturn -1;\n-\n-\tif (params->tb_rate == 0 || params->tb_rate > port->rate)\n-\t\treturn -2;\n-\n-\tif (params->tb_size == 0)\n-\t\treturn -3;\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (params->tc_rate[i] == 0 ||\n-\t\t    params->tc_rate[i] > params->tb_rate)\n-\t\t\treturn -4;\n+\t/* Check user parameters. Determine the amount of memory to allocate */\n+\tmem_size = rte_sched_subport_get_memory_footprint(port,\n+\t\tsubport_id, params);\n+\tif (mem_size == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Fail to determine the memory to allocate \\n\", __func__);\n+\t\treturn -EINVAL;\n \t}\n \n-\tif (params->tc_period == 0)\n-\t\treturn -5;\n-\n-\ts = port->subport + subport_id;\n+\t/* Allocate memory to store the data structures */\n+\ts = rte_zmalloc_socket(\"subport_params\", mem_size, RTE_CACHE_LINE_SIZE,\n+\t\tport->socket);\n+\tif (s == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Memory allocation fails \\n\", __func__);\n+\t\treturn -ENOMEM;\n+\t}\n \n \t/* Token Bucket (TB) */\n \tif (params->tb_rate == port->rate) {\n@@ -784,19 +1090,110 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t/* Traffic Classes (TCs) */\n \ts->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\ts->tc_credits_per_period[i]\n-\t\t\t= rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t     params->tc_rate[i]);\n+\t\tif (params->qsize[i])\n+\t\t\ts->tc_credits_per_period[i]\n+\t\t\t\t= rte_sched_time_ms_to_bytes(params->tc_period,\n+\t\t\t\t\tparams->tc_rate[i]);\n \t}\n \ts->tc_time = port->time + s->tc_period;\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n+\t\tif (params->qsize[i])\n+\t\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n+\n+\t/* compile time checks */\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS &\n+\t\t(RTE_SCHED_PORT_N_GRINDERS - 1));\n+\n+\t/* User parameters */\n+\ts->n_subport_pipes = params->n_subport_pipes;\n+\tn_subport_pipes_log2 = __builtin_ctz(params->n_subport_pipes);\n+\tmemcpy(s->qsize, params->qsize, sizeof(params->qsize));\n+\ts->n_pipe_profiles = params->n_pipe_profiles;\n+\ts->n_max_pipe_profiles = params->n_max_pipe_profiles;\n+\n+#ifdef RTE_SCHED_RED\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint32_t j;\n+\n+\t\tfor (j = 0; j < RTE_COLORS; j++) {\n+\t\t\t/* if min/max are both zero, then RED is disabled */\n+\t\t\tif ((params->red_params[i][j].min_th |\n+\t\t\t     params->red_params[i][j].max_th) == 0) {\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (rte_red_config_init(&s->red_config[i][j],\n+\t\t\t\tparams->red_params[i][j].wq_log2,\n+\t\t\t\tparams->red_params[i][j].min_th,\n+\t\t\t\tparams->red_params[i][j].max_th,\n+\t\t\t\tparams->red_params[i][j].maxp_inv) != 0) {\n+\t\t\t\trte_free(s);\n+\t\t\t\treturn -3;\n+\t\t\t}\n+\t\t}\n+\t}\n+#endif\n+\n+\t/* Scheduling loop detection */\n+\ts->pipe_loop = RTE_SCHED_PIPE_INVALID;\n+\ts->pipe_exhaustion = 0;\n+\n+\t/* Grinders */\n+\ts->busy_grinders = 0;\n+\n+\t/* Queue base calculation */\n+\trte_sched_subport_config_qsize(s);\n+\n+\t/* Large data structures */\n+\ts->pipe = (struct rte_sched_pipe *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_PIPE));\n+\ts->queue = (struct rte_sched_queue *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE));\n+\ts->queue_extra = (struct rte_sched_queue_extra *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA));\n+\ts->pipe_profiles = (struct rte_sched_pipe_profile *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES));\n+\ts->bmp_array =  s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY);\n+\ts->queue_array = (struct rte_mbuf **)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY));\n+\n+\t/* Pipe profile table */\n+\trte_sched_subport_config_pipe_profile_table(s, params, port->rate);\n+\n+\t/* Bitmap */\n+\tn_subport_queues = rte_sched_subport_queues(s);\n+\tbmp_mem_size = rte_bitmap_get_memory_footprint(n_subport_queues);\n+\ts->bmp = rte_bitmap_init(n_subport_queues, s->bmp_array,\n+\t\t\t\tbmp_mem_size);\n+\tif (s->bmp == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Subport bitmap init error \\n\", __func__);\n+\n+\t\trte_free(port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)\n+\t\ts->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n+\n+\t/* Port */\n+\tport->subports[subport_id] = s;\n+\n+\tif (n_subport_pipes_log2 > port->max_subport_pipes_log2)\n+\t\tport->max_subport_pipes_log2 = n_subport_pipes_log2;\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \t/* TC oversubscription */\n \ts->tc_ov_wm_min = port->mtu;\n \ts->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t     port->pipe_tc3_rate_max);\n+\t\t\t\t\t\t     s->pipe_tc_be_rate_max);\n \ts->tc_ov_wm = s->tc_ov_wm_max;\n \ts->tc_ov_period_id = 0;\n \ts->tc_ov = 0;\n@@ -909,10 +1306,12 @@ rte_sched_pipe_config(struct rte_sched_port *port,\n \n int __rte_experimental\n rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n+\tuint32_t subport_id,\n \tstruct rte_sched_pipe_params *params,\n \tuint32_t *pipe_profile_id)\n {\n \tstruct rte_sched_pipe_profile *pp;\n+\tstruct rte_sched_subport *s;\n \tuint32_t i;\n \tint status;\n \n@@ -920,31 +1319,37 @@ rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n \tif (port == NULL)\n \t\treturn -1;\n \n-\t/* Pipe profiles not exceeds the max limit */\n-\tif (port->n_pipe_profiles >= RTE_SCHED_PIPE_PROFILES_PER_PORT)\n+\t/* Subport id not exceeds the max limit */\n+\tif (subport_id > port->n_subports_per_port)\n \t\treturn -2;\n \n+\ts = port->subports[subport_id];\n+\n+\t/* Pipe profiles not exceeds the max limit */\n+\tif (s->n_pipe_profiles >= s->n_max_pipe_profiles)\n+\t\treturn -3;\n+\n \t/* Pipe params */\n-\tstatus = pipe_profile_check(params, port->rate);\n+\tstatus = pipe_profile_check(params, port->rate, &s->qsize[0]);\n \tif (status != 0)\n \t\treturn status;\n \n-\tpp = &port->pipe_profiles[port->n_pipe_profiles];\n-\trte_sched_pipe_profile_convert(params, pp, port->rate);\n+\tpp = &s->pipe_profiles[s->n_pipe_profiles];\n+\trte_sched_pipe_profile_convert(s, params, pp, port->rate);\n \n \t/* Pipe profile not exists */\n-\tfor (i = 0; i < port->n_pipe_profiles; i++)\n-\t\tif (memcmp(port->pipe_profiles + i, pp, sizeof(*pp)) == 0)\n-\t\t\treturn -3;\n+\tfor (i = 0; i < s->n_pipe_profiles; i++)\n+\t\tif (memcmp(s->pipe_profiles + i, pp, sizeof(*pp)) == 0)\n+\t\t\treturn -4;\n \n \t/* Pipe profile commit */\n-\t*pipe_profile_id = port->n_pipe_profiles;\n-\tport->n_pipe_profiles++;\n+\t*pipe_profile_id = s->n_pipe_profiles;\n+\ts->n_pipe_profiles++;\n \n-\tif (port->pipe_tc3_rate_max < params->tc_rate[3])\n-\t\tport->pipe_tc3_rate_max = params->tc_rate[3];\n+\tif (s->pipe_tc_be_rate_max < params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE])\n+\t\ts->pipe_tc_be_rate_max = params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE];\n \n-\trte_sched_port_log_pipe_profile(port, *pipe_profile_id);\n+\trte_sched_port_log_pipe_profile(s, *pipe_profile_id);\n \n \treturn 0;\n }\ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex ebde07669..6ebc592ff 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -296,6 +296,8 @@ rte_sched_port_free(struct rte_sched_port *port);\n  *\n  * @param port\n  *   Handle to port scheduler instance\n+ * @param subport_id\n+ *   Subport ID\n  * @param params\n  *   Pipe profile parameters\n  * @param pipe_profile_id\n@@ -305,6 +307,7 @@ rte_sched_port_free(struct rte_sched_port *port);\n  */\n int __rte_experimental\n rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n+\tuint32_t subport_id,\n \tstruct rte_sched_pipe_params *params,\n \tuint32_t *pipe_profile_id);\n \n",
    "prefixes": [
        "v2",
        "06/28"
    ]
}