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GET /api/patches/55251/?format=api
{ "id": 55251, "url": "http://patches.dpdk.org/api/patches/55251/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190624154018.128379-4-jackmin@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190624154018.128379-4-jackmin@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190624154018.128379-4-jackmin@mellanox.com", "date": "2019-06-24T15:40:17", "name": "[3/4] net/mlx5: match GRE's key and present bits", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "23080c1d9a92776f06840ed8ed433a8e9c72756d", "submitter": { "id": 1065, "url": "http://patches.dpdk.org/api/people/1065/?format=api", "name": "Xiaoyu Min", "email": "jackmin@mellanox.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190624154018.128379-4-jackmin@mellanox.com/mbox/", "series": [ { "id": 5134, "url": "http://patches.dpdk.org/api/series/5134/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5134", "date": "2019-06-24T15:40:14", "name": "ethdev: add GRE key field to flow API", "version": 1, "mbox": "http://patches.dpdk.org/series/5134/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55251/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55251/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A08811BD26;\n\tMon, 24 Jun 2019 17:40:31 +0200 (CEST)", "from git-send-mailer.rdmz.labs.mlnx (unknown [37.142.13.130])\n\tby dpdk.org (Postfix) with ESMTP id D10271BC87\n\tfor <dev@dpdk.org>; Mon, 24 Jun 2019 17:40:25 +0200 (CEST)" ], "From": "Xiaoyu Min <jackmin@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>", "Cc": "dev@dpdk.org", "Date": "Mon, 24 Jun 2019 23:40:17 +0800", "Message-Id": "<20190624154018.128379-4-jackmin@mellanox.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190624154018.128379-1-jackmin@mellanox.com>", "References": "<20190624154018.128379-1-jackmin@mellanox.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 3/4] net/mlx5: match GRE's key and present bits", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "support matching on the present bits (C,K,S)\nas well as the optional key field.\n\nIf the rte_flow_item_gre_key is specified in pattern,\nit will set K present match automatically.\n\nSigned-off-by: Xiaoyu Min <jackmin@mellanox.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 49 +++++++++++++++++++-\n drivers/net/mlx5/mlx5_flow.h | 5 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 80 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_prm.h | 6 ++-\n 4 files changed, 138 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 4cb04c32ff..4f0583eead 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1564,6 +1564,49 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,\n \t\t\t\t\t \" defined\");\n \treturn 0;\n }\n+/**\n+ * Validate GRE Key item.\n+ *\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] item_flags\n+ * Bit flags to mark detected items.\n+ * @param[in] target_protocol\n+ * The next protocol in the previous item.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,\n+\t\t\t\t uint64_t item_flags,\n+\t\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_gre_key *mask = item->mask;\n+\tint ret = 0;\n+\n+\tif (item_flags & MLX5_FLOW_LAYER_GRE_KEY)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"Multiple GRE key not support\");\n+\tif (!(item_flags & MLX5_FLOW_LAYER_GRE))\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"No preceding GRE header\");\n+\tif (item_flags & MLX5_FLOW_LAYER_INNER)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t\t\t \"GRE key following a wrong item\");\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_gre_key_mask;\n+\tret = mlx5_flow_item_acceptable\n+\t\t(item, (const uint8_t *)mask,\n+\t\t (const uint8_t *)&rte_flow_item_gre_key_mask,\n+\t\t sizeof(struct rte_flow_item_gre_key), error);\n+\treturn ret;\n+}\n \n /**\n * Validate GRE item.\n@@ -1589,6 +1632,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,\n \tconst struct rte_flow_item_gre *spec __rte_unused = item->spec;\n \tconst struct rte_flow_item_gre *mask = item->mask;\n \tint ret;\n+\tconst struct rte_flow_item_gre nic_mask = {\n+\t\t.c_rsvd0_ver = RTE_BE16(0xB000),\n+\t\t.protocol = RTE_BE16(UINT16_MAX),\n+\t};\n \n \tif (target_protocol != 0xff && target_protocol != IPPROTO_GRE)\n \t\treturn rte_flow_error_set(error, EINVAL,\n@@ -1608,7 +1655,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,\n \t\tmask = &rte_flow_item_gre_mask;\n \tret = mlx5_flow_item_acceptable\n \t\t(item, (const uint8_t *)mask,\n-\t\t (const uint8_t *)&rte_flow_item_gre_mask,\n+\t\t (const uint8_t *)&nic_mask,\n \t\t sizeof(struct rte_flow_item_gre), error);\n \tif (ret < 0)\n \t\treturn ret;\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex b6654200cb..0d83539cc9 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -50,6 +50,8 @@\n #define MLX5_FLOW_ITEM_METADATA (1u << 16)\n #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)\n \n+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -480,6 +482,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,\n \t\t\t\tuint64_t item_flags,\n \t\t\t\tuint8_t target_protocol,\n \t\t\t\tstruct rte_flow_error *error);\n+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,\n+\t\t\t\t uint64_t item_flags,\n+\t\t\t\t struct rte_flow_error *error);\n int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t const struct rte_flow_item_ipv4 *acc_mask,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 933ad0b819..eca926d670 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_LAYER_GRE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n+\t\t\tret = mlx5_flow_validate_item_gre_key\n+\t\t\t\t(items, item_flags, error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_GRE_KEY;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n \t\t\tret = mlx5_flow_validate_item_vxlan(items, item_flags,\n \t\t\t\t\t\t\t error);\n@@ -2922,6 +2929,43 @@ flow_dv_translate_item_udp(void *matcher, void *key,\n \t\t rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));\n }\n \n+/**\n+ * Add GRE optional Key item to matcher and to the value.\n+ *\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ * @param[in] inner\n+ * Item is inner pattern.\n+ */\n+static void\n+flow_dv_translate_item_gre_key(void *matcher, void *key,\n+\t\t\t\t const struct rte_flow_item *item)\n+{\n+\tconst struct rte_flow_item_gre_key *key_m = item->mask;\n+\tconst struct rte_flow_item_gre_key *key_v = item->spec;\n+\tvoid *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);\n+\tvoid *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n+\n+\tif (!key_v)\n+\t\treturn;\n+\tif (!key_m)\n+\t\tkey_m = &rte_flow_item_gre_key_mask;\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_key_h,\n+\t\t rte_be_to_cpu_32(key_m->key) >> 8);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_key_h,\n+\t\t rte_be_to_cpu_32(key_v->key & key_m->key) >> 8);\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_key_l,\n+\t\t rte_be_to_cpu_32(key_m->key) & 0xFF);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_key_l,\n+\t\t rte_be_to_cpu_32(key_v->key & key_m->key) & 0xFF);\n+}\n+\n /**\n * Add GRE item to matcher and to the value.\n *\n@@ -2945,6 +2989,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,\n \tvoid *headers_v;\n \tvoid *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);\n \tvoid *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n+\tstruct {\n+\t\tunion {\n+\t\t\t__extension__\n+\t\t\tstruct {\n+\t\t\t\tuint16_t version:3;\n+\t\t\t\tuint16_t rsvd0:9;\n+\t\t\t\tuint16_t s_present:1;\n+\t\t\t\tuint16_t k_present:1;\n+\t\t\t\tuint16_t rsvd_bit1:1;\n+\t\t\t\tuint16_t c_present:1;\n+\t\t\t};\n+\t\t\tuint16_t value;\n+\t\t};\n+\t} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;\n \n \tif (inner) {\n \t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n@@ -2965,6 +3023,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,\n \t\t rte_be_to_cpu_16(gre_m->protocol));\n \tMLX5_SET(fte_match_set_misc, misc_v, gre_protocol,\n \t\t rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));\n+\tgre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);\n+\tgre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_c_present,\n+\t\t gre_crks_rsvd0_ver_m.c_present);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_c_present,\n+\t\t gre_crks_rsvd0_ver_v.c_present &\n+\t\t gre_crks_rsvd0_ver_m.c_present);\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_k_present,\n+\t\t gre_crks_rsvd0_ver_m.k_present);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_k_present,\n+\t\t gre_crks_rsvd0_ver_v.k_present &\n+\t\t gre_crks_rsvd0_ver_m.k_present);\n+\tMLX5_SET(fte_match_set_misc, misc_m, gre_s_present,\n+\t\t gre_crks_rsvd0_ver_m.s_present);\n+\tMLX5_SET(fte_match_set_misc, misc_v, gre_s_present,\n+\t\t gre_crks_rsvd0_ver_v.s_present &\n+\t\t gre_crks_rsvd0_ver_m.s_present);\n }\n \n /**\n@@ -3995,6 +4070,11 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t items, tunnel);\n \t\t\tlast_item = MLX5_FLOW_LAYER_GRE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n+\t\t\tflow_dv_translate_item_gre_key(match_mask,\n+\t\t\t\t\t\t\t match_value, items);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_GRE_KEY;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n \t\t\tflow_dv_translate_item_nvgre(match_mask, match_value,\n \t\t\t\t\t\t items, tunnel);\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 1a199580c5..4022770b7b 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -416,7 +416,11 @@ typedef uint8_t u8;\n #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)\n \n struct mlx5_ifc_fte_match_set_misc_bits {\n-\tu8 reserved_at_0[0x8];\n+\tu8 gre_c_present[0x1];\n+\tu8 reserved_at_1[0x1];\n+\tu8 gre_k_present[0x1];\n+\tu8 gre_s_present[0x1];\n+\tu8 source_vhci_port[0x4];\n \tu8 source_sqn[0x18];\n \tu8 reserved_at_20[0x10];\n \tu8 source_port[0x10];\n", "prefixes": [ "3/4" ] }