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GET /api/patches/55210/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55210,
    "url": "http://patches.dpdk.org/api/patches/55210/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-22-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190622132417.32694-22-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-22-jerinj@marvell.com",
    "date": "2019-06-22T13:24:11",
    "name": "[v4,21/27] mempool/octeontx2: add mempool alloc op",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b402caef820dc8945e5eb147a26ec96be3ca8bb9",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-22-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5124,
            "url": "http://patches.dpdk.org/api/series/5124/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5124",
            "date": "2019-06-22T13:23:50",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/5124/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55210/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55210/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C797D1C5E7;\n\tSat, 22 Jun 2019 15:26:18 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 76CB61C609\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 15:25:34 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5MDOdZS028280; Sat, 22 Jun 2019 06:25:33 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2t9hpnrgh0-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSat, 22 Jun 2019 06:25:33 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 22 Jun 2019 06:25:32 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 22 Jun 2019 06:25:32 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 666173F703F;\n\tSat, 22 Jun 2019 06:25:30 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=6ABF1zIvOGHbh2y/GLyfWGxwDoYPkutJ+zY8cwag3Ds=;\n\tb=gF/5bjLfMiIiADVCPpAStwLt2y/CdmXKCxJvrMt75I4V5d6vbiyagHzKLHWS6HwTXFgS\n\t+nE/lXpMtCa8YEOiyk0D1dSqtc/fX6iSkor1HbdJbKVEIushgIAeqrf60Ccp4Yiz1Zg1\n\t66OeZ4A9nJcadM+vvxN/+qtFfaLsi3f0T9DVyTSUbZD0cyJMGJiizc3yJr1H0gIeQxHa\n\tFx8LmkxkPlcDj6g/JY89ywVmByQpLj5Kq7x3mXs0X5/cy7thWscnmwHYz0oIPM4HHxkJ\n\tqNQFzUq4/h9l/7UNjJ3TUnaEy5gll/D5hYNvZ8uWTLK+lNhce/BaiuNYI+Q5s0NYp24t\n\tcg== ",
        "From": "<jerinj@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "<dev@dpdk.org>, Olivier Matz <olivier.matz@6wind.com>",
        "Date": "Sat, 22 Jun 2019 18:54:11 +0530",
        "Message-ID": "<20190622132417.32694-22-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>",
        "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v4 21/27] mempool/octeontx2: add mempool alloc op",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe DPDK mempool allocation reserves a single HW AURA\nand POOL in 1:1 map mode. Upon reservation, SW programs the slow path\noperations such as allocate stack memory for DMA and\nbunch HW configurations to respective HW blocks.\n\nCc: Olivier Matz <olivier.matz@6wind.com>\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/mempool/octeontx2/Makefile           |   1 +\n drivers/mempool/octeontx2/meson.build        |   3 +-\n drivers/mempool/octeontx2/otx2_mempool_ops.c | 246 +++++++++++++++++++\n 3 files changed, 249 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mempool/octeontx2/otx2_mempool_ops.c",
    "diff": "diff --git a/drivers/mempool/octeontx2/Makefile b/drivers/mempool/octeontx2/Makefile\nindex b86d469f4..b3568443e 100644\n--- a/drivers/mempool/octeontx2/Makefile\n+++ b/drivers/mempool/octeontx2/Makefile\n@@ -28,6 +28,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \\\n+\totx2_mempool_ops.c\t\\\n \totx2_mempool.c \t\t\\\n \totx2_mempool_irq.c\t\\\n \totx2_mempool_debug.c\ndiff --git a/drivers/mempool/octeontx2/meson.build b/drivers/mempool/octeontx2/meson.build\nindex ab306b729..9fde40f0e 100644\n--- a/drivers/mempool/octeontx2/meson.build\n+++ b/drivers/mempool/octeontx2/meson.build\n@@ -2,7 +2,8 @@\n # Copyright(C) 2019 Marvell International Ltd.\n #\n \n-sources = files('otx2_mempool.c',\n+sources = files('otx2_mempool_ops.c',\n+\t\t'otx2_mempool.c',\n \t\t'otx2_mempool_irq.c',\n \t\t'otx2_mempool_debug.c'\n \t\t)\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c\nnew file mode 100644\nindex 000000000..0e7b7a77c\n--- /dev/null\n+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c\n@@ -0,0 +1,246 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_mempool.h>\n+#include <rte_vect.h>\n+\n+#include \"otx2_mempool.h\"\n+\n+static int\n+npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id,\n+\t\t      struct npa_aura_s *aura, struct npa_pool_s *pool)\n+{\n+\tstruct npa_aq_enq_req *aura_init_req, *pool_init_req;\n+\tstruct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp;\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n+\tint rc, off;\n+\n+\taura_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n+\n+\taura_init_req->aura_id = aura_id;\n+\taura_init_req->ctype = NPA_AQ_CTYPE_AURA;\n+\taura_init_req->op = NPA_AQ_INSTOP_INIT;\n+\tmemcpy(&aura_init_req->aura, aura, sizeof(*aura));\n+\n+\tpool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n+\n+\tpool_init_req->aura_id = aura_id;\n+\tpool_init_req->ctype = NPA_AQ_CTYPE_POOL;\n+\tpool_init_req->op = NPA_AQ_INSTOP_INIT;\n+\tmemcpy(&pool_init_req->pool, pool, sizeof(*pool));\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\toff = mbox->rx_start +\n+\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\taura_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n+\toff = mbox->rx_start + aura_init_rsp->hdr.next_msgoff;\n+\tpool_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n+\n+\tif (rc == 2 && aura_init_rsp->hdr.rc == 0 && pool_init_rsp->hdr.rc == 0)\n+\t\treturn 0;\n+\telse\n+\t\treturn NPA_LF_ERR_AURA_POOL_INIT;\n+}\n+\n+static inline char*\n+npa_lf_stack_memzone_name(struct otx2_npa_lf *lf, int pool_id, char *name)\n+{\n+\tsnprintf(name, RTE_MEMZONE_NAMESIZE, \"otx2_npa_stack_%x_%d\",\n+\t\t\tlf->pf_func, pool_id);\n+\n+\treturn name;\n+}\n+\n+static inline const struct rte_memzone *\n+npa_lf_stack_dma_alloc(struct otx2_npa_lf *lf, char *name,\n+\t\t       int pool_id, size_t size)\n+{\n+\treturn rte_memzone_reserve_aligned(\n+\t\tnpa_lf_stack_memzone_name(lf, pool_id, name), size, 0,\n+\t\t\tRTE_MEMZONE_IOVA_CONTIG, OTX2_ALIGN);\n+}\n+\n+static inline int\n+bitmap_ctzll(uint64_t slab)\n+{\n+\tif (slab == 0)\n+\t\treturn 0;\n+\n+\treturn __builtin_ctzll(slab);\n+}\n+\n+static int\n+npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const uint32_t block_size,\n+\t\t\t    const uint32_t block_count, struct npa_aura_s *aura,\n+\t\t\t    struct npa_pool_s *pool, uint64_t *aura_handle)\n+{\n+\tint rc, aura_id, pool_id, stack_size, alloc_size;\n+\tchar name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\tuint64_t slab;\n+\tuint32_t pos;\n+\n+\t/* Sanity check */\n+\tif (!lf || !block_size || !block_count ||\n+\t    !pool || !aura || !aura_handle)\n+\t\treturn NPA_LF_ERR_PARAM;\n+\n+\t/* Block size should be cache line aligned and in range of 128B-128KB */\n+\tif (block_size % OTX2_ALIGN || block_size < 128 ||\n+\t    block_size > 128 * 1024)\n+\t\treturn NPA_LF_ERR_INVALID_BLOCK_SZ;\n+\n+\tpos = slab = 0;\n+\t/* Scan from the beginning */\n+\t__rte_bitmap_scan_init(lf->npa_bmp);\n+\t/* Scan bitmap to get the free pool */\n+\trc = rte_bitmap_scan(lf->npa_bmp, &pos, &slab);\n+\t/* Empty bitmap */\n+\tif (rc == 0) {\n+\t\totx2_err(\"Mempools exhausted, 'max_pools' devargs to increase\");\n+\t\treturn -ERANGE;\n+\t}\n+\n+\t/* Get aura_id from resource bitmap */\n+\taura_id = pos + bitmap_ctzll(slab);\n+\t/* Mark pool as reserved */\n+\trte_bitmap_clear(lf->npa_bmp, aura_id);\n+\n+\t/* Configuration based on each aura has separate pool(aura-pool pair) */\n+\tpool_id = aura_id;\n+\trc = (aura_id < 0 || pool_id >= (int)lf->nr_pools || aura_id >=\n+\t      (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_LF_ERR_AURA_ID_ALLOC : 0;\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\t/* Allocate stack memory */\n+\tstack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs;\n+\talloc_size = stack_size * lf->stack_pg_bytes;\n+\n+\tmz = npa_lf_stack_dma_alloc(lf, name, pool_id, alloc_size);\n+\tif (mz == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto aura_res_put;\n+\t}\n+\n+\t/* Update aura fields */\n+\taura->pool_addr = pool_id;/* AF will translate to associated poolctx */\n+\taura->ena = 1;\n+\taura->shift = __builtin_clz(block_count) - 8;\n+\taura->limit = block_count;\n+\taura->pool_caching = 1;\n+\taura->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER);\n+\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);\n+\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);\n+\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);\n+\t/* Many to one reduction */\n+\taura->err_qint_idx = aura_id % lf->qints;\n+\n+\t/* Update pool fields */\n+\tpool->stack_base = mz->iova;\n+\tpool->ena = 1;\n+\tpool->buf_size = block_size / OTX2_ALIGN;\n+\tpool->stack_max_pages = stack_size;\n+\tpool->shift = __builtin_clz(block_count) - 8;\n+\tpool->ptr_start = 0;\n+\tpool->ptr_end = ~0;\n+\tpool->stack_caching = 1;\n+\tpool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);\n+\tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);\n+\tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);\n+\n+\t/* Many to one reduction */\n+\tpool->err_qint_idx = pool_id % lf->qints;\n+\n+\t/* Issue AURA_INIT and POOL_INIT op */\n+\trc = npa_lf_aura_pool_init(lf->mbox, aura_id, aura, pool);\n+\tif (rc)\n+\t\tgoto stack_mem_free;\n+\n+\t*aura_handle = npa_lf_aura_handle_gen(aura_id, lf->base);\n+\n+\t/* Update aura count */\n+\tnpa_lf_aura_op_cnt_set(*aura_handle, 0, block_count);\n+\t/* Read it back to make sure aura count is updated */\n+\tnpa_lf_aura_op_cnt_get(*aura_handle);\n+\n+\treturn 0;\n+\n+stack_mem_free:\n+\trte_memzone_free(mz);\n+aura_res_put:\n+\trte_bitmap_set(lf->npa_bmp, aura_id);\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+otx2_npa_alloc(struct rte_mempool *mp)\n+{\n+\tuint32_t block_size, block_count;\n+\tstruct otx2_npa_lf *lf;\n+\tstruct npa_aura_s aura;\n+\tstruct npa_pool_s pool;\n+\tuint64_t aura_handle;\n+\tint rc;\n+\n+\tlf = otx2_npa_lf_obj_get();\n+\tif (lf == NULL) {\n+\t\trc = -EINVAL;\n+\t\tgoto error;\n+\t}\n+\n+\tblock_size = mp->elt_size + mp->header_size + mp->trailer_size;\n+\tblock_count = mp->size;\n+\n+\tif (block_size % OTX2_ALIGN != 0) {\n+\t\totx2_err(\"Block size should be multiple of 128B\");\n+\t\trc = -ERANGE;\n+\t\tgoto error;\n+\t}\n+\n+\tmemset(&aura, 0, sizeof(struct npa_aura_s));\n+\tmemset(&pool, 0, sizeof(struct npa_pool_s));\n+\tpool.nat_align = 1;\n+\tpool.buf_offset = 1;\n+\n+\tif ((uint32_t)pool.buf_offset * OTX2_ALIGN != mp->header_size) {\n+\t\totx2_err(\"Unsupported mp->header_size=%d\", mp->header_size);\n+\t\trc = -EINVAL;\n+\t\tgoto error;\n+\t}\n+\n+\t/* Use driver specific mp->pool_config to override aura config */\n+\tif (mp->pool_config != NULL)\n+\t\tmemcpy(&aura, mp->pool_config, sizeof(struct npa_aura_s));\n+\n+\trc = npa_lf_aura_pool_pair_alloc(lf, block_size, block_count,\n+\t\t\t &aura, &pool, &aura_handle);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to alloc pool or aura rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n+\t/* Store aura_handle for future queue operations */\n+\tmp->pool_id = aura_handle;\n+\totx2_npa_dbg(\"lf=%p block_sz=%d block_count=%d aura_handle=0x%\"PRIx64,\n+\t\t     lf, block_size, block_count, aura_handle);\n+\n+\t/* Just hold the reference of the object */\n+\totx2_npa_lf_obj_ref();\n+\treturn 0;\n+error:\n+\treturn rc;\n+}\n+\n+static struct rte_mempool_ops otx2_npa_ops = {\n+\t.name = \"octeontx2_npa\",\n+\t.alloc = otx2_npa_alloc,\n+};\n+\n+MEMPOOL_REGISTER_OPS(otx2_npa_ops);\n",
    "prefixes": [
        "v4",
        "21/27"
    ]
}