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GET /api/patches/55208/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55208,
    "url": "http://patches.dpdk.org/api/patches/55208/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-20-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190622132417.32694-20-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-20-jerinj@marvell.com",
    "date": "2019-06-22T13:24:09",
    "name": "[v4,19/27] mempool/octeontx2: add NPA IRQ handler",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "67e313ff9d17f1770145477c9d8b0cabfd00ddc3",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-20-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5124,
            "url": "http://patches.dpdk.org/api/series/5124/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5124",
            "date": "2019-06-22T13:23:50",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/5124/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55208/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55208/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DF9681CFC2;\n\tSat, 22 Jun 2019 15:25:52 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 585B91C59E\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 15:25:28 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5MDP4Te030637 for <dev@dpdk.org>; Sat, 22 Jun 2019 06:25:27 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2t9kuj8654-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 06:25:27 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 22 Jun 2019 06:25:26 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 22 Jun 2019 06:25:26 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 685683F7040;\n\tSat, 22 Jun 2019 06:25:24 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=7IQkoq1UwXw3J83NrWFZ/QWyvC0Kl5bkEKEfhbF5Ass=;\n\tb=nk6E46TJXErQric0FXgr9lFGv+52viieSiuP8hKCZEZw5AxnPh7e1HPq4TfGJxly/4Bo\n\t/5Y62rBfhouys45lsZfheoEN53iPFRWW3BVXktOMKmA+FA/JSAttfZ600A9XQL3ZAGq0\n\t6fi/A+WCYcTcKKDTItPItJDNpWLbtM60gscWSxMsN4+EBHE89WIVqWTH/hyA22q/ze1t\n\tFzURjcnvnUtancTLtqc1qsb+G7kD5JQU3hILAgeG5PkHfaWiOSPgRXbVjWh7NZJidT0i\n\tQuC9oTnQrUVinxZDZV7g1nu+WK7bmDv+cVyeSO/E5WUH8Ceee5Z2e3t50K0nXcKuwKqI\n\tQA== ",
        "From": "<jerinj@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>",
        "Date": "Sat, 22 Jun 2019 18:54:09 +0530",
        "Message-ID": "<20190622132417.32694-20-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>",
        "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v4 19/27] mempool/octeontx2: add NPA IRQ handler",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nRegister and implement NPA IRQ handler for RAS and all type of\nerror interrupts to get the fatal errors from HW.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/mempool/octeontx2/Makefile           |   3 +-\n drivers/mempool/octeontx2/meson.build        |   1 +\n drivers/mempool/octeontx2/otx2_mempool.c     |   6 +\n drivers/mempool/octeontx2/otx2_mempool.h     |   4 +\n drivers/mempool/octeontx2/otx2_mempool_irq.c | 302 +++++++++++++++++++\n 5 files changed, 315 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mempool/octeontx2/otx2_mempool_irq.c",
    "diff": "diff --git a/drivers/mempool/octeontx2/Makefile b/drivers/mempool/octeontx2/Makefile\nindex 6fbb6e291..86950b270 100644\n--- a/drivers/mempool/octeontx2/Makefile\n+++ b/drivers/mempool/octeontx2/Makefile\n@@ -28,7 +28,8 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \\\n-\totx2_mempool.c\n+\totx2_mempool.c \t\t\\\n+\totx2_mempool_irq.c\n \n LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf\n LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci\ndiff --git a/drivers/mempool/octeontx2/meson.build b/drivers/mempool/octeontx2/meson.build\nindex ec3c59eef..3f93b509d 100644\n--- a/drivers/mempool/octeontx2/meson.build\n+++ b/drivers/mempool/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources = files('otx2_mempool.c',\n+\t\t'otx2_mempool_irq.c',\n \t\t)\n \n extra_flags = []\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c\nindex fa74b7532..1bcb86cf4 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool.c\n@@ -195,6 +195,7 @@ otx2_npa_lf_fini(void)\n \t\treturn -ENOMEM;\n \n \tif (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {\n+\t\totx2_npa_unregister_irqs(idev->npa_lf);\n \t\trc |= npa_lf_fini(idev->npa_lf);\n \t\trc |= npa_lf_detach(idev->npa_lf->mbox);\n \t\totx2_npa_set_defaults(idev);\n@@ -251,6 +252,9 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \t\tidev->npa_pf_func = dev->pf_func;\n \t\tidev->npa_lf = lf;\n \t\trte_smp_wmb();\n+\t\trc = otx2_npa_register_irqs(lf);\n+\t\tif (rc)\n+\t\t\tgoto npa_fini;\n \n \t\trte_mbuf_set_platform_mempool_ops(\"octeontx2_npa\");\n \t\totx2_npa_dbg(\"npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x\",\n@@ -259,6 +263,8 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \n \treturn 0;\n \n+npa_fini:\n+\tnpa_lf_fini(idev->npa_lf);\n npa_detach:\n \tnpa_lf_detach(dev->mbox);\n fail:\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h\nindex 871b45870..41542cf89 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.h\n+++ b/drivers/mempool/octeontx2/otx2_mempool.h\n@@ -198,4 +198,8 @@ npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,\n int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n int otx2_npa_lf_fini(void);\n \n+/* IRQ */\n+int otx2_npa_register_irqs(struct otx2_npa_lf *lf);\n+void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);\n+\n #endif /* __OTX2_MEMPOOL_H__ */\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_irq.c b/drivers/mempool/octeontx2/otx2_mempool_irq.c\nnew file mode 100644\nindex 000000000..c026e1eea\n--- /dev/null\n+++ b/drivers/mempool/octeontx2/otx2_mempool_irq.c\n@@ -0,0 +1,302 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_common.h>\n+#include <rte_bus_pci.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_irq.h\"\n+#include \"otx2_mempool.h\"\n+\n+static void\n+npa_lf_err_irq(void *param)\n+{\n+\tstruct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(lf->base + NPA_LF_ERR_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"Err_intr=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, lf->base + NPA_LF_ERR_INT);\n+}\n+\n+static int\n+npa_lf_register_err_irq(struct otx2_npa_lf *lf)\n+{\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n+\t/* Register err interrupt vector */\n+\trc = otx2_register_irq(handle, npa_lf_err_irq, lf, vec);\n+\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_lf_unregister_err_irq(struct otx2_npa_lf *lf)\n+{\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\tint vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, npa_lf_err_irq, lf, vec);\n+}\n+\n+static void\n+npa_lf_ras_irq(void *param)\n+{\n+\tstruct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(lf->base + NPA_LF_RAS);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"Ras_intr=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, lf->base + NPA_LF_RAS);\n+}\n+\n+static int\n+npa_lf_register_ras_irq(struct otx2_npa_lf *lf)\n+{\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, npa_lf_ras_irq, lf, vec);\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_lf_unregister_ras_irq(struct otx2_npa_lf *lf)\n+{\n+\tint vec;\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\n+\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n+\totx2_unregister_irq(handle, npa_lf_ras_irq, lf, vec);\n+}\n+\n+static inline uint8_t\n+npa_lf_q_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t q,\n+\t\t\tuint32_t off, uint64_t mask)\n+{\n+\tuint64_t reg, wdata;\n+\tuint8_t qint;\n+\n+\twdata = (uint64_t)q << 44;\n+\treg = otx2_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\totx2_err(\"Failed execute irq get off=0x%x\", off);\n+\t\treturn 0;\n+\t}\n+\n+\tqint = reg & 0xff;\n+\twdata &= mask;\n+\totx2_write64(wdata, lf->base + off);\n+\n+\treturn qint;\n+}\n+\n+static inline uint8_t\n+npa_lf_pool_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t p)\n+{\n+\treturn npa_lf_q_irq_get_and_clear(lf, p, NPA_LF_POOL_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+npa_lf_aura_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t a)\n+{\n+\treturn npa_lf_q_irq_get_and_clear(lf, a, NPA_LF_AURA_OP_INT, ~0xff00);\n+}\n+\n+static void\n+npa_lf_q_irq(void *param)\n+{\n+\tstruct otx2_npa_qint *qint = (struct otx2_npa_qint *)param;\n+\tstruct otx2_npa_lf *lf = qint->lf;\n+\tuint8_t irq, qintx = qint->qintx;\n+\tuint32_t q, pool, aura;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(lf->base + NPA_LF_QINTX_INT(qintx));\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"queue_intr=0x%\" PRIx64 \" qintx=%d\", intr, qintx);\n+\n+\t/* Handle pool queue interrupts */\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\t\t/* Skip disabled POOL */\n+\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\tpool = q % lf->qints;\n+\t\tirq = npa_lf_pool_irq_get_and_clear(lf, pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS))\n+\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_OVFLS\", pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE))\n+\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_RANGE\", pool);\n+\n+\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR))\n+\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_PERR\", pool);\n+\t}\n+\n+\t/* Handle aura queue interrupts */\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\n+\t\t/* Skip disabled AURA */\n+\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\taura = q % lf->qints;\n+\t\tirq = npa_lf_aura_irq_get_and_clear(lf, aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER))\n+\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_OVER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER))\n+\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_UNDER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER))\n+\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_FREE_UNDER\", aura);\n+\n+\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS))\n+\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_POOL_DIS\", aura);\n+\t}\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx));\n+}\n+\n+static int\n+npa_lf_register_queue_irqs(struct otx2_npa_lf *lf)\n+{\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\tint vec, q, qs, rc = 0;\n+\n+\t/* Figure out max qintx required */\n+\tqs = RTE_MIN(lf->qints, lf->nr_pools);\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n+\n+\t\tstruct otx2_npa_qint *qintmem = lf->npa_qint_mem;\n+\t\tqintmem += q;\n+\n+\t\tqintmem->lf = lf;\n+\t\tqintmem->qintx = q;\n+\n+\t\t/* Sync qints_mem update */\n+\t\trte_smp_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = otx2_register_irq(handle, npa_lf_q_irq, qintmem, vec);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\n+\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\t\totx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n+\t\t/* Enable QINT interrupt */\n+\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1S(q));\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static void\n+npa_lf_unregister_queue_irqs(struct otx2_npa_lf *lf)\n+{\n+\tstruct rte_intr_handle *handle = lf->intr_handle;\n+\tint vec, q, qs;\n+\n+\t/* Figure out max qintx required */\n+\tqs = RTE_MIN(lf->qints, lf->nr_pools);\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n+\t\totx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n+\n+\t\tstruct otx2_npa_qint *qintmem = lf->npa_qint_mem;\n+\t\tqintmem += q;\n+\n+\t\t/* Unregister queue irq vector */\n+\t\totx2_unregister_irq(handle, npa_lf_q_irq, qintmem, vec);\n+\n+\t\tqintmem->lf = NULL;\n+\t\tqintmem->qintx = 0;\n+\t}\n+}\n+\n+int\n+otx2_npa_register_irqs(struct otx2_npa_lf *lf)\n+{\n+\tint rc;\n+\n+\tif (lf->npa_msixoff == MSIX_VECTOR_INVALID) {\n+\t\totx2_err(\"Invalid NPALF MSIX vector offset vector: 0x%x\",\n+\t\t\tlf->npa_msixoff);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Register lf err interrupt */\n+\trc = npa_lf_register_err_irq(lf);\n+\t/* Register RAS interrupt */\n+\trc |= npa_lf_register_ras_irq(lf);\n+\t/* Register queue interrupts */\n+\trc |= npa_lf_register_queue_irqs(lf);\n+\n+\treturn rc;\n+}\n+\n+void\n+otx2_npa_unregister_irqs(struct otx2_npa_lf *lf)\n+{\n+\tnpa_lf_unregister_err_irq(lf);\n+\tnpa_lf_unregister_ras_irq(lf);\n+\tnpa_lf_unregister_queue_irqs(lf);\n+}\n",
    "prefixes": [
        "v4",
        "19/27"
    ]
}