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GET /api/patches/55195/?format=api
{ "id": 55195, "url": "http://patches.dpdk.org/api/patches/55195/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-7-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190622132417.32694-7-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-7-jerinj@marvell.com", "date": "2019-06-22T13:23:56", "name": "[v4,06/27] common/octeontx2: add mailbox send and receive support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9841fc8283fe92575b6de1156e5b706ee1f83745", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-7-jerinj@marvell.com/mbox/", "series": [ { "id": 5124, "url": "http://patches.dpdk.org/api/series/5124/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5124", "date": "2019-06-22T13:23:50", "name": "OCTEON TX2 common and mempool driver", "version": 4, "mbox": "http://patches.dpdk.org/series/5124/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55195/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55195/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2DBE21C5D4;\n\tSat, 22 Jun 2019 15:25:04 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 409F41C58C\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 15:24:49 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5MDL4gu027550 for <dev@dpdk.org>; Sat, 22 Jun 2019 06:24:48 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2t9kuj862s-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 06:24:48 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 22 Jun 2019 06:24:47 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 22 Jun 2019 06:24:47 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 8D3AC3F703F;\n\tSat, 22 Jun 2019 06:24:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=Au6GFLJhpxIgyGi9w4rpPJmD7jTVCGY7BqkbYi+rhOk=;\n\tb=rXiz5Cm9XJEgdtL2UupY3C8e2bywO0JcqAz8cuB9p5moT7gpA+s8/daDe3u3sooDPCea\n\tc/XYC7LSNXGXYgHFla/gQ7szlJArHMADE1wPYyr8SduWCOb5/QlP0gip8e1xDu8z4ORK\n\tRAktSN/KzoCBZpFJDKJgCwmKZW2SScLn0p9LvxH3+qRA+g4GR0n7YzB1WJEBfwg5CcDO\n\tZowJaSsCbi0sVjIOqVIokRL4DcRA7iFy5AGAlD6xy/pbkptdYRSvyDfYshWnJYrovbwK\n\tEAAN9NZIBNSmKANST7jF6OkCEEIApu4rVPCOsr+oQHVP6qQlmyxFMvCLYguER3aHJUNX\n\tQA== ", "From": "<jerinj@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sat, 22 Jun 2019 18:53:56 +0530", "Message-ID": "<20190622132417.32694-7-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>", "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v4 06/27] common/octeontx2: add mailbox send and\n\treceive support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nEach RVU device has a dedicated 64KB mailbox region\nshared with its peer for communication. RVU AF has\na separate mailbox region shared with each of RVU PFs\nand an RVU PF has a separate region shared with each of\nit's VF.\n\nThis patch add use 64KB memory and implemented mailbox\nsend and receive support.\n\nThese set of APIs are used by this driver (RVU AF) and\nother RVU PF/VF drivers eg ethdev, cryptodev e.t.c.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/octeontx2/otx2_mbox.c | 278 ++++++++++++++++++\n drivers/common/octeontx2/otx2_mbox.h | 142 +++++++++\n .../rte_common_octeontx2_version.map | 7 +\n 3 files changed, 427 insertions(+)", "diff": "diff --git a/drivers/common/octeontx2/otx2_mbox.c b/drivers/common/octeontx2/otx2_mbox.c\nindex cb03f6503..86559fa98 100644\n--- a/drivers/common/octeontx2/otx2_mbox.c\n+++ b/drivers/common/octeontx2/otx2_mbox.c\n@@ -24,6 +24,12 @@\n #define\tRVU_VF_VFPF_MBOX0\t(0x0000)\n #define\tRVU_VF_VFPF_MBOX1\t(0x0008)\n \n+static inline uint16_t\n+msgs_offset(void)\n+{\n+\treturn RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+}\n+\n void\n otx2_mbox_fini(struct otx2_mbox *mbox)\n {\n@@ -136,3 +142,275 @@ otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,\n \n \treturn 0;\n }\n+\n+/**\n+ * @internal\n+ * Allocate a message response\n+ */\n+struct mbox_msghdr *\n+otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, int size,\n+\t\t\tint size_rsp)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr = NULL;\n+\n+\trte_spinlock_lock(&mdev->mbox_lock);\n+\tsize = RTE_ALIGN(size, MBOX_MSG_ALIGN);\n+\tsize_rsp = RTE_ALIGN(size_rsp, MBOX_MSG_ALIGN);\n+\t/* Check if there is space in mailbox */\n+\tif ((mdev->msg_size + size) > mbox->tx_size - msgs_offset())\n+\t\tgoto exit;\n+\tif ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset())\n+\t\tgoto exit;\n+\tif (mdev->msg_size == 0)\n+\t\tmdev->num_msgs = 0;\n+\tmdev->num_msgs++;\n+\n+\tmsghdr = (struct mbox_msghdr *)(((uintptr_t)mdev->mbase +\n+\t\t\tmbox->tx_start + msgs_offset() + mdev->msg_size));\n+\n+\t/* Clear the whole msg region */\n+\totx2_mbox_memset(msghdr, 0, sizeof(*msghdr) + size);\n+\t/* Init message header with reset values */\n+\tmsghdr->ver = OTX2_MBOX_VERSION;\n+\tmdev->msg_size += size;\n+\tmdev->rsp_size += size_rsp;\n+\tmsghdr->next_msgoff = mdev->msg_size + msgs_offset();\n+exit:\n+\trte_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn msghdr;\n+}\n+\n+/**\n+ * @internal\n+ * Send a mailbox message\n+ */\n+void\n+otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_hdr *tx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n+\tstruct mbox_hdr *rx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\n+\t/* Reset header for next messages */\n+\ttx_hdr->msg_size = mdev->msg_size;\n+\tmdev->msg_size = 0;\n+\tmdev->rsp_size = 0;\n+\tmdev->msgs_acked = 0;\n+\n+\t/* num_msgs != 0 signals to the peer that the buffer has a number of\n+\t * messages. So this should be written after copying txmem\n+\t */\n+\ttx_hdr->num_msgs = mdev->num_msgs;\n+\trx_hdr->num_msgs = 0;\n+\n+\t/* Sync mbox data into memory */\n+\trte_wmb();\n+\n+\t/* The interrupt should be fired after num_msgs is written\n+\t * to the shared memory\n+\t */\n+\trte_write64(1, (volatile void *)(mbox->reg_base +\n+\t\t(mbox->trigger | (devid << mbox->tr_shift))));\n+}\n+\n+/**\n+ * @internal\n+ * Wait and get mailbox response\n+ */\n+int\n+otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr;\n+\tuint64_t offset;\n+\tint rc;\n+\n+\trc = otx2_mbox_wait_for_rsp(mbox, devid);\n+\tif (rc != 1)\n+\t\treturn -EIO;\n+\n+\trte_rmb();\n+\n+\toffset = mbox->rx_start +\n+\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\tif (msg != NULL)\n+\t\t*msg = msghdr;\n+\n+\treturn msghdr->rc;\n+}\n+\n+/**\n+ * @internal\n+ * Wait and get mailbox response with timeout\n+ */\n+int\n+otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,\n+\t\t uint32_t tmo)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_msghdr *msghdr;\n+\tuint64_t offset;\n+\tint rc;\n+\n+\trc = otx2_mbox_wait_for_rsp_tmo(mbox, devid, tmo);\n+\tif (rc != 1)\n+\t\treturn -EIO;\n+\n+\trte_rmb();\n+\n+\toffset = mbox->rx_start +\n+\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\tif (msg != NULL)\n+\t\t*msg = msghdr;\n+\n+\treturn msghdr->rc;\n+}\n+\n+static int\n+mbox_wait(struct otx2_mbox *mbox, int devid, uint32_t rst_timo)\n+{\n+\tvolatile struct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tuint32_t timeout = 0, sleep = 1;\n+\n+\twhile (mdev->num_msgs > mdev->msgs_acked) {\n+\t\trte_delay_ms(sleep);\n+\t\ttimeout += sleep;\n+\t\tif (timeout >= rst_timo) {\n+\t\t\tstruct mbox_hdr *tx_hdr =\n+\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n+\t\t\t\t\t\t\tmbox->tx_start);\n+\t\t\tstruct mbox_hdr *rx_hdr =\n+\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n+\t\t\t\t\t\t\tmbox->rx_start);\n+\n+\t\t\totx2_err(\"MBOX[devid: %d] message wait timeout %d, \"\n+\t\t\t\t \"num_msgs: %d, msgs_acked: %d \"\n+\t\t\t\t \"(tx/rx num_msgs: %d/%d), msg_size: %d, \"\n+\t\t\t\t \"rsp_size: %d\",\n+\t\t\t\t devid, timeout, mdev->num_msgs,\n+\t\t\t\t mdev->msgs_acked, tx_hdr->num_msgs,\n+\t\t\t\t rx_hdr->num_msgs, mdev->msg_size,\n+\t\t\t\t mdev->rsp_size);\n+\n+\t\t\treturn -EIO;\n+\t\t}\n+\t\trte_rmb();\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tint rc = 0;\n+\n+\t/* Sync with mbox region */\n+\trte_rmb();\n+\n+\tif (mbox->trigger == RVU_PF_VFX_PFVF_MBOX1 ||\n+\t\tmbox->trigger == RVU_PF_VFX_PFVF_MBOX0) {\n+\t\t/* In case of VF, Wait a bit more to account round trip delay */\n+\t\ttmo = tmo * 2;\n+\t}\n+\n+\t/* Wait message */\n+\trc = mbox_wait(mbox, devid, tmo);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn mdev->msgs_acked;\n+}\n+\n+/**\n+ * @internal\n+ * Wait for the mailbox response\n+ */\n+int\n+otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid)\n+{\n+\treturn otx2_mbox_wait_for_rsp_tmo(mbox, devid, MBOX_RSP_TIMEOUT);\n+}\n+\n+int\n+otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tint avail;\n+\n+\trte_spinlock_lock(&mdev->mbox_lock);\n+\tavail = mbox->tx_size - mdev->msg_size - msgs_offset();\n+\trte_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn avail;\n+}\n+\n+int\n+otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pcifunc)\n+{\n+\tstruct ready_msg_rsp *rsp;\n+\tint rc;\n+\n+\totx2_mbox_alloc_msg_ready(mbox);\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (pcifunc)\n+\t\t*pcifunc = rsp->hdr.pcifunc;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pcifunc,\n+\t\t uint16_t id)\n+{\n+\tstruct msg_rsp *rsp;\n+\n+\trsp = (struct msg_rsp *)otx2_mbox_alloc_msg(mbox, devid, sizeof(*rsp));\n+\tif (!rsp)\n+\t\treturn -ENOMEM;\n+\trsp->hdr.id = id;\n+\trsp->hdr.sig = OTX2_MBOX_RSP_SIG;\n+\trsp->hdr.rc = MBOX_MSG_INVALID;\n+\trsp->hdr.pcifunc = pcifunc;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * @internal\n+ * Convert mail box ID to name\n+ */\n+const char *otx2_mbox_id2name(uint16_t id)\n+{\n+\tswitch (id) {\n+#define M(_name, _id, _1, _2, _3) case _id: return # _name;\n+\tMBOX_MESSAGES\n+\tMBOX_UP_CGX_MESSAGES\n+#undef M\n+\tdefault :\n+\t\treturn \"INVALID ID\";\n+\t}\n+}\n+\n+int otx2_mbox_id2size(uint16_t id)\n+{\n+\tswitch (id) {\n+#define M(_1, _id, _2, _req_type, _3) case _id: return sizeof(struct _req_type);\n+\tMBOX_MESSAGES\n+\tMBOX_UP_CGX_MESSAGES\n+#undef M\n+\tdefault :\n+\t\treturn 0;\n+\t}\n+}\ndiff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex c6c899661..c0bb676b2 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -1411,9 +1411,151 @@ struct tim_enable_rsp {\n \tuint32_t __otx2_io currentbucket;\n };\n \n+const char *otx2_mbox_id2name(uint16_t id);\n+int otx2_mbox_id2size(uint16_t id);\n void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);\n int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,\n \t\t uintptr_t reg_base, int direction, int ndevs);\n void otx2_mbox_fini(struct otx2_mbox *mbox);\n+void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);\n+int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);\n+int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);\n+int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);\n+int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,\n+\t\t\t uint32_t tmo);\n+int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);\n+struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,\n+\t\t\t\t\t int size, int size_rsp);\n+\n+static inline struct mbox_msghdr *\n+otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)\n+{\n+\treturn otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);\n+}\n+\n+static inline void\n+otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)\n+{\n+\tstruct mbox_msghdr *hdr = msghdr;\n+\n+\thdr->sig = OTX2_MBOX_REQ_SIG;\n+\thdr->ver = OTX2_MBOX_VERSION;\n+\thdr->id = mbox_id;\n+\thdr->pcifunc = 0;\n+}\n+\n+static inline void\n+otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)\n+{\n+\tstruct mbox_msghdr *hdr = msghdr;\n+\n+\thdr->sig = OTX2_MBOX_RSP_SIG;\n+\thdr->rc = -ETIMEDOUT;\n+\thdr->id = mbox_id;\n+}\n+\n+static inline bool\n+otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tbool ret;\n+\n+\trte_spinlock_lock(&mdev->mbox_lock);\n+\tret = mdev->num_msgs != 0;\n+\trte_spinlock_unlock(&mdev->mbox_lock);\n+\n+\treturn ret;\n+}\n+\n+static inline int\n+otx2_mbox_process(struct otx2_mbox *mbox)\n+{\n+\totx2_mbox_msg_send(mbox, 0);\n+\treturn otx2_mbox_get_rsp(mbox, 0, NULL);\n+}\n+\n+static inline int\n+otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)\n+{\n+\totx2_mbox_msg_send(mbox, 0);\n+\treturn otx2_mbox_get_rsp(mbox, 0, msg);\n+}\n+\n+static inline int\n+otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)\n+{\n+\totx2_mbox_msg_send(mbox, 0);\n+\treturn otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);\n+}\n+\n+static inline int\n+otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)\n+{\n+\totx2_mbox_msg_send(mbox, 0);\n+\treturn otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);\n+}\n+\n+int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);\n+int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,\n+\t\t\tuint16_t id);\n+\n+#define M(_name, _id, _fn_name, _req_type, _rsp_type)\t\t\t\\\n+static inline struct _req_type\t\t\t\t\t\t\\\n+*otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tstruct _req_type *req;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\treq = (struct _req_type *)otx2_mbox_alloc_msg_rsp(\t\t\\\n+\t\tmbox, 0, sizeof(struct _req_type),\t\t\t\\\n+\t\tsizeof(struct _rsp_type));\t\t\t\t\\\n+\tif (!req)\t\t\t\t\t\t\t\\\n+\t\treturn NULL;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\t\t\t\t\\\n+\treq->hdr.id = _id;\t\t\t\t\t\t\\\n+\totx2_mbox_dbg(\"id=0x%x (%s)\",\t\t\t\t\t\\\n+\t\t\treq->hdr.id, otx2_mbox_id2name(req->hdr.id));\t\\\n+\treturn req;\t\t\t\t\t\t\t\\\n+}\n+\n+MBOX_MESSAGES\n+#undef M\n+\n+/* This is required for copy operations from device memory which do not work on\n+ * addresses which are unaligned to 16B. This is because of specific\n+ * optimizations to libc memcpy.\n+ */\n+static inline volatile void *\n+otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)\n+{\n+\tconst volatile uint8_t *sb;\n+\tvolatile uint8_t *db;\n+\tsize_t i;\n+\n+\tif (!d || !s)\n+\t\treturn NULL;\n+\tdb = (volatile uint8_t *)d;\n+\tsb = (const volatile uint8_t *)s;\n+\tfor (i = 0; i < l; i++)\n+\t\tdb[i] = sb[i];\n+\treturn d;\n+}\n+\n+/* This is required for memory operations from device memory which do not\n+ * work on addresses which are unaligned to 16B. This is because of specific\n+ * optimizations to libc memset.\n+ */\n+static inline void\n+otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)\n+{\n+\tvolatile uint8_t *db;\n+\tsize_t i = 0;\n+\n+\tif (!d || !l)\n+\t\treturn;\n+\tdb = (volatile uint8_t *)d;\n+\tfor (i = 0; i < l; i++)\n+\t\tdb[i] = val;\n+}\n \n #endif /* __OTX2_MBOX_H__ */\ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex 02f03e177..e10a2d3b2 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -11,5 +11,12 @@ DPDK_19.08 {\n \totx2_logtype_tm;\n \totx2_logtype_tim;\n \n+\totx2_mbox_alloc_msg_rsp;\n+\totx2_mbox_get_rsp;\n+\totx2_mbox_get_rsp_tmo;\n+\totx2_mbox_id2name;\n+\totx2_mbox_msg_send;\n+\totx2_mbox_wait_for_rsp;\n+\n \tlocal: *;\n };\n", "prefixes": [ "v4", "06/27" ] }