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{
    "id": 55193,
    "url": "http://patches.dpdk.org/api/patches/55193/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-4-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190622132417.32694-4-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-4-jerinj@marvell.com",
    "date": "2019-06-22T13:23:53",
    "name": "[v4,03/27] common/octeontx2: add mbox request and response definition",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b30252d2a7db4d940f37a990c687600197369870",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-4-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5124,
            "url": "http://patches.dpdk.org/api/series/5124/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5124",
            "date": "2019-06-22T13:23:50",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/5124/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55193/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55193/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id BAE123F703F;\n\tSat, 22 Jun 2019 06:24:34 -0700 (PDT)"
        ],
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        "From": "<jerinj@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>, Vivek Sharma <viveksharma@marvell.com>,\n\t\"Harman\n\tKalra\" <hkalra@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n\t\"Krzysztof Kanas\" <kkanas@marvell.com>, Zyta Szpak <zyta@marvell.com>",
        "Date": "Sat, 22 Jun 2019 18:53:53 +0530",
        "Message-ID": "<20190622132417.32694-4-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>",
        "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v4 03/27] common/octeontx2: add mbox request and\n\tresponse definition",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe admin function driver sits in Linux kernel as mailbox\nserver. The DPDK AF mailbox client, send the message to mailbox\nserver to complete the administrative task such as get mac\naddress.\n\nThis patch adds mailbox request and response definition of\nexisting mailbox defined between AF driver and DPDK driver.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Vivek Sharma <viveksharma@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\nSigned-off-by: Zyta Szpak <zyta@marvell.com>\n---\n drivers/common/octeontx2/otx2_mbox.h | 1404 ++++++++++++++++++++++++++\n 1 file changed, 1404 insertions(+)",
    "diff": "diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex 6d7b77ed9..47bd91a97 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -5,6 +5,1410 @@\n #ifndef __OTX2_MBOX_H__\n #define __OTX2_MBOX_H__\n \n+#include <errno.h>\n+#include <stdbool.h>\n+\n+#include <rte_ether.h>\n+#include <rte_spinlock.h>\n+\n #include <otx2_common.h>\n \n+#define SZ_64K\t\t\t(64 * 1024)\n+#define SZ_1K\t\t\t(1 * 1024)\n+#define MBOX_SIZE\t\tSZ_64K\n+\n+/* AF/PF: PF initiated, PF/VF VF initiated */\n+#define MBOX_DOWN_RX_START\t0\n+#define MBOX_DOWN_RX_SIZE\t(46 * SZ_1K)\n+#define MBOX_DOWN_TX_START\t(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)\n+#define MBOX_DOWN_TX_SIZE\t(16 * SZ_1K)\n+/* AF/PF: AF initiated, PF/VF PF initiated */\n+#define MBOX_UP_RX_START\t(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)\n+#define MBOX_UP_RX_SIZE\t\tSZ_1K\n+#define MBOX_UP_TX_START\t(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)\n+#define MBOX_UP_TX_SIZE\t\tSZ_1K\n+\n+#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE\n+# error \"Incorrect mailbox area sizes\"\n+#endif\n+\n+#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))\n+\n+#define MBOX_RSP_TIMEOUT\t3000 /* Time to wait for mbox response in ms */\n+\n+#define MBOX_MSG_ALIGN\t\t16  /* Align mbox msg start to 16bytes */\n+\n+/* Mailbox directions */\n+#define MBOX_DIR_AFPF\t\t0  /* AF replies to PF */\n+#define MBOX_DIR_PFAF\t\t1  /* PF sends messages to AF */\n+#define MBOX_DIR_PFVF\t\t2  /* PF replies to VF */\n+#define MBOX_DIR_VFPF\t\t3  /* VF sends messages to PF */\n+#define MBOX_DIR_AFPF_UP\t4  /* AF sends messages to PF */\n+#define MBOX_DIR_PFAF_UP\t5  /* PF replies to AF */\n+#define MBOX_DIR_PFVF_UP\t6  /* PF sends messages to VF */\n+#define MBOX_DIR_VFPF_UP\t7  /* VF replies to PF */\n+\n+/* Device memory does not support unaligned access, instruct compiler to\n+ * not optimize the memory access when working with mailbox memory.\n+ */\n+#define __otx2_io volatile\n+\n+struct otx2_mbox_dev {\n+\tvoid\t    *mbase;   /* This dev's mbox region */\n+\trte_spinlock_t  mbox_lock;\n+\tuint16_t     msg_size; /* Total msg size to be sent */\n+\tuint16_t     rsp_size; /* Total rsp size to be sure the reply is ok */\n+\tuint16_t     num_msgs; /* No of msgs sent or waiting for response */\n+\tuint16_t     msgs_acked; /* No of msgs for which response is received */\n+};\n+\n+struct otx2_mbox {\n+\tuintptr_t hwbase;  /* Mbox region advertised by HW */\n+\tuintptr_t reg_base;/* CSR base for this dev */\n+\tuint64_t trigger;  /* Trigger mbox notification */\n+\tuint16_t tr_shift; /* Mbox trigger shift */\n+\tuint64_t rx_start; /* Offset of Rx region in mbox memory */\n+\tuint64_t tx_start; /* Offset of Tx region in mbox memory */\n+\tuint16_t rx_size;  /* Size of Rx region */\n+\tuint16_t tx_size;  /* Size of Tx region */\n+\tuint16_t ndevs;    /* The number of peers */\n+\tstruct otx2_mbox_dev *dev;\n+};\n+\n+/* Header which precedes all mbox messages */\n+struct mbox_hdr {\n+\tuint64_t __otx2_io msg_size;   /* Total msgs size embedded */\n+\tuint16_t __otx2_io num_msgs;   /* No of msgs embedded */\n+};\n+\n+/* Header which precedes every msg and is also part of it */\n+struct mbox_msghdr {\n+\tuint16_t __otx2_io pcifunc; /* Who's sending this msg */\n+\tuint16_t __otx2_io id;      /* Mbox message ID */\n+#define OTX2_MBOX_REQ_SIG (0xdead)\n+#define OTX2_MBOX_RSP_SIG (0xbeef)\n+\t/* Signature, for validating corrupted msgs */\n+\tuint16_t __otx2_io sig;\n+#define OTX2_MBOX_VERSION (0x0001)\n+\t/* Version of msg's structure for this ID */\n+\tuint16_t __otx2_io ver;\n+\t/* Offset of next msg within mailbox region */\n+\tuint16_t __otx2_io next_msgoff;\n+\tint __otx2_io rc; /* Msg processed response code */\n+};\n+\n+/* Mailbox message types */\n+#define MBOX_MSG_MASK\t\t\t\t0xFFFF\n+#define MBOX_MSG_INVALID\t\t\t0xFFFE\n+#define MBOX_MSG_MAX\t\t\t\t0xFFFF\n+\n+#define MBOX_MESSAGES\t\t\t\t\t\t\t\\\n+/* Generic mbox IDs (range 0x000 - 0x1FF) */\t\t\t\t\\\n+M(READY,\t\t0x001, ready, msg_req, ready_msg_rsp)\t\t\\\n+M(ATTACH_RESOURCES,\t0x002, attach_resources, rsrc_attach_req, msg_rsp)\\\n+M(DETACH_RESOURCES,\t0x003, detach_resources, rsrc_detach_req, msg_rsp)\\\n+M(FREE_RSRC_CNT,\t0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)\t\\\n+M(MSIX_OFFSET,\t\t0x005, msix_offset, msg_req, msix_offset_rsp)\t\\\n+M(VF_FLR,\t\t0x006, vf_flr, msg_req, msg_rsp)\t\t\\\n+M(PTP_OP,\t\t0x007, ptp_op, ptp_req, ptp_rsp)\t\t\\\n+M(GET_HW_CAP,\t\t0x008, get_hw_cap, msg_req, get_hw_cap_rsp)\t\\\n+M(NDC_SYNC_OP,\t\t0x009, ndc_sync_op, ndc_sync_op, msg_rsp)\t\\\n+/* CGX mbox IDs (range 0x200 - 0x3FF) */\t\t\t\t\\\n+M(CGX_START_RXTX,\t0x200, cgx_start_rxtx, msg_req, msg_rsp)\t\\\n+M(CGX_STOP_RXTX,\t0x201, cgx_stop_rxtx, msg_req, msg_rsp)\t\t\\\n+M(CGX_STATS,\t\t0x202, cgx_stats, msg_req, cgx_stats_rsp)\t\\\n+M(CGX_MAC_ADDR_SET,\t0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\\\n+\t\t\t\tcgx_mac_addr_set_or_get)\t\t\\\n+M(CGX_MAC_ADDR_GET,\t0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\\\n+\t\t\t\tcgx_mac_addr_set_or_get)\t\t\\\n+M(CGX_PROMISC_ENABLE,\t0x205, cgx_promisc_enable, msg_req, msg_rsp)\t\\\n+M(CGX_PROMISC_DISABLE,\t0x206, cgx_promisc_disable, msg_req, msg_rsp)\t\\\n+M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)\t\\\n+M(CGX_STOP_LINKEVENTS,\t0x208, cgx_stop_linkevents, msg_req, msg_rsp)\t\\\n+M(CGX_GET_LINKINFO,\t0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\\\n+M(CGX_INTLBK_ENABLE,\t0x20A, cgx_intlbk_enable, msg_req, msg_rsp)\t\\\n+M(CGX_INTLBK_DISABLE,\t0x20B, cgx_intlbk_disable, msg_req, msg_rsp)\t\\\n+M(CGX_PTP_RX_ENABLE,\t0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)\t\\\n+M(CGX_PTP_RX_DISABLE,\t0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)\t\\\n+M(CGX_CFG_PAUSE_FRM,\t0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,\t\\\n+\t\t\t\tcgx_pause_frm_cfg)\t\t\t\\\n+M(CGX_FW_DATA_GET,\t0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \\\n+M(CGX_MAC_ADDR_ADD,     0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,\t\\\n+\t\t\t\tcgx_mac_addr_add_rsp)\t\t\t\\\n+M(CGX_MAC_ADDR_DEL,     0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,\t\\\n+\t\t\t\t cgx_max_dmac_entries_get_rsp)\t\t\\\n+M(CGX_SET_LINK_STATE,\t0x214, cgx_set_link_state,\t\t\\\n+\t\t\tcgx_set_link_state_msg, msg_rsp)\t\t\\\n+/* NPA mbox IDs (range 0x400 - 0x5FF) */\t\t\t\t\\\n+M(NPA_LF_ALLOC,\t\t0x400, npa_lf_alloc, npa_lf_alloc_req,\t\t\\\n+\t\t\t\tnpa_lf_alloc_rsp)\t\t\t\\\n+M(NPA_LF_FREE,\t\t0x401, npa_lf_free, msg_req, msg_rsp)\t\t\\\n+M(NPA_AQ_ENQ,\t\t0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\\\n+M(NPA_HWCTX_DISABLE,\t0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\\\n+/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */\t\t\t\t\\\n+M(SSO_LF_ALLOC,\t\t0x600, sso_lf_alloc, sso_lf_alloc_req,\t\t\\\n+\t\t\t\tsso_lf_alloc_rsp)\t\t\t\\\n+M(SSO_LF_FREE,\t\t0x601, sso_lf_free, sso_lf_free_req, msg_rsp)\t\\\n+M(SSOW_LF_ALLOC,\t0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\\\n+M(SSOW_LF_FREE,\t\t0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp)\t\\\n+M(SSO_HW_SETCONFIG,\t0x604, sso_hw_setconfig, sso_hw_setconfig,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(SSO_GRP_SET_PRIORITY,\t0x605, sso_grp_set_priority, sso_grp_priority,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(SSO_GRP_GET_PRIORITY,\t0x606, sso_grp_get_priority, sso_info_req,\t\\\n+\t\t\t\tsso_grp_priority)\t\t\t\\\n+M(SSO_WS_CACHE_INV,\t0x607, sso_ws_cache_inv, msg_req, msg_rsp)\t\\\n+M(SSO_GRP_QOS_CONFIG,\t0x608, sso_grp_qos_config, sso_grp_qos_cfg,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(SSO_GRP_GET_STATS,\t0x609, sso_grp_get_stats, sso_info_req,\t\t\\\n+\t\t\t\tsso_grp_stats)\t\t\t\t\\\n+M(SSO_HWS_GET_STATS,\t0x610, sso_hws_get_stats, sso_info_req,\t\t\\\n+\t\t\t\tsso_hws_stats)\t\t\t\t\\\n+/* TIM mbox IDs (range 0x800 - 0x9FF) */\t\t\t\t\\\n+M(TIM_LF_ALLOC,\t\t0x800, tim_lf_alloc, tim_lf_alloc_req,\t\t\\\n+\t\t\t\ttim_lf_alloc_rsp)\t\t\t\\\n+M(TIM_LF_FREE,\t\t0x801, tim_lf_free, tim_ring_req, msg_rsp)\t\\\n+M(TIM_CONFIG_RING,\t0x802, tim_config_ring, tim_config_req, msg_rsp)\\\n+M(TIM_ENABLE_RING,\t0x803, tim_enable_ring, tim_ring_req,\t\t\\\n+\t\t\t\ttim_enable_rsp)\t\t\t\t\\\n+M(TIM_DISABLE_RING,\t0x804, tim_disable_ring, tim_ring_req, msg_rsp)\t\\\n+/* CPT mbox IDs (range 0xA00 - 0xBFF) */\t\t\t\t\\\n+M(CPT_RD_WR_REGISTER,\t0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg,\t\\\n+\t\t\t       cpt_rd_wr_reg_msg)\t\t\t\\\n+M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,\t\t\t\\\n+\t\t\t       cpt_inline_ipsec_cfg_msg, msg_rsp)\t\\\n+/* NPC mbox IDs (range 0x6000 - 0x7FFF) */\t\t\t\t\\\n+M(NPC_MCAM_ALLOC_ENTRY,\t0x6000, npc_mcam_alloc_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_alloc_entry_req,\t\t\\\n+\t\t\t\tnpc_mcam_alloc_entry_rsp)\t\t\\\n+M(NPC_MCAM_FREE_ENTRY,\t0x6001, npc_mcam_free_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_free_entry_req, msg_rsp)\t\\\n+M(NPC_MCAM_WRITE_ENTRY,\t0x6002, npc_mcam_write_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_write_entry_req, msg_rsp)\t\\\n+M(NPC_MCAM_ENA_ENTRY,\t0x6003, npc_mcam_ena_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_ena_dis_entry_req, msg_rsp)\t\\\n+M(NPC_MCAM_DIS_ENTRY,\t0x6004, npc_mcam_dis_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_ena_dis_entry_req, msg_rsp)\t\\\n+M(NPC_MCAM_SHIFT_ENTRY,\t0x6005, npc_mcam_shift_entry,\t\t\t\\\n+\t\t\t\tnpc_mcam_shift_entry_req,\t\t\\\n+\t\t\t\tnpc_mcam_shift_entry_rsp)\t\t\\\n+M(NPC_MCAM_ALLOC_COUNTER,\t0x6006, npc_mcam_alloc_counter,\t\t\\\n+\t\t\t\tnpc_mcam_alloc_counter_req,\t\t\\\n+\t\t\t\tnpc_mcam_alloc_counter_rsp)\t\t\\\n+M(NPC_MCAM_FREE_COUNTER,\t0x6007, npc_mcam_free_counter,\t\t\\\n+\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NPC_MCAM_UNMAP_COUNTER,\t0x6008, npc_mcam_unmap_counter,\t\t\\\n+\t\t\t\tnpc_mcam_unmap_counter_req,\t\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NPC_MCAM_CLEAR_COUNTER,\t0x6009, npc_mcam_clear_counter,\t\t\\\n+\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NPC_MCAM_COUNTER_STATS,\t0x600a, npc_mcam_counter_stats,\t\t\\\n+\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n+\t\t\t\tnpc_mcam_oper_counter_rsp)\t\t\\\n+M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\\\n+\t\t\t\tnpc_mcam_alloc_and_write_entry_req,\t\\\n+\t\t\t\tnpc_mcam_alloc_and_write_entry_rsp)\t\\\n+M(NPC_GET_KEX_CFG,\t  0x600c, npc_get_kex_cfg, msg_req,\t\t\\\n+\t\t\t\tnpc_get_kex_cfg_rsp)\t\t\t\\\n+M(NPC_INSTALL_FLOW,\t  0x600d, npc_install_flow,\t\t\t\\\n+\t\t\t\t  npc_install_flow_req,\t\t\t\\\n+\t\t\t\t  npc_install_flow_rsp)\t\t\t\\\n+M(NPC_DELETE_FLOW,\t  0x600e, npc_delete_flow,\t\t\t\\\n+\t\t\t\t  npc_delete_flow_req, msg_rsp)\t\t\\\n+M(NPC_MCAM_READ_ENTRY,\t  0x600f, npc_mcam_read_entry,\t\t\t\\\n+\t\t\t\t  npc_mcam_read_entry_req,\t\t\\\n+\t\t\t\t  npc_mcam_read_entry_rsp)\t\t\\\n+/* NIX mbox IDs (range 0x8000 - 0xFFFF) */\t\t\t\t\\\n+M(NIX_LF_ALLOC,\t\t0x8000, nix_lf_alloc, nix_lf_alloc_req,\t\t\\\n+\t\t\t\tnix_lf_alloc_rsp)\t\t\t\\\n+M(NIX_LF_FREE,\t\t0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)\t\\\n+M(NIX_AQ_ENQ,\t\t0x8002, nix_aq_enq, nix_aq_enq_req,\t\t\\\n+\t\t\t\tnix_aq_enq_rsp)\t\t\t\t\\\n+M(NIX_HWCTX_DISABLE,\t0x8003, nix_hwctx_disable, hwctx_disable_req,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_TXSCH_ALLOC,\t0x8004, nix_txsch_alloc, nix_txsch_alloc_req,\t\\\n+\t\t\t\tnix_txsch_alloc_rsp)\t\t\t\\\n+M(NIX_TXSCH_FREE,\t0x8005, nix_txsch_free,\tnix_txsch_free_req,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_TXSCHQ_CFG,\t0x8006, nix_txschq_cfg, nix_txschq_config,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_STATS_RST,\t0x8007, nix_stats_rst, msg_req, msg_rsp)\t\\\n+M(NIX_VTAG_CFG,\t\t0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp)\t\\\n+M(NIX_RSS_FLOWKEY_CFG,\t0x8009, nix_rss_flowkey_cfg,\t\t\t\\\n+\t\t\t\tnix_rss_flowkey_cfg,\t\t\t\\\n+\t\t\t\tnix_rss_flowkey_cfg_rsp)\t\t\\\n+M(NIX_SET_MAC_ADDR,\t0x800a, nix_set_mac_addr, nix_set_mac_addr,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_SET_RX_MODE,\t0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)\t\\\n+M(NIX_SET_HW_FRS,\t0x800c, nix_set_hw_frs,\tnix_frs_cfg, msg_rsp)\t\\\n+M(NIX_LF_START_RX,\t0x800d, nix_lf_start_rx, msg_req, msg_rsp)\t\\\n+M(NIX_LF_STOP_RX,\t0x800e, nix_lf_stop_rx,\tmsg_req, msg_rsp)\t\\\n+M(NIX_MARK_FORMAT_CFG,\t0x800f, nix_mark_format_cfg,\t\t\t\\\n+\t\t\t\tnix_mark_format_cfg,\t\t\t\\\n+\t\t\t\tnix_mark_format_cfg_rsp)\t\t\\\n+M(NIX_LSO_FORMAT_CFG,\t0x8011, nix_lso_format_cfg, nix_lso_format_cfg,\t\\\n+\t\t\t\tnix_lso_format_cfg_rsp)\t\t\t\\\n+M(NIX_LF_PTP_TX_ENABLE,\t0x8013, nix_lf_ptp_tx_enable, msg_req,\t\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_LF_PTP_TX_DISABLE,\t0x8014, nix_lf_ptp_tx_disable, msg_req,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_SET_VLAN_TPID,\t0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(NIX_BP_ENABLE,\t0x8016, nix_bp_enable, nix_bp_cfg_req,\t\t\\\n+\t\t\t\tnix_bp_cfg_rsp)\t\t\t\t\\\n+M(NIX_BP_DISABLE,\t0x8017, nix_bp_disable,\tnix_bp_cfg_req, msg_rsp)\\\n+M(NIX_GET_MAC_ADDR,\t0x8018, nix_get_mac_addr, msg_req,\t\t\\\n+\t\t\t\tnix_get_mac_addr_rsp)\t\t\t\\\n+M(NIX_INLINE_IPSEC_CFG,\t0x8019, nix_inline_ipsec_cfg,\t\t\t\\\n+\t\t\t\tnix_inline_ipsec_cfg, msg_rsp)\t\t\\\n+M(NIX_INLINE_IPSEC_LF_CFG,\t\t\t\t\t\t\\\n+\t\t\t0x801a, nix_inline_ipsec_lf_cfg,\t\t\\\n+\t\t\t\tnix_inline_ipsec_lf_cfg, msg_rsp)\n+\n+/* Messages initiated by AF (range 0xC00 - 0xDFF) */\n+#define MBOX_UP_CGX_MESSAGES\t\t\t\t\t\t\\\n+M(CGX_LINK_EVENT,\t0xC00, cgx_link_event, cgx_link_info_msg,\t\\\n+\t\t\t\tmsg_rsp)\t\t\t\t\\\n+M(CGX_PTP_RX_INFO,\t0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg,\t\\\n+\t\t\t\tmsg_rsp)\n+\n+enum {\n+#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,\n+MBOX_MESSAGES\n+MBOX_UP_CGX_MESSAGES\n+#undef M\n+};\n+\n+/* Mailbox message formats */\n+\n+#define RVU_DEFAULT_PF_FUNC     0xFFFF\n+\n+/* Generic request msg used for those mbox messages which\n+ * don't send any data in the request.\n+ */\n+struct msg_req {\n+\tstruct mbox_msghdr hdr;\n+};\n+\n+/* Generic response msg used a ack or response for those mbox\n+ * messages which doesn't have a specific rsp msg format.\n+ */\n+struct msg_rsp {\n+\tstruct mbox_msghdr hdr;\n+};\n+\n+/* RVU mailbox error codes\n+ * Range 256 - 300.\n+ */\n+enum rvu_af_status {\n+\tRVU_INVALID_VF_ID           = -256,\n+};\n+\n+struct ready_msg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io sclk_feq;\t/* SCLK frequency */\n+};\n+\n+/* Structure for requesting resource provisioning.\n+ * 'modify' flag to be used when either requesting more\n+ * or detach partial of a certain resource type.\n+ * Rest of the fields specify how many of what type to\n+ * be attached.\n+ */\n+struct rsrc_attach_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io modify:1;\n+\tuint8_t __otx2_io npalf:1;\n+\tuint8_t __otx2_io nixlf:1;\n+\tuint16_t __otx2_io sso;\n+\tuint16_t __otx2_io ssow;\n+\tuint16_t __otx2_io timlfs;\n+\tuint16_t __otx2_io cptlfs;\n+};\n+\n+/* Structure for relinquishing resources.\n+ * 'partial' flag to be used when relinquishing all resources\n+ * but only of a certain type. If not set, all resources of all\n+ * types provisioned to the RVU function will be detached.\n+ */\n+struct rsrc_detach_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io partial:1;\n+\tuint8_t __otx2_io npalf:1;\n+\tuint8_t __otx2_io nixlf:1;\n+\tuint8_t __otx2_io sso:1;\n+\tuint8_t __otx2_io ssow:1;\n+\tuint8_t __otx2_io timlfs:1;\n+\tuint8_t __otx2_io cptlfs:1;\n+};\n+\n+/* NIX Transmit schedulers */\n+#define\tNIX_TXSCH_LVL_SMQ 0x0\n+#define\tNIX_TXSCH_LVL_MDQ 0x0\n+#define\tNIX_TXSCH_LVL_TL4 0x1\n+#define\tNIX_TXSCH_LVL_TL3 0x2\n+#define\tNIX_TXSCH_LVL_TL2 0x3\n+#define\tNIX_TXSCH_LVL_TL1 0x4\n+#define\tNIX_TXSCH_LVL_CNT 0x5\n+\n+/*\n+ * Number of resources available to the caller.\n+ * In reply to MBOX_MSG_FREE_RSRC_CNT.\n+ */\n+struct free_rsrcs_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];\n+\tuint16_t __otx2_io sso;\n+\tuint16_t __otx2_io tim;\n+\tuint16_t __otx2_io ssow;\n+\tuint16_t __otx2_io cpt;\n+\tuint8_t __otx2_io npa;\n+\tuint8_t __otx2_io nix;\n+};\n+\n+#define MSIX_VECTOR_INVALID\t0xFFFF\n+#define MAX_RVU_BLKLF_CNT\t256\n+\n+struct msix_offset_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io npa_msixoff;\n+\tuint16_t __otx2_io nix_msixoff;\n+\tuint8_t __otx2_io sso;\n+\tuint8_t __otx2_io ssow;\n+\tuint8_t __otx2_io timlfs;\n+\tuint8_t __otx2_io cptlfs;\n+\tuint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];\n+\tuint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];\n+};\n+\n+/* CGX mbox message formats */\n+struct cgx_stats_rsp {\n+\tstruct mbox_msghdr hdr;\n+#define CGX_RX_STATS_COUNT\t13\n+#define CGX_TX_STATS_COUNT\t18\n+\tuint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];\n+\tuint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];\n+};\n+\n+/* Structure for requesting the operation for\n+ * setting/getting mac address in the CGX interface\n+ */\n+struct cgx_mac_addr_set_or_get {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n+};\n+\n+/* Structure for requesting the operation to\n+ * add DMAC filter entry into CGX interface\n+ */\n+struct cgx_mac_addr_add_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n+};\n+\n+/* Structure for response against the operation to\n+ * add DMAC filter entry into CGX interface\n+ */\n+struct cgx_mac_addr_add_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io index;\n+};\n+\n+/* Structure for requesting the operation to\n+ * delete DMAC filter entry from CGX interface\n+ */\n+struct cgx_mac_addr_del_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io index;\n+};\n+\n+/* Structure for response against the operation to\n+ * get maximum supported DMAC filter entries\n+ */\n+struct cgx_max_dmac_entries_get_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io max_dmac_filters;\n+};\n+\n+struct cgx_link_user_info {\n+\tuint64_t __otx2_io link_up:1;\n+\tuint64_t __otx2_io full_duplex:1;\n+\tuint64_t __otx2_io lmac_type_id:4;\n+\tuint64_t __otx2_io speed:20; /* speed in Mbps */\n+#define LMACTYPE_STR_LEN 16\n+\tchar lmac_type[LMACTYPE_STR_LEN];\n+};\n+\n+struct cgx_link_info_msg {\n+\tstruct mbox_msghdr hdr;\n+\tstruct cgx_link_user_info link_info;\n+};\n+\n+struct cgx_pause_frm_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io set;\n+\t/* set = 1 if the request is to config pause frames */\n+\t/* set = 0 if the request is to fetch pause frames config */\n+\tuint8_t __otx2_io rx_pause;\n+\tuint8_t __otx2_io tx_pause;\n+};\n+\n+struct cgx_ptp_rx_info_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io ptp_en;\n+\tuint8_t __otx2_io ptp_offset;\n+};\n+\n+struct sfp_eeprom_s {\n+#define SFP_EEPROM_SIZE 256\n+\tuint16_t __otx2_io sff_id;\n+\tuint8_t __otx2_io buf[SFP_EEPROM_SIZE];\n+};\n+\n+struct cgx_lmac_fwdata_s {\n+\tuint16_t __otx2_io rw_valid;\n+\tuint64_t __otx2_io supported_fec;\n+\tuint64_t __otx2_io supported_an;\n+\tuint64_t __otx2_io supported_link_modes;\n+\t/* Only applicable if AN is supported */\n+\tuint64_t __otx2_io advertised_fec;\n+\tuint64_t __otx2_io advertised_link_modes;\n+\t/* Only applicable if SFP/QSFP slot is present */\n+\tstruct sfp_eeprom_s sfp_eeprom;\n+};\n+\n+struct cgx_fw_data {\n+\tstruct mbox_msghdr hdr;\n+\tstruct cgx_lmac_fwdata_s fwdata;\n+};\n+\n+struct cgx_set_link_state_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io enable;\n+};\n+\n+/* NPA mbox message formats */\n+\n+/* NPA mailbox error codes\n+ * Range 301 - 400.\n+ */\n+enum npa_af_status {\n+\tNPA_AF_ERR_PARAM            = -301,\n+\tNPA_AF_ERR_AQ_FULL          = -302,\n+\tNPA_AF_ERR_AQ_ENQUEUE       = -303,\n+\tNPA_AF_ERR_AF_LF_INVALID    = -304,\n+\tNPA_AF_ERR_AF_LF_ALLOC      = -305,\n+\tNIX_AF_ERR_X2P_CALIBRATE    = -398,\n+\tNIX_AF_ERR_RAN_OUT_BPID     = -399,\n+};\n+\n+#define NPA_AURA_SZ_0\t\t0\n+#define NPA_AURA_SZ_128\t\t1\n+#define\tNPA_AURA_SZ_256\t\t2\n+#define\tNPA_AURA_SZ_512\t\t3\n+#define\tNPA_AURA_SZ_1K\t\t4\n+#define\tNPA_AURA_SZ_2K\t\t5\n+#define\tNPA_AURA_SZ_4K\t\t6\n+#define\tNPA_AURA_SZ_8K\t\t7\n+#define\tNPA_AURA_SZ_16K\t\t8\n+#define\tNPA_AURA_SZ_32K\t\t9\n+#define\tNPA_AURA_SZ_64K\t\t10\n+#define\tNPA_AURA_SZ_128K\t11\n+#define\tNPA_AURA_SZ_256K\t12\n+#define\tNPA_AURA_SZ_512K\t13\n+#define\tNPA_AURA_SZ_1M\t\t14\n+#define\tNPA_AURA_SZ_MAX\t\t15\n+\n+/* For NPA LF context alloc and init */\n+struct npa_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tint __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */\n+\tuint32_t __otx2_io nr_pools; /* No of pools */\n+\tuint64_t __otx2_io way_mask;\n+};\n+\n+struct npa_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io stack_pg_ptrs;  /* No of ptrs per stack page */\n+\tuint32_t __otx2_io stack_pg_bytes; /* Size of stack page */\n+\tuint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */\n+};\n+\n+/* NPA AQ enqueue msg */\n+struct npa_aq_enq_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io aura_id;\n+\tuint8_t __otx2_io ctype;\n+\tuint8_t __otx2_io op;\n+\tunion {\n+\t\t/* Valid when op == WRITE/INIT and ctype == AURA.\n+\t\t * LF fills the pool_id in aura.pool_addr. AF will translate\n+\t\t * the pool_id to pool context pointer.\n+\t\t */\n+\t\tstruct npa_aura_s aura;\n+\t\t/* Valid when op == WRITE/INIT and ctype == POOL */\n+\t\tstruct npa_pool_s pool;\n+\t};\n+\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n+\tunion {\n+\t\t/* Valid when op == WRITE and ctype == AURA */\n+\t\tstruct npa_aura_s aura_mask;\n+\t\t/* Valid when op == WRITE and ctype == POOL */\n+\t\tstruct npa_pool_s pool_mask;\n+\t};\n+};\n+\n+struct npa_aq_enq_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\t/* Valid when op == READ and ctype == AURA */\n+\t\tstruct npa_aura_s aura;\n+\t\t/* Valid when op == READ and ctype == POOL */\n+\t\tstruct npa_pool_s pool;\n+\t};\n+};\n+\n+/* Disable all contexts of type 'ctype' */\n+struct hwctx_disable_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io ctype;\n+};\n+\n+/* NIX mbox message formats */\n+/* NIX mailbox error codes\n+ * Range 401 - 500.\n+ */\n+enum nix_af_status {\n+\tNIX_AF_ERR_PARAM            = -401,\n+\tNIX_AF_ERR_AQ_FULL          = -402,\n+\tNIX_AF_ERR_AQ_ENQUEUE       = -403,\n+\tNIX_AF_ERR_AF_LF_INVALID    = -404,\n+\tNIX_AF_ERR_AF_LF_ALLOC      = -405,\n+\tNIX_AF_ERR_TLX_ALLOC_FAIL   = -406,\n+\tNIX_AF_ERR_TLX_INVALID      = -407,\n+\tNIX_AF_ERR_RSS_SIZE_INVALID = -408,\n+\tNIX_AF_ERR_RSS_GRPS_INVALID = -409,\n+\tNIX_AF_ERR_FRS_INVALID      = -410,\n+\tNIX_AF_ERR_RX_LINK_INVALID  = -411,\n+\tNIX_AF_INVAL_TXSCHQ_CFG     = -412,\n+\tNIX_AF_SMQ_FLUSH_FAILED     = -413,\n+\tNIX_AF_MACADDR_SET_FAILED   = -414,\n+\tNIX_AF_RX_MODE_SET_FAILED   = -415,\n+\tNIX_AF_ERR_RSS_NOSPC_ALGO   = -416,\n+\tNIX_AF_ERR_RSS_NOSPC_FIELD  = -417,\n+\tNIX_AF_ERR_MARK_ALLOC_FAIL  = -418,\n+\tNIX_AF_ERR_LSOFMT_CFG_FAIL  = -419,\n+};\n+\n+/* For NIX LF context alloc and init */\n+struct nix_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tuint32_t __otx2_io rq_cnt;   /* No of receive queues */\n+\tuint32_t __otx2_io sq_cnt;   /* No of send queues */\n+\tuint32_t __otx2_io cq_cnt;   /* No of completion queues */\n+\tuint8_t __otx2_io xqe_sz;\n+\tuint16_t __otx2_io rss_sz;\n+\tuint8_t __otx2_io rss_grps;\n+\tuint16_t __otx2_io npa_func;\n+\t/* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */\n+\tuint16_t __otx2_io sso_func;\n+\tuint64_t __otx2_io rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */\n+\tuint64_t __otx2_io way_mask;\n+};\n+\n+struct nix_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io sqb_size;\n+\tuint16_t __otx2_io rx_chan_base;\n+\tuint16_t __otx2_io tx_chan_base;\n+\tuint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */\n+\tuint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */\n+\tuint8_t __otx2_io lso_tsov4_idx;\n+\tuint8_t __otx2_io lso_tsov6_idx;\n+\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n+\tuint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */\n+\tuint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */\n+\tuint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */\n+\tuint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */\n+\tuint8_t __otx2_io ptp; /* boolean; true iff PTP block is supported */\n+};\n+\n+struct nix_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_LF_DISABLE_FLOWS   0x1\n+\tuint64_t __otx2_io flags;\n+};\n+\n+/* NIX AQ enqueue msg */\n+struct nix_aq_enq_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io qidx;\n+\tuint8_t __otx2_io ctype;\n+\tuint8_t __otx2_io op;\n+\tunion {\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */\n+\t\tstruct nix_rq_ctx_s rq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */\n+\t\tstruct nix_sq_ctx_s sq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */\n+\t\tstruct nix_cq_ctx_s cq;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */\n+\t\tstruct nix_rsse_s rss;\n+\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n+\t\tstruct nix_rx_mce_s mce;\n+\t};\n+\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n+\tunion {\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */\n+\t\tstruct nix_rq_ctx_s rq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */\n+\t\tstruct nix_sq_ctx_s sq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */\n+\t\tstruct nix_cq_ctx_s cq_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */\n+\t\tstruct nix_rsse_s rss_mask;\n+\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n+\t\tstruct nix_rx_mce_s mce_mask;\n+\t};\n+};\n+\n+struct nix_aq_enq_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\tstruct nix_rq_ctx_s rq;\n+\t\tstruct nix_sq_ctx_s sq;\n+\t\tstruct nix_cq_ctx_s cq;\n+\t\tstruct nix_rsse_s   rss;\n+\t\tstruct nix_rx_mce_s mce;\n+\t};\n+};\n+\n+/* Tx scheduler/shaper mailbox messages */\n+\n+#define MAX_TXSCHQ_PER_FUNC\t128\n+\n+struct nix_txsch_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\t/* Scheduler queue count request at each level */\n+\tuint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n+\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */\n+};\n+\n+struct nix_txsch_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Scheduler queue count allocated at each level */\n+\tuint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n+\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */\n+\t/* Scheduler queue list allocated at each level */\n+\tuint16_t __otx2_io\n+\t\tschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\tuint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\t/* Traffic aggregation scheduler level */\n+\tuint8_t  __otx2_io aggr_level;\n+\t/* Aggregation lvl's RR_PRIO config */\n+\tuint8_t  __otx2_io aggr_lvl_rr_prio;\n+\t/* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */\n+\tuint8_t  __otx2_io link_cfg_lvl;\n+};\n+\n+struct nix_txsch_free_req {\n+\tstruct mbox_msghdr hdr;\n+#define TXSCHQ_FREE_ALL BIT_ULL(0)\n+\tuint16_t __otx2_io flags;\n+\t/* Scheduler queue level to be freed */\n+\tuint16_t __otx2_io schq_lvl;\n+\t/* List of scheduler queues to be freed */\n+\tuint16_t __otx2_io schq;\n+};\n+\n+struct nix_txschq_config {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */\n+#define TXSCHQ_IDX_SHIFT 16\n+#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)\n+#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)\n+\tuint8_t __otx2_io num_regs;\n+#define MAX_REGS_PER_MBOX_MSG 20\n+\tuint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];\n+\tuint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];\n+};\n+\n+struct nix_vtag_config {\n+\tstruct mbox_msghdr hdr;\n+\t/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */\n+\tuint8_t __otx2_io vtag_size;\n+\t/* cfg_type is '0' for tx vlan cfg\n+\t * cfg_type is '1' for rx vlan cfg\n+\t */\n+\tuint8_t __otx2_io cfg_type;\n+\tunion {\n+\t\t/* Valid when cfg_type is '0' */\n+\t\tstruct {\n+\t\t\tuint64_t __otx2_io vtag0;\n+\t\t\tuint64_t __otx2_io vtag1;\n+\n+\t\t\t/* cfg_vtag0 & cfg_vtag1 fields are valid\n+\t\t\t * when free_vtag0 & free_vtag1 are '0's.\n+\t\t\t */\n+\t\t\t/* cfg_vtag0 = 1 to configure vtag0 */\n+\t\t\tuint8_t __otx2_io cfg_vtag0 :1;\n+\t\t\t/* cfg_vtag1 = 1 to configure vtag1 */\n+\t\t\tuint8_t __otx2_io cfg_vtag1 :1;\n+\n+\t\t\t/* vtag0_idx & vtag1_idx are only valid when\n+\t\t\t * both cfg_vtag0 & cfg_vtag1 are '0's,\n+\t\t\t * these fields are used along with free_vtag0\n+\t\t\t * & free_vtag1 to free the nix lf's tx_vlan\n+\t\t\t * configuration.\n+\t\t\t *\n+\t\t\t * Denotes the indices of tx_vtag def registers\n+\t\t\t * that needs to be cleared and freed.\n+\t\t\t */\n+\t\t\tint __otx2_io vtag0_idx;\n+\t\t\tint __otx2_io vtag1_idx;\n+\n+\t\t\t/* Free_vtag0 & free_vtag1 fields are valid\n+\t\t\t * when cfg_vtag0 & cfg_vtag1 are '0's.\n+\t\t\t */\n+\t\t\t/* Free_vtag0 = 1 clears vtag0 configuration\n+\t\t\t * vtag0_idx denotes the index to be cleared.\n+\t\t\t */\n+\t\t\tuint8_t __otx2_io free_vtag0 :1;\n+\t\t\t/* Free_vtag1 = 1 clears vtag1 configuration\n+\t\t\t * vtag1_idx denotes the index to be cleared.\n+\t\t\t */\n+\t\t\tuint8_t __otx2_io free_vtag1 :1;\n+\t\t} tx;\n+\n+\t\t/* Valid when cfg_type is '1' */\n+\t\tstruct {\n+\t\t\t/* Rx vtag type index, valid values are in 0..7 range */\n+\t\t\tuint8_t __otx2_io vtag_type;\n+\t\t\t/* Rx vtag strip */\n+\t\t\tuint8_t __otx2_io strip_vtag :1;\n+\t\t\t/* Rx vtag capture */\n+\t\t\tuint8_t __otx2_io capture_vtag :1;\n+\t\t} rx;\n+\t};\n+};\n+\n+struct nix_vtag_config_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Indices of tx_vtag def registers used to configure\n+\t * tx vtag0 & vtag1 headers, these indices are valid\n+\t * when nix_vtag_config mbox requested for vtag0 and/\n+\t * or vtag1 configuration.\n+\t */\n+\tint __otx2_io vtag0_idx;\n+\tint __otx2_io vtag1_idx;\n+};\n+\n+struct nix_rss_flowkey_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io mcam_index;  /* MCAM entry index to modify */\n+\tuint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */\n+#define FLOW_KEY_TYPE_PORT     BIT(0)\n+#define FLOW_KEY_TYPE_IPV4     BIT(1)\n+#define FLOW_KEY_TYPE_IPV6     BIT(2)\n+#define FLOW_KEY_TYPE_TCP      BIT(3)\n+#define FLOW_KEY_TYPE_UDP      BIT(4)\n+#define FLOW_KEY_TYPE_SCTP     BIT(5)\n+#define FLOW_KEY_TYPE_NVGRE    BIT(6)\n+#define FLOW_KEY_TYPE_VXLAN    BIT(7)\n+#define FLOW_KEY_TYPE_GENEVE   BIT(8)\n+#define FLOW_KEY_TYPE_ETH_DMAC BIT(9)\n+#define FLOW_KEY_TYPE_IPV6_EXT BIT(10)\n+#define FLOW_KEY_TYPE_GTPU       BIT(11)\n+#define FLOW_KEY_TYPE_INNR_IPV4     BIT(12)\n+#define FLOW_KEY_TYPE_INNR_IPV6     BIT(13)\n+#define FLOW_KEY_TYPE_INNR_TCP      BIT(14)\n+#define FLOW_KEY_TYPE_INNR_UDP      BIT(15)\n+#define FLOW_KEY_TYPE_INNR_SCTP     BIT(16)\n+#define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)\n+\tuint8_t\tgroup;       /* RSS context or group */\n+};\n+\n+struct nix_rss_flowkey_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io alg_idx; /* Selected algo index */\n+};\n+\n+struct nix_set_mac_addr {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n+};\n+\n+struct nix_get_mac_addr_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n+};\n+\n+struct nix_mark_format_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io offset;\n+\tuint8_t __otx2_io y_mask;\n+\tuint8_t __otx2_io y_val;\n+\tuint8_t __otx2_io r_mask;\n+\tuint8_t __otx2_io r_val;\n+};\n+\n+struct nix_mark_format_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io mark_format_idx;\n+};\n+\n+struct nix_lso_format_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io field_mask;\n+#define NIX_LSO_FIELD_MAX\t(8)\n+\tuint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];\n+};\n+\n+struct nix_lso_format_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io lso_format_idx;\n+};\n+\n+struct nix_rx_mode {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_RX_MODE_UCAST    BIT(0)\n+#define NIX_RX_MODE_PROMISC  BIT(1)\n+#define NIX_RX_MODE_ALLMULTI BIT(2)\n+\tuint16_t __otx2_io mode;\n+};\n+\n+struct nix_frs_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io update_smq;    /* Update SMQ's min/max lens */\n+\tuint8_t __otx2_io update_minlen; /* Set minlen also */\n+\tuint8_t __otx2_io sdp_link;      /* Set SDP RX link */\n+\tuint16_t __otx2_io maxlen;\n+\tuint16_t __otx2_io minlen;\n+};\n+\n+struct nix_set_vlan_tpid {\n+\tstruct mbox_msghdr hdr;\n+#define NIX_VLAN_TYPE_INNER 0\n+#define NIX_VLAN_TYPE_OUTER 1\n+\tuint8_t __otx2_io vlan_type;\n+\tuint16_t __otx2_io tpid;\n+};\n+\n+struct nix_bp_cfg_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io chan_base; /* Starting channel number */\n+\tuint8_t __otx2_io chan_cnt; /* Number of channels */\n+\tuint8_t __otx2_io bpid_per_chan;\n+\t/* bpid_per_chan = 0  assigns single bp id for range of channels */\n+\t/* bpid_per_chan = 1 assigns separate bp id for each channel */\n+};\n+\n+/* Global NIX inline IPSec configuration */\n+struct nix_inline_ipsec_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io cpt_credit;\n+\tstruct {\n+\t\tuint8_t __otx2_io egrp;\n+\t\tuint8_t __otx2_io opcode;\n+\t} gen_cfg;\n+\tstruct {\n+\t\tuint16_t __otx2_io cpt_pf_func;\n+\t\tuint8_t __otx2_io cpt_slot;\n+\t} inst_qsel;\n+\tuint8_t __otx2_io enable;\n+};\n+\n+/* Per NIX LF inline IPSec configuration */\n+struct nix_inline_ipsec_lf_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io sa_base_addr;\n+\tstruct {\n+\t\tuint32_t __otx2_io tag_const;\n+\t\tuint16_t __otx2_io lenm1_max;\n+\t\tuint8_t __otx2_io sa_pow2_size;\n+\t\tuint8_t __otx2_io tt;\n+\t} ipsec_cfg0;\n+\tstruct {\n+\t\tuint32_t __otx2_io sa_idx_max;\n+\t\tuint8_t __otx2_io sa_idx_w;\n+\t} ipsec_cfg1;\n+\tuint8_t __otx2_io enable;\n+};\n+\n+/* PF can be mapped to either CGX or LBK interface,\n+ * so maximum 64 channels are possible.\n+ */\n+#define NIX_MAX_CHAN\t64\n+struct nix_bp_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Channel and bpid mapping */\n+\tuint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];\n+\t/* Number of channel for which bpids are assigned */\n+\tuint8_t __otx2_io chan_cnt;\n+};\n+\n+/* SSO mailbox error codes\n+ * Range 501 - 600.\n+ */\n+enum sso_af_status {\n+\tSSO_AF_ERR_PARAM\t= -501,\n+\tSSO_AF_ERR_LF_INVALID\t= -502,\n+\tSSO_AF_ERR_AF_LF_ALLOC\t= -503,\n+\tSSO_AF_ERR_GRP_EBUSY\t= -504,\n+\tSSO_AF_ERR_AF_LF_INVALID = -599,\n+};\n+\n+struct sso_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tuint16_t __otx2_io hwgrps;\n+};\n+\n+struct sso_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io xaq_buf_size;\n+\tuint32_t __otx2_io xaq_wq_entries;\n+\tuint32_t __otx2_io in_unit_entries;\n+\tuint16_t __otx2_io hwgrps;\n+};\n+\n+struct sso_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tuint16_t __otx2_io hwgrps;\n+};\n+\n+/* SSOW mailbox error codes\n+ * Range 601 - 700.\n+ */\n+enum ssow_af_status {\n+\tSSOW_AF_ERR_PARAM\t= -601,\n+\tSSOW_AF_ERR_LF_INVALID\t= -602,\n+\tSSOW_AF_ERR_AF_LF_ALLOC\t= -603,\n+};\n+\n+struct ssow_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tuint16_t __otx2_io hws;\n+};\n+\n+struct ssow_lf_free_req {\n+\tstruct mbox_msghdr hdr;\n+\tint __otx2_io node;\n+\tuint16_t __otx2_io hws;\n+};\n+\n+struct sso_hw_setconfig {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __otx2_io npa_aura_id;\n+\tuint16_t __otx2_io npa_pf_func;\n+\tuint16_t __otx2_io hwgrps;\n+};\n+\n+struct sso_info_req {\n+\tstruct mbox_msghdr hdr;\n+\tunion {\n+\t\tuint16_t __otx2_io grp;\n+\t\tuint16_t __otx2_io hws;\n+\t};\n+};\n+\n+struct sso_grp_priority {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io grp;\n+\tuint8_t __otx2_io priority;\n+\tuint8_t __otx2_io affinity;\n+\tuint8_t __otx2_io weight;\n+};\n+\n+struct sso_grp_qos_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io grp;\n+\tuint32_t __otx2_io xaq_limit;\n+\tuint16_t __otx2_io taq_thr;\n+\tuint16_t __otx2_io iaq_thr;\n+};\n+\n+struct sso_grp_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io grp;\n+\tuint64_t __otx2_io ws_pc;\n+\tuint64_t __otx2_io ext_pc;\n+\tuint64_t __otx2_io wa_pc;\n+\tuint64_t __otx2_io ts_pc;\n+\tuint64_t __otx2_io ds_pc;\n+\tuint64_t __otx2_io dq_pc;\n+\tuint64_t __otx2_io aw_status;\n+\tuint64_t __otx2_io page_cnt;\n+};\n+\n+struct sso_hws_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io hws;\n+\tuint64_t __otx2_io arbitration;\n+};\n+\n+/* CPT mbox message formats */\n+\n+struct cpt_rd_wr_reg_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io reg_offset;\n+\tuint64_t __otx2_io *ret_val;\n+\tuint64_t __otx2_io val;\n+\tuint8_t __otx2_io is_write;\n+};\n+\n+#define CPT_INLINE_INBOUND\t0\n+#define CPT_INLINE_OUTBOUND\t1\n+\n+struct cpt_inline_ipsec_cfg_msg {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io enable;\n+\tuint8_t __otx2_io slot;\n+\tuint8_t __otx2_io dir;\n+\tuint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */\n+\tuint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */\n+};\n+\n+/* NPC mbox message structs */\n+\n+#define NPC_MCAM_ENTRY_INVALID\t0xFFFF\n+#define NPC_MCAM_INVALID_MAP\t0xFFFF\n+\n+/* NPC mailbox error codes\n+ * Range 701 - 800.\n+ */\n+enum npc_af_status {\n+\tNPC_MCAM_INVALID_REQ\t= -701,\n+\tNPC_MCAM_ALLOC_DENIED\t= -702,\n+\tNPC_MCAM_ALLOC_FAILED\t= -703,\n+\tNPC_MCAM_PERM_DENIED\t= -704,\n+};\n+\n+struct npc_mcam_alloc_entry_req {\n+\tstruct mbox_msghdr hdr;\n+#define NPC_MAX_NONCONTIG_ENTRIES\t256\n+\tuint8_t __otx2_io contig;   /* Contiguous entries ? */\n+#define NPC_MCAM_ANY_PRIO\t\t0\n+#define NPC_MCAM_LOWER_PRIO\t\t1\n+#define NPC_MCAM_HIGHER_PRIO\t\t2\n+\tuint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */\n+\tuint16_t __otx2_io ref_entry;\n+\tuint16_t __otx2_io count;    /* Number of entries requested */\n+};\n+\n+struct npc_mcam_alloc_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Entry alloc'ed or start index if contiguous.\n+\t * Invalid in case of non-contiguous.\n+\t */\n+\tuint16_t __otx2_io entry;\n+\tuint16_t __otx2_io count; /* Number of entries allocated */\n+\tuint16_t __otx2_io free_count; /* Number of entries available */\n+\tuint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];\n+};\n+\n+struct npc_mcam_free_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io entry; /* Entry index to be freed */\n+\tuint8_t __otx2_io all;   /* Free all entries alloc'ed to this PFVF */\n+};\n+\n+struct mcam_entry {\n+#define NPC_MAX_KWS_IN_KEY\t7 /* Number of keywords in max key width */\n+\tuint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];\n+\tuint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];\n+\tuint64_t __otx2_io action;\n+\tuint64_t __otx2_io vtag_action;\n+};\n+\n+struct npc_mcam_write_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint16_t __otx2_io entry; /* MCAM entry to write this match key */\n+\tuint16_t __otx2_io cntr;\t /* Counter for this MCAM entry */\n+\tuint8_t __otx2_io intf;\t /* Rx or Tx interface */\n+\tuint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */\n+\tuint8_t __otx2_io set_cntr;    /* Set counter for this entry ? */\n+};\n+\n+/* Enable/Disable a given entry */\n+struct npc_mcam_ena_dis_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io entry;\n+};\n+\n+struct npc_mcam_shift_entry_req {\n+\tstruct mbox_msghdr hdr;\n+#define NPC_MCAM_MAX_SHIFTS\t64\n+\tuint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];\n+\tuint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];\n+\tuint16_t __otx2_io shift_count; /* Number of entries to shift */\n+};\n+\n+struct npc_mcam_shift_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Index in 'curr_entry', not entry itself */\n+\tuint16_t __otx2_io failed_entry_idx;\n+};\n+\n+struct npc_mcam_alloc_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io contig;\t/* Contiguous counters ? */\n+#define NPC_MAX_NONCONTIG_COUNTERS 64\n+\tuint16_t __otx2_io count;\t/* Number of counters requested */\n+};\n+\n+struct npc_mcam_alloc_counter_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Counter alloc'ed or start idx if contiguous.\n+\t * Invalid incase of non-contiguous.\n+\t */\n+\tuint16_t __otx2_io cntr;\n+\tuint16_t __otx2_io count; /* Number of counters allocated */\n+\tuint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];\n+};\n+\n+struct npc_mcam_oper_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */\n+};\n+\n+struct npc_mcam_oper_counter_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* valid only while fetching counter's stats */\n+\tuint64_t __otx2_io stat;\n+};\n+\n+struct npc_mcam_unmap_counter_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io cntr;\n+\tuint16_t __otx2_io entry; /* Entry and counter to be unmapped */\n+\tuint8_t __otx2_io all;   /* Unmap all entries using this counter ? */\n+};\n+\n+struct npc_mcam_alloc_and_write_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint16_t __otx2_io ref_entry;\n+\tuint8_t __otx2_io priority;    /* Lower or higher w.r.t ref_entry */\n+\tuint8_t __otx2_io intf;\t /* Rx or Tx interface */\n+\tuint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */\n+\tuint8_t __otx2_io alloc_cntr;  /* Allocate counter and map ? */\n+};\n+\n+struct npc_mcam_alloc_and_write_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io entry;\n+\tuint16_t __otx2_io cntr;\n+};\n+\n+struct npc_get_kex_cfg_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io rx_keyx_cfg;   /* NPC_AF_INTF(0)_KEX_CFG */\n+\tuint64_t __otx2_io tx_keyx_cfg;   /* NPC_AF_INTF(1)_KEX_CFG */\n+#define NPC_MAX_INTF\t2\n+#define NPC_MAX_LID\t8\n+#define NPC_MAX_LT\t16\n+#define NPC_MAX_LD\t2\n+#define NPC_MAX_LFL\t16\n+\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n+\tuint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];\n+\t/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */\n+\tuint64_t __otx2_io\n+\tintf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];\n+\t/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */\n+\tuint64_t __otx2_io\n+\tintf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];\n+#define MKEX_NAME_LEN 128\n+\tuint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];\n+};\n+\n+struct flow_msg {\n+\tunsigned char __otx2_io dmac[6];\n+\tunsigned char __otx2_io smac[6];\n+\tuint16_t __otx2_io etype;\n+\tuint16_t __otx2_io vlan_etype;\n+\tuint16_t __otx2_io vlan_tci;\n+\tunion {\n+\t\tuint32_t __otx2_io ip4src;\n+\t\tuint32_t __otx2_io ip6src[4];\n+\t};\n+\tunion {\n+\t\tuint32_t __otx2_io ip4dst;\n+\t\tuint32_t __otx2_io ip6dst[4];\n+\t};\n+\tuint8_t __otx2_io tos;\n+\tuint8_t __otx2_io ip_ver;\n+\tuint8_t __otx2_io ip_proto;\n+\tuint8_t __otx2_io tc;\n+\tuint16_t __otx2_io sport;\n+\tuint16_t __otx2_io dport;\n+};\n+\n+struct npc_install_flow_req {\n+\tstruct mbox_msghdr hdr;\n+\tstruct flow_msg packet;\n+\tstruct flow_msg mask;\n+\tuint64_t __otx2_io features;\n+\tuint16_t __otx2_io entry;\n+\tuint16_t __otx2_io channel;\n+\tuint8_t __otx2_io intf;\n+\tuint8_t __otx2_io set_cntr;\n+\tuint8_t __otx2_io default_rule;\n+\t/* Overwrite(0) or append(1) flow to default rule? */\n+\tuint8_t __otx2_io append;\n+\tuint16_t __otx2_io vf;\n+\t/* action */\n+\tuint32_t __otx2_io index;\n+\tuint16_t __otx2_io match_id;\n+\tuint8_t __otx2_io flow_key_alg;\n+\tuint8_t __otx2_io op;\n+\t/* vtag action */\n+\tuint8_t __otx2_io vtag0_type;\n+\tuint8_t __otx2_io vtag0_valid;\n+\tuint8_t __otx2_io vtag1_type;\n+\tuint8_t __otx2_io vtag1_valid;\n+};\n+\n+struct npc_install_flow_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Negative if no counter else counter number */\n+\tint __otx2_io counter;\n+};\n+\n+struct npc_delete_flow_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io entry;\n+\t/* PF + VFs */\n+\tuint8_t __otx2_io all;\n+};\n+\n+struct npc_mcam_read_entry_req {\n+\tstruct mbox_msghdr hdr;\n+\t/* MCAM entry to read */\n+\tuint16_t __otx2_io entry;\n+};\n+\n+struct npc_mcam_read_entry_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tstruct mcam_entry entry_data;\n+\tuint8_t __otx2_io intf;\n+\tuint8_t __otx2_io enable;\n+};\n+\n+/* TIM mailbox error codes\n+ * Range 801 - 900.\n+ */\n+enum tim_af_status {\n+\tTIM_AF_NO_RINGS_LEFT\t\t\t= -801,\n+\tTIM_AF_INVALID_NPA_PF_FUNC\t\t= -802,\n+\tTIM_AF_INVALID_SSO_PF_FUNC\t\t= -803,\n+\tTIM_AF_RING_STILL_RUNNING\t\t= -804,\n+\tTIM_AF_LF_INVALID\t\t\t= -805,\n+\tTIM_AF_CSIZE_NOT_ALIGNED\t\t= -806,\n+\tTIM_AF_CSIZE_TOO_SMALL\t\t\t= -807,\n+\tTIM_AF_CSIZE_TOO_BIG\t\t\t= -808,\n+\tTIM_AF_INTERVAL_TOO_SMALL\t\t= -809,\n+\tTIM_AF_INVALID_BIG_ENDIAN_VALUE\t\t= -810,\n+\tTIM_AF_INVALID_CLOCK_SOURCE\t\t= -811,\n+\tTIM_AF_GPIO_CLK_SRC_NOT_ENABLED\t\t= -812,\n+\tTIM_AF_INVALID_BSIZE\t\t\t= -813,\n+\tTIM_AF_INVALID_ENABLE_PERIODIC\t\t= -814,\n+\tTIM_AF_INVALID_ENABLE_DONTFREE\t\t= -815,\n+\tTIM_AF_ENA_DONTFRE_NSET_PERIODIC\t= -816,\n+\tTIM_AF_RING_ALREADY_DISABLED\t\t= -817,\n+};\n+\n+enum tim_clk_srcs {\n+\tTIM_CLK_SRCS_TENNS\t= 0,\n+\tTIM_CLK_SRCS_GPIO\t= 1,\n+\tTIM_CLK_SRCS_GTI\t= 2,\n+\tTIM_CLK_SRCS_PTP\t= 3,\n+\tTIM_CLK_SRSC_INVALID,\n+};\n+\n+enum tim_gpio_edge {\n+\tTIM_GPIO_NO_EDGE\t\t= 0,\n+\tTIM_GPIO_LTOH_TRANS\t\t= 1,\n+\tTIM_GPIO_HTOL_TRANS\t\t= 2,\n+\tTIM_GPIO_BOTH_TRANS\t\t= 3,\n+\tTIM_GPIO_INVALID,\n+};\n+\n+enum ptp_op {\n+\tPTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */\n+\tPTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */\n+};\n+\n+struct ptp_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io op;\n+\tint64_t __otx2_io scaled_ppm;\n+};\n+\n+struct ptp_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io clk;\n+};\n+\n+struct get_hw_cap_rsp {\n+\tstruct mbox_msghdr hdr;\n+\t/* Schq mapping fixed or flexible */\n+\tuint8_t __otx2_io nix_fixed_txschq_mapping;\n+\tuint8_t __otx2_io nix_express_traffic; /* Are express links supported */\n+\tuint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */\n+};\n+\n+struct ndc_sync_op {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __otx2_io nix_lf_tx_sync;\n+\tuint8_t __otx2_io nix_lf_rx_sync;\n+\tuint8_t __otx2_io npa_lf_sync;\n+};\n+\n+struct tim_lf_alloc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io ring;\n+\tuint16_t __otx2_io npa_pf_func;\n+\tuint16_t __otx2_io sso_pf_func;\n+};\n+\n+struct tim_ring_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io ring;\n+};\n+\n+struct tim_config_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t __otx2_io ring;\n+\tuint8_t __otx2_io bigendian;\n+\tuint8_t __otx2_io clocksource;\n+\tuint8_t __otx2_io enableperiodic;\n+\tuint8_t __otx2_io enabledontfreebuffer;\n+\tuint32_t __otx2_io bucketsize;\n+\tuint32_t __otx2_io chunksize;\n+\tuint32_t __otx2_io interval;\n+};\n+\n+struct tim_lf_alloc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io tenns_clk;\n+};\n+\n+struct tim_enable_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __otx2_io timestarted;\n+\tuint32_t __otx2_io currentbucket;\n+};\n+\n #endif /* __OTX2_MBOX_H__ */\n",
    "prefixes": [
        "v4",
        "03/27"
    ]
}