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GET /api/patches/55192/?format=api
{ "id": 55192, "url": "http://patches.dpdk.org/api/patches/55192/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-5-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190622132417.32694-5-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-5-jerinj@marvell.com", "date": "2019-06-22T13:23:54", "name": "[v4,04/27] common/octeontx2: add mailbox base support infra", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "20ddcac9b88aea0cde785ef637cae8e3c9a99e26", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-5-jerinj@marvell.com/mbox/", "series": [ { "id": 5124, "url": "http://patches.dpdk.org/api/series/5124/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5124", "date": "2019-06-22T13:23:50", "name": "OCTEON TX2 common and mempool driver", "version": 4, "mbox": "http://patches.dpdk.org/series/5124/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55192/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55192/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 76C241C5A1;\n\tSat, 22 Jun 2019 15:24:49 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id C3AA31C592\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 15:24:42 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5MDOdvL028286 for <dev@dpdk.org>; Sat, 22 Jun 2019 06:24:42 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2t9hpnrgen-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 06:24:41 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 22 Jun 2019 06:24:40 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 22 Jun 2019 06:24:40 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 628F03F703F;\n\tSat, 22 Jun 2019 06:24:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=9iJPrcuD6NBjaJNrzoWjrwJkdFFteXgk490qdY0OM18=;\n\tb=feUcG7Sto4g77an60SvJc9z77i7SYqbMkC+0c/pQx1Jp5fdp9HEmy3xYh8MeHMfwLXuU\n\tf/KvkSxib5Jd5VoBExkh6kwnkEaC4dxB8z//IID4es5GVLBAUfLlMTfBsp2Rji9+MIs8\n\tkhQaI1S1gZazXMeCbacraYcO3f8K/+OhpoAvGIWZsGB/DCDUaB6B+4qUxVdwBVCwaiAP\n\ttCgbc+7WCEZoGA4hWk1TouuAwvYP+kW3gxaMaG3/3+ZigRlJHEM82bq25Kop/flzR2CB\n\tWBCajjy/L1d9TBuqGZFZTVvdnsHrQkOQLxTZKbuYop+61BPJ5E2NtHHNaF7jQRwwJ0Xq\n\tIg== ", "From": "<jerinj@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sat, 22 Jun 2019 18:53:54 +0530", "Message-ID": "<20190622132417.32694-5-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>", "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v4 04/27] common/octeontx2: add mailbox base\n\tsupport infra", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThis patch adds mailbox init and fini support.\nEach RVU device has a dedicated 64KB mailbox region\nshared with its peer for communication. RVU AF has\na separate mailbox region shared with each of RVU PFs\nand an RVU PF has a separate region shared with\neach of it's VF.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/octeontx2/otx2_mbox.c | 133 +++++++++++++++++++++++++++\n drivers/common/octeontx2/otx2_mbox.h | 5 +\n 2 files changed, 138 insertions(+)", "diff": "diff --git a/drivers/common/octeontx2/otx2_mbox.c b/drivers/common/octeontx2/otx2_mbox.c\nindex c9cdbdbbc..cb03f6503 100644\n--- a/drivers/common/octeontx2/otx2_mbox.c\n+++ b/drivers/common/octeontx2/otx2_mbox.c\n@@ -2,4 +2,137 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <errno.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include <rte_atomic.h>\n+#include <rte_cycles.h>\n+\n #include \"otx2_mbox.h\"\n+\n+#define RVU_AF_AFPF_MBOX0\t(0x02000)\n+#define RVU_AF_AFPF_MBOX1\t(0x02008)\n+\n+#define RVU_PF_PFAF_MBOX0\t(0xC00)\n+#define RVU_PF_PFAF_MBOX1\t(0xC08)\n+\n+#define RVU_PF_VFX_PFVF_MBOX0\t(0x0000)\n+#define RVU_PF_VFX_PFVF_MBOX1\t(0x0008)\n+\n+#define\tRVU_VF_VFPF_MBOX0\t(0x0000)\n+#define\tRVU_VF_VFPF_MBOX1\t(0x0008)\n+\n+void\n+otx2_mbox_fini(struct otx2_mbox *mbox)\n+{\n+\tmbox->reg_base = 0;\n+\tmbox->hwbase = 0;\n+\tfree(mbox->dev);\n+\tmbox->dev = NULL;\n+}\n+\n+void\n+otx2_mbox_reset(struct otx2_mbox *mbox, int devid)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n+\tstruct mbox_hdr *tx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n+\tstruct mbox_hdr *rx_hdr =\n+\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\n+\trte_spinlock_lock(&mdev->mbox_lock);\n+\tmdev->msg_size = 0;\n+\tmdev->rsp_size = 0;\n+\ttx_hdr->msg_size = 0;\n+\ttx_hdr->num_msgs = 0;\n+\trx_hdr->msg_size = 0;\n+\trx_hdr->num_msgs = 0;\n+\trte_spinlock_unlock(&mdev->mbox_lock);\n+}\n+\n+int\n+otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,\n+\t uintptr_t reg_base, int direction, int ndevs)\n+{\n+\tstruct otx2_mbox_dev *mdev;\n+\tint devid;\n+\n+\tmbox->reg_base = reg_base;\n+\tmbox->hwbase = hwbase;\n+\n+\tswitch (direction) {\n+\tcase MBOX_DIR_AFPF:\n+\tcase MBOX_DIR_PFVF:\n+\t\tmbox->tx_start = MBOX_DOWN_TX_START;\n+\t\tmbox->rx_start = MBOX_DOWN_RX_START;\n+\t\tmbox->tx_size = MBOX_DOWN_TX_SIZE;\n+\t\tmbox->rx_size = MBOX_DOWN_RX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF:\n+\tcase MBOX_DIR_VFPF:\n+\t\tmbox->tx_start = MBOX_DOWN_RX_START;\n+\t\tmbox->rx_start = MBOX_DOWN_TX_START;\n+\t\tmbox->tx_size = MBOX_DOWN_RX_SIZE;\n+\t\tmbox->rx_size = MBOX_DOWN_TX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_AFPF_UP:\n+\tcase MBOX_DIR_PFVF_UP:\n+\t\tmbox->tx_start = MBOX_UP_TX_START;\n+\t\tmbox->rx_start = MBOX_UP_RX_START;\n+\t\tmbox->tx_size = MBOX_UP_TX_SIZE;\n+\t\tmbox->rx_size = MBOX_UP_RX_SIZE;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF_UP:\n+\tcase MBOX_DIR_VFPF_UP:\n+\t\tmbox->tx_start = MBOX_UP_RX_START;\n+\t\tmbox->rx_start = MBOX_UP_TX_START;\n+\t\tmbox->tx_size = MBOX_UP_RX_SIZE;\n+\t\tmbox->rx_size = MBOX_UP_TX_SIZE;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tswitch (direction) {\n+\tcase MBOX_DIR_AFPF:\n+\tcase MBOX_DIR_AFPF_UP:\n+\t\tmbox->trigger = RVU_AF_AFPF_MBOX0;\n+\t\tmbox->tr_shift = 4;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFAF:\n+\tcase MBOX_DIR_PFAF_UP:\n+\t\tmbox->trigger = RVU_PF_PFAF_MBOX1;\n+\t\tmbox->tr_shift = 0;\n+\t\tbreak;\n+\tcase MBOX_DIR_PFVF:\n+\tcase MBOX_DIR_PFVF_UP:\n+\t\tmbox->trigger = RVU_PF_VFX_PFVF_MBOX0;\n+\t\tmbox->tr_shift = 12;\n+\t\tbreak;\n+\tcase MBOX_DIR_VFPF:\n+\tcase MBOX_DIR_VFPF_UP:\n+\t\tmbox->trigger = RVU_VF_VFPF_MBOX1;\n+\t\tmbox->tr_shift = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tmbox->dev = malloc(ndevs * sizeof(struct otx2_mbox_dev));\n+\tif (!mbox->dev) {\n+\t\totx2_mbox_fini(mbox);\n+\t\treturn -ENOMEM;\n+\t}\n+\tmbox->ndevs = ndevs;\n+\tfor (devid = 0; devid < ndevs; devid++) {\n+\t\tmdev = &mbox->dev[devid];\n+\t\tmdev->mbase = (void *)(mbox->hwbase + (devid * MBOX_SIZE));\n+\t\trte_spinlock_init(&mdev->mbox_lock);\n+\t\t/* Init header to reset value */\n+\t\totx2_mbox_reset(mbox, devid);\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex 47bd91a97..c6c899661 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -1411,4 +1411,9 @@ struct tim_enable_rsp {\n \tuint32_t __otx2_io currentbucket;\n };\n \n+void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);\n+int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,\n+\t\t uintptr_t reg_base, int direction, int ndevs);\n+void otx2_mbox_fini(struct otx2_mbox *mbox);\n+\n #endif /* __OTX2_MBOX_H__ */\n", "prefixes": [ "v4", "04/27" ] }