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GET /api/patches/55181/?format=api
{ "id": 55181, "url": "http://patches.dpdk.org/api/patches/55181/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1561136352-32198-4-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1561136352-32198-4-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1561136352-32198-4-git-send-email-nicolas.chautru@intel.com", "date": "2019-06-21T16:59:05", "name": "[v3,03/10] bbdev: renaming non-generic LTE specific structure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1734f894b675cccdf02ab79148675bcffc14bf00", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1561136352-32198-4-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 5122, "url": "http://patches.dpdk.org/api/series/5122/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5122", "date": "2019-06-21T16:59:02", "name": "bbdev: adding support in BBDEV for 5GNR FEC", "version": 3, "mbox": "http://patches.dpdk.org/series/5122/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55181/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55181/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CC1C41D568;\n\tSat, 22 Jun 2019 02:02:22 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id DE9341D53F\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 02:02:12 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t21 Jun 2019 17:02:11 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n\tby orsmga003.jf.intel.com with ESMTP; 21 Jun 2019 17:02:10 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,402,1557212400\"; d=\"scan'208\";a=\"163039846\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "akhil.goyal@nxp.com,\n\tdev@dpdk.org", "Cc": "thomas@monjalon.net, ferruh.yigit@intel.com, amr.mokhtar@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Fri, 21 Jun 2019 09:59:05 -0700", "Message-Id": "<1561136352-32198-4-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1561136352-32198-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1557863143-174842-2-git-send-email-nicolas.chautru@intel.com>\n\t<1561136352-32198-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 03/10] bbdev: renaming non-generic LTE\n\tspecific structure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Renaming of the enums and structure which were LTE specific to\nallow for extension and support for 5GNR operations.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/test_bbdev_vector.c | 4 +-\n app/test-bbdev/test_bbdev_vector.h | 2 +-\n drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 103 ++++++++++++-----------\n drivers/baseband/turbo_sw/bbdev_turbo_software.c | 36 ++++----\n lib/librte_bbdev/rte_bbdev_op.h | 26 +++---\n 5 files changed, 86 insertions(+), 85 deletions(-)", "diff": "diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c\nindex e4f68e2..e149ced 100644\n--- a/app/test-bbdev/test_bbdev_vector.c\n+++ b/app/test-bbdev/test_bbdev_vector.c\n@@ -298,9 +298,9 @@\n \top_data = vector->entries[type].segments;\n \tnb_ops = &vector->entries[type].nb_segments;\n \n-\tif (*nb_ops >= RTE_BBDEV_MAX_CODE_BLOCKS) {\n+\tif (*nb_ops >= RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {\n \t\tprintf(\"Too many segments (code blocks defined): %u, max %d!\\n\",\n-\t\t\t\t*nb_ops, RTE_BBDEV_MAX_CODE_BLOCKS);\n+\t\t\t\t*nb_ops, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);\n \t\treturn -1;\n \t}\n \ndiff --git a/app/test-bbdev/test_bbdev_vector.h b/app/test-bbdev/test_bbdev_vector.h\nindex 476aae1..c85e94d 100644\n--- a/app/test-bbdev/test_bbdev_vector.h\n+++ b/app/test-bbdev/test_bbdev_vector.h\n@@ -46,7 +46,7 @@ struct op_data_buf {\n };\n \n struct op_data_entries {\n-\tstruct op_data_buf segments[RTE_BBDEV_MAX_CODE_BLOCKS];\n+\tstruct op_data_buf segments[RTE_BBDEV_TURBO_MAX_CODE_BLOCKS];\n \tunsigned int nb_segments;\n };\n \ndiff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\nindex 19e7689..7e05b94 100644\n--- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\n+++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c\n@@ -607,9 +607,9 @@ struct __rte_cache_aligned fpga_queue {\n \t\t\t\t\tRTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP,\n \t\t\t\t.max_llr_modulus = INT8_MAX,\n \t\t\t\t.num_buffers_src =\n-\t\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_hard_out =\n-\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_soft_out = 0\n \t\t\t}\n \t\t},\n@@ -621,9 +621,9 @@ struct __rte_cache_aligned fpga_queue {\n \t\t\t\t\tRTE_BBDEV_TURBO_RATE_MATCH |\n \t\t\t\t\tRTE_BBDEV_TURBO_ENC_INTERRUPTS,\n \t\t\t\t.num_buffers_src =\n-\t\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_dst =\n-\t\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS\n \t\t\t}\n \t\t},\n \t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n@@ -1332,14 +1332,15 @@ struct __rte_cache_aligned fpga_queue {\n validate_enc_op(struct rte_bbdev_enc_op *op)\n {\n \tstruct rte_bbdev_op_turbo_enc *turbo_enc = &op->turbo_enc;\n-\tstruct rte_bbdev_op_enc_cb_params *cb = NULL;\n-\tstruct rte_bbdev_op_enc_tb_params *tb = NULL;\n+\tstruct rte_bbdev_op_enc_turbo_cb_params *cb = NULL;\n+\tstruct rte_bbdev_op_enc_turbo_tb_params *tb = NULL;\n \tuint16_t kw, kw_neg, kw_pos;\n \n \tif (turbo_enc->input.length >\n-\t\t\tRTE_BBDEV_MAX_TB_SIZE >> 3) {\n+\t\t\tRTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) {\n \t\trte_bbdev_log(ERR, \"TB size (%u) is too big, max: %d\",\n-\t\t\t\tturbo_enc->input.length, RTE_BBDEV_MAX_TB_SIZE);\n+\t\t\t\tturbo_enc->input.length,\n+\t\t\t\tRTE_BBDEV_TURBO_MAX_TB_SIZE);\n \t\top->status = 1 << RTE_BBDEV_DATA_ERROR;\n \t\treturn -1;\n \t}\n@@ -1372,32 +1373,32 @@ struct __rte_cache_aligned fpga_queue {\n \n \tif (turbo_enc->code_block_mode == 0) {\n \t\ttb = &turbo_enc->tb_params;\n-\t\tif ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| tb->k_neg > RTE_BBDEV_MAX_CB_SIZE)\n+\t\tif ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)\n \t\t\t\t&& tb->c_neg > 0) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k_neg (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\ttb->k_neg, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\ttb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n-\t\tif (tb->k_pos < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| tb->k_pos > RTE_BBDEV_MAX_CB_SIZE) {\n+\t\tif (tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k_pos (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\ttb->k_pos, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\ttb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n-\t\tif (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1))\n+\t\tif (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"c_neg (%u) is out of range 0 <= value <= %u\",\n \t\t\t\t\ttb->c_neg,\n-\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS - 1);\n-\t\tif (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) {\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);\n+\t\tif (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"c (%u) is out of range 1 <= value <= %u\",\n-\t\t\t\t\ttb->c, RTE_BBDEV_MAX_CODE_BLOCKS);\n+\t\t\t\t\ttb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);\n \t\t\treturn -1;\n \t\t}\n \t\tif (tb->cab > tb->c) {\n@@ -1406,23 +1407,23 @@ struct __rte_cache_aligned fpga_queue {\n \t\t\t\t\ttb->cab, tb->c);\n \t\t\treturn -1;\n \t\t}\n-\t\tif ((tb->ea < RTE_BBDEV_MIN_CB_SIZE || (tb->ea % 2))\n+\t\tif ((tb->ea < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->ea % 2))\n \t\t\t\t&& tb->r < tb->cab) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"ea (%u) is less than %u or it is not even\",\n-\t\t\t\t\ttb->ea, RTE_BBDEV_MIN_CB_SIZE);\n+\t\t\t\t\ttb->ea, RTE_BBDEV_TURBO_MIN_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n-\t\tif ((tb->eb < RTE_BBDEV_MIN_CB_SIZE || (tb->eb % 2))\n+\t\tif ((tb->eb < RTE_BBDEV_TURBO_MIN_CB_SIZE || (tb->eb % 2))\n \t\t\t\t&& tb->c > tb->cab) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"eb (%u) is less than %u or it is not even\",\n-\t\t\t\t\ttb->eb, RTE_BBDEV_MIN_CB_SIZE);\n+\t\t\t\t\ttb->eb, RTE_BBDEV_TURBO_MIN_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n \n \t\tkw_neg = 3 * RTE_ALIGN_CEIL(tb->k_neg + 4,\n-\t\t\t\t\tRTE_BBDEV_C_SUBBLOCK);\n+\t\t\t\t\tRTE_BBDEV_TURBO_C_SUBBLOCK);\n \t\tif (tb->ncb_neg < tb->k_neg || tb->ncb_neg > kw_neg) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"ncb_neg (%u) is out of range (%u) k_neg <= value <= (%u) kw_neg\",\n@@ -1431,7 +1432,7 @@ struct __rte_cache_aligned fpga_queue {\n \t\t}\n \n \t\tkw_pos = 3 * RTE_ALIGN_CEIL(tb->k_pos + 4,\n-\t\t\t\t\tRTE_BBDEV_C_SUBBLOCK);\n+\t\t\t\t\tRTE_BBDEV_TURBO_C_SUBBLOCK);\n \t\tif (tb->ncb_pos < tb->k_pos || tb->ncb_pos > kw_pos) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"ncb_pos (%u) is out of range (%u) k_pos <= value <= (%u) kw_pos\",\n@@ -1446,23 +1447,23 @@ struct __rte_cache_aligned fpga_queue {\n \t\t}\n \t} else {\n \t\tcb = &turbo_enc->cb_params;\n-\t\tif (cb->k < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| cb->k > RTE_BBDEV_MAX_CB_SIZE) {\n+\t\tif (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\tcb->k, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\tcb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n \n-\t\tif (cb->e < RTE_BBDEV_MIN_CB_SIZE || (cb->e % 2)) {\n+\t\tif (cb->e < RTE_BBDEV_TURBO_MIN_CB_SIZE || (cb->e % 2)) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"e (%u) is less than %u or it is not even\",\n-\t\t\t\t\tcb->e, RTE_BBDEV_MIN_CB_SIZE);\n+\t\t\t\t\tcb->e, RTE_BBDEV_TURBO_MIN_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n \n-\t\tkw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_C_SUBBLOCK) * 3;\n+\t\tkw = RTE_ALIGN_CEIL(cb->k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3;\n \t\tif (cb->ncb < cb->k || cb->ncb > kw) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"ncb (%u) is out of range (%u) k <= value <= (%u) kw\",\n@@ -1655,8 +1656,8 @@ struct __rte_cache_aligned fpga_queue {\n validate_dec_op(struct rte_bbdev_dec_op *op)\n {\n \tstruct rte_bbdev_op_turbo_dec *turbo_dec = &op->turbo_dec;\n-\tstruct rte_bbdev_op_dec_cb_params *cb = NULL;\n-\tstruct rte_bbdev_op_dec_tb_params *tb = NULL;\n+\tstruct rte_bbdev_op_dec_turbo_cb_params *cb = NULL;\n+\tstruct rte_bbdev_op_dec_turbo_tb_params *tb = NULL;\n \n \tif (op->mempool == NULL) {\n \t\trte_bbdev_log(ERR, \"Invalid mempool pointer\");\n@@ -1713,33 +1714,33 @@ struct __rte_cache_aligned fpga_queue {\n \t\t}\n \n \t\ttb = &turbo_dec->tb_params;\n-\t\tif ((tb->k_neg < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| tb->k_neg > RTE_BBDEV_MAX_CB_SIZE)\n+\t\tif ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)\n \t\t\t\t&& tb->c_neg > 0) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k_neg (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\ttb->k_neg, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\ttb->k_neg, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n-\t\tif ((tb->k_pos < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| tb->k_pos > RTE_BBDEV_MAX_CB_SIZE)\n+\t\tif ((tb->k_pos < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| tb->k_pos > RTE_BBDEV_TURBO_MAX_CB_SIZE)\n \t\t\t\t&& tb->c > tb->c_neg) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k_pos (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\ttb->k_pos, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\ttb->k_pos, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n-\t\tif (tb->c_neg > (RTE_BBDEV_MAX_CODE_BLOCKS - 1))\n+\t\tif (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"c_neg (%u) is out of range 0 <= value <= %u\",\n \t\t\t\t\ttb->c_neg,\n-\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS - 1);\n-\t\tif (tb->c < 1 || tb->c > RTE_BBDEV_MAX_CODE_BLOCKS) {\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1);\n+\t\tif (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"c (%u) is out of range 1 <= value <= %u\",\n-\t\t\t\t\ttb->c, RTE_BBDEV_MAX_CODE_BLOCKS);\n+\t\t\t\t\ttb->c, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS);\n \t\t\treturn -1;\n \t\t}\n \t\tif (tb->cab > tb->c) {\n@@ -1757,12 +1758,12 @@ struct __rte_cache_aligned fpga_queue {\n \t\t}\n \n \t\tcb = &turbo_dec->cb_params;\n-\t\tif (cb->k < RTE_BBDEV_MIN_CB_SIZE\n-\t\t\t\t|| cb->k > RTE_BBDEV_MAX_CB_SIZE) {\n+\t\tif (cb->k < RTE_BBDEV_TURBO_MIN_CB_SIZE\n+\t\t\t\t|| cb->k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {\n \t\t\trte_bbdev_log(ERR,\n \t\t\t\t\t\"k (%u) is out of range %u <= value <= %u\",\n-\t\t\t\t\tcb->k, RTE_BBDEV_MIN_CB_SIZE,\n-\t\t\t\t\tRTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\t\tcb->k, RTE_BBDEV_TURBO_MIN_CB_SIZE,\n+\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\t\treturn -1;\n \t\t}\n \t}\ndiff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c\nindex 94aa536..374d177 100644\n--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c\n+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c\n@@ -34,9 +34,9 @@\n \trte_bbdev_log(DEBUG, RTE_STR(__LINE__) \":%s() \" fmt, __func__, \\\n \t\t##__VA_ARGS__)\n \n-#define DEINT_INPUT_BUF_SIZE (((RTE_BBDEV_MAX_CB_SIZE >> 3) + 1) * 48)\n+#define DEINT_INPUT_BUF_SIZE (((RTE_BBDEV_TURBO_MAX_CB_SIZE >> 3) + 1) * 48)\n #define DEINT_OUTPUT_BUF_SIZE (DEINT_INPUT_BUF_SIZE * 6)\n-#define ADAPTER_OUTPUT_BUF_SIZE ((RTE_BBDEV_MAX_CB_SIZE + 4) * 48)\n+#define ADAPTER_OUTPUT_BUF_SIZE ((RTE_BBDEV_TURBO_MAX_CB_SIZE + 4) * 48)\n \n /* private data structure */\n struct bbdev_private {\n@@ -103,7 +103,7 @@ struct turbo_sw_queue {\n {\n \tint32_t result = 0;\n \n-\tif (k < RTE_BBDEV_MIN_CB_SIZE || k > RTE_BBDEV_MAX_CB_SIZE)\n+\tif (k < RTE_BBDEV_TURBO_MIN_CB_SIZE || k > RTE_BBDEV_TURBO_MAX_CB_SIZE)\n \t\treturn -1;\n \n \tif (k > 2048) {\n@@ -158,9 +158,9 @@ struct turbo_sw_queue {\n \t\t\t\t\tRTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP |\n \t\t\t\t\tRTE_BBDEV_TURBO_EARLY_TERMINATION,\n \t\t\t\t.max_llr_modulus = 16,\n-\t\t\t\t.num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_hard_out =\n-\t\t\t\t\t\tRTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_soft_out = 0,\n \t\t\t}\n \t\t},\n@@ -172,8 +172,8 @@ struct turbo_sw_queue {\n \t\t\t\t\t\tRTE_BBDEV_TURBO_CRC_24A_ATTACH |\n \t\t\t\t\t\tRTE_BBDEV_TURBO_RATE_MATCH |\n \t\t\t\t\t\tRTE_BBDEV_TURBO_RV_INDEX_BYPASS,\n-\t\t\t\t.num_buffers_src = RTE_BBDEV_MAX_CODE_BLOCKS,\n-\t\t\t\t.num_buffers_dst = RTE_BBDEV_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_src = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n+\t\t\t\t.num_buffers_dst = RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n \t\t\t}\n \t\t},\n #endif\n@@ -257,7 +257,7 @@ struct turbo_sw_queue {\n \t\treturn -ENAMETOOLONG;\n \t}\n \tq->enc_out = rte_zmalloc_socket(name,\n-\t\t\t((RTE_BBDEV_MAX_TB_SIZE >> 3) + 3) *\n+\t\t\t((RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) + 3) *\n \t\t\tsizeof(*q->enc_out) * 3,\n \t\t\tRTE_CACHE_LINE_SIZE, queue_conf->socket);\n \tif (q->enc_out == NULL) {\n@@ -277,7 +277,7 @@ struct turbo_sw_queue {\n \t\treturn -ENAMETOOLONG;\n \t}\n \tq->enc_in = rte_zmalloc_socket(name,\n-\t\t\t(RTE_BBDEV_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in),\n+\t\t\t(RTE_BBDEV_TURBO_MAX_CB_SIZE >> 3) * sizeof(*q->enc_in),\n \t\t\tRTE_CACHE_LINE_SIZE, queue_conf->socket);\n \tif (q->enc_in == NULL) {\n \t\trte_bbdev_log(ERR,\n@@ -295,7 +295,7 @@ struct turbo_sw_queue {\n \t\treturn -ENAMETOOLONG;\n \t}\n \tq->ag = rte_zmalloc_socket(name,\n-\t\t\tRTE_BBDEV_MAX_CB_SIZE * 10 * sizeof(*q->ag),\n+\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE * 10 * sizeof(*q->ag),\n \t\t\tRTE_CACHE_LINE_SIZE, queue_conf->socket);\n \tif (q->ag == NULL) {\n \t\trte_bbdev_log(ERR,\n@@ -313,7 +313,7 @@ struct turbo_sw_queue {\n \t\treturn -ENAMETOOLONG;\n \t}\n \tq->code_block = rte_zmalloc_socket(name,\n-\t\t\tRTE_BBDEV_MAX_CB_SIZE * sizeof(*q->code_block),\n+\t\t\tRTE_BBDEV_TURBO_MAX_CB_SIZE * sizeof(*q->code_block),\n \t\t\tRTE_CACHE_LINE_SIZE, queue_conf->socket);\n \tif (q->code_block == NULL) {\n \t\trte_bbdev_log(ERR,\n@@ -439,9 +439,9 @@ struct turbo_sw_queue {\n \t\treturn -1;\n \t}\n \n-\tif (k > RTE_BBDEV_MAX_CB_SIZE) {\n+\tif (k > RTE_BBDEV_TURBO_MAX_CB_SIZE) {\n \t\trte_bbdev_log(ERR, \"CB size (%u) is too big, max: %d\",\n-\t\t\t\tk, RTE_BBDEV_MAX_CB_SIZE);\n+\t\t\t\tk, RTE_BBDEV_TURBO_MAX_CB_SIZE);\n \t\treturn -1;\n \t}\n \n@@ -466,9 +466,9 @@ struct turbo_sw_queue {\n \t\treturn -1;\n \t}\n \n-\tif (kw > RTE_BBDEV_MAX_KW) {\n+\tif (kw > RTE_BBDEV_TURBO_MAX_KW) {\n \t\trte_bbdev_log(ERR, \"Input length (%u) is too big, max: %d\",\n-\t\t\t\tkw, RTE_BBDEV_MAX_KW);\n+\t\t\t\tkw, RTE_BBDEV_TURBO_MAX_KW);\n \t\treturn -1;\n \t}\n \n@@ -773,9 +773,9 @@ struct turbo_sw_queue {\n \t/* Clear op status */\n \top->status = 0;\n \n-\tif (mbuf_total_left > RTE_BBDEV_MAX_TB_SIZE >> 3) {\n+\tif (mbuf_total_left > RTE_BBDEV_TURBO_MAX_TB_SIZE >> 3) {\n \t\trte_bbdev_log(ERR, \"TB size (%u) is too big, max: %d\",\n-\t\t\t\tmbuf_total_left, RTE_BBDEV_MAX_TB_SIZE);\n+\t\t\t\tmbuf_total_left, RTE_BBDEV_TURBO_MAX_TB_SIZE);\n \t\top->status = 1 << RTE_BBDEV_DATA_ERROR;\n \t\treturn;\n \t}\n@@ -1074,7 +1074,7 @@ struct turbo_sw_queue {\n \t\t * where D is the size of each output from turbo encoder block\n \t\t * (k + 4).\n \t\t */\n-\t\tkw = RTE_ALIGN_CEIL(k + 4, RTE_BBDEV_C_SUBBLOCK) * 3;\n+\t\tkw = RTE_ALIGN_CEIL(k + 4, RTE_BBDEV_TURBO_C_SUBBLOCK) * 3;\n \n \t\tprocess_dec_cb(q, op, c, k, kw, m_in, m_out_head, m_out,\n \t\t\t\tin_offset, out_offset, check_bit(dec->op_flags,\ndiff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h\nindex 6be53f5..f61c115 100644\n--- a/lib/librte_bbdev/rte_bbdev_op.h\n+++ b/lib/librte_bbdev/rte_bbdev_op.h\n@@ -26,22 +26,22 @@\n #include <rte_mempool.h>\n \n /* Number of columns in sub-block interleaver (36.212, section 5.1.4.1.1) */\n-#define RTE_BBDEV_C_SUBBLOCK (32)\n+#define RTE_BBDEV_TURBO_C_SUBBLOCK (32)\n /* Maximum size of Transport Block (36.213, Table, Table 7.1.7.2.5-1) */\n-#define RTE_BBDEV_MAX_TB_SIZE (391656)\n+#define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656)\n /* Maximum size of Code Block (36.212, Table 5.1.3-3) */\n-#define RTE_BBDEV_MAX_CB_SIZE (6144)\n+#define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144)\n /* Minimum size of Code Block (36.212, Table 5.1.3-3) */\n-#define RTE_BBDEV_MIN_CB_SIZE (40)\n+#define RTE_BBDEV_TURBO_MIN_CB_SIZE (40)\n /* Maximum size of circular buffer */\n-#define RTE_BBDEV_MAX_KW (18528)\n+#define RTE_BBDEV_TURBO_MAX_KW (18528)\n /*\n * Maximum number of Code Blocks in Transport Block. It is calculated based on\n * maximum size of one Code Block and one Transport Block (considering CRC24A\n * and CRC24B):\n * (391656 + 24) / (6144 - 24) = 64\n */\n-#define RTE_BBDEV_MAX_CODE_BLOCKS (64)\n+#define RTE_BBDEV_TURBO_MAX_CODE_BLOCKS (64)\n \n /** Flags for turbo decoder operation and capability structure */\n enum rte_bbdev_op_td_flag_bitmasks {\n@@ -133,7 +133,7 @@ struct rte_bbdev_op_data {\n \t * multiple CBs contiguously located next to each other.\n \t * A Transport Block (TB) represents a whole piece of data that is\n \t * divided into one or more CBs. Maximum number of CBs can be contained\n-\t * in one TB is defined by RTE_BBDEV_MAX_CODE_BLOCKS.\n+\t * in one TB is defined by RTE_BBDEV_TURBO_MAX_CODE_BLOCKS.\n \t *\n \t * An mbuf data structure cannot represent more than one TB. The\n \t * smallest piece of data that can be contained in one mbuf is one CB.\n@@ -204,7 +204,7 @@ struct rte_bbdev_op_dec_tb_params {\n \tuint16_t k_pos;\n \t/**< The number of CBs that have K- size, [0:63] */\n \tuint8_t c_neg;\n-\t/**< The total number of CBs in the TB, [1:RTE_BBDEV_MAX_CODE_BLOCKS] */\n+\t/**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */\n \tuint8_t c;\n \t/**< The number of CBs that uses Ea before switching to Eb, [0:63] */\n \tuint8_t cab;\n@@ -288,7 +288,7 @@ struct rte_bbdev_op_turbo_dec {\n \t};\n };\n \n-struct rte_bbdev_op_enc_cb_params {\n+struct rte_bbdev_op_enc_turbo_cb_params {\n \t/**< The K size of the input CB, in bits [40:6144], as specified in\n \t * 3GPP TS 36.212.\n \t * This size is inclusive of CRC24A, regardless whether it was\n@@ -305,7 +305,7 @@ struct rte_bbdev_op_enc_cb_params {\n \tuint16_t ncb;\n };\n \n-struct rte_bbdev_op_enc_tb_params {\n+struct rte_bbdev_op_enc_turbo_tb_params {\n \t/**< The K- size of the input CB, in bits [40:6144], that is in the\n \t * Turbo operation when r < C-, as in 3GPP TS 36.212.\n \t * This size is inclusive of CRC24B, regardless whether it was\n@@ -320,7 +320,7 @@ struct rte_bbdev_op_enc_tb_params {\n \tuint16_t k_pos;\n \t/**< The number of CBs that have K- size, [0:63] */\n \tuint8_t c_neg;\n-\t/**< The total number of CBs in the TB, [1:RTE_BBDEV_MAX_CODE_BLOCKS] */\n+\t/**< The total number of CBs in the TB, [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS] */\n \tuint8_t c;\n \t/**< The number of CBs that uses Ea before switching to Eb, [0:63] */\n \tuint8_t cab;\n@@ -375,9 +375,9 @@ struct rte_bbdev_op_turbo_enc {\n \tuint8_t code_block_mode; /**< [0 - TB : 1 - CB] */\n \tunion {\n \t\t/**< Struct which stores Code Block specific parameters */\n-\t\tstruct rte_bbdev_op_enc_cb_params cb_params;\n+\t\tstruct rte_bbdev_op_enc_turbo_cb_params cb_params;\n \t\t/**< Struct which stores Transport Block specific parameters */\n-\t\tstruct rte_bbdev_op_enc_tb_params tb_params;\n+\t\tstruct rte_bbdev_op_enc_turbo_tb_params tb_params;\n \t};\n };\n \n", "prefixes": [ "v3", "03/10" ] }