get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/55124/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55124,
    "url": "http://patches.dpdk.org/api/patches/55124/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190620102147.41557-3-xiaoyun.li@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190620102147.41557-3-xiaoyun.li@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190620102147.41557-3-xiaoyun.li@intel.com",
    "date": "2019-06-20T10:21:43",
    "name": "[v7,2/6] raw/ntb: add intel ntb support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "39d46dd49197788a6ec43daf6887f08c5a94e4dc",
    "submitter": {
        "id": 798,
        "url": "http://patches.dpdk.org/api/people/798/?format=api",
        "name": "Li, Xiaoyun",
        "email": "xiaoyun.li@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190620102147.41557-3-xiaoyun.li@intel.com/mbox/",
    "series": [
        {
            "id": 5099,
            "url": "http://patches.dpdk.org/api/series/5099/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5099",
            "date": "2019-06-20T10:21:41",
            "name": "rawdev driver for ntb",
            "version": 7,
            "mbox": "http://patches.dpdk.org/series/5099/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55124/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55124/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 491131D185;\n\tThu, 20 Jun 2019 12:22:53 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 5AE121D173\n\tfor <dev@dpdk.org>; Thu, 20 Jun 2019 12:22:48 +0200 (CEST)",
            "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t20 Jun 2019 03:22:48 -0700",
            "from dpdk-xiaoyun3.sh.intel.com ([10.67.119.132])\n\tby orsmga004.jf.intel.com with ESMTP; 20 Jun 2019 03:22:46 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.63,396,1557212400\"; d=\"scan'208\";a=\"311617802\"",
        "From": "Xiaoyun Li <xiaoyun.li@intel.com>",
        "To": "jingjing.wu@intel.com, keith.wiles@intel.com, cunming.liang@intel.com,\n\tomkar.maslekar@intel.com",
        "Cc": "dev@dpdk.org,\n\tXiaoyun Li <xiaoyun.li@intel.com>",
        "Date": "Thu, 20 Jun 2019 18:21:43 +0800",
        "Message-Id": "<20190620102147.41557-3-xiaoyun.li@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20190620102147.41557-1-xiaoyun.li@intel.com>",
        "References": "<20190618021055.12709-1-xiaoyun.li@intel.com>\n\t<20190620102147.41557-1-xiaoyun.li@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v7 2/6] raw/ntb: add intel ntb support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add in the list of registers for the device. And enable ntb device\nops for intel skylake platform.\n\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\n---\n drivers/raw/ntb_rawdev/Makefile       |   1 +\n drivers/raw/ntb_rawdev/meson.build    |   3 +-\n drivers/raw/ntb_rawdev/ntb_hw_intel.c | 369 ++++++++++++++++++++++++++\n drivers/raw/ntb_rawdev/ntb_hw_intel.h |  86 ++++++\n drivers/raw/ntb_rawdev/ntb_rawdev.c   |   5 +\n 5 files changed, 463 insertions(+), 1 deletion(-)\n create mode 100644 drivers/raw/ntb_rawdev/ntb_hw_intel.c\n create mode 100644 drivers/raw/ntb_rawdev/ntb_hw_intel.h",
    "diff": "diff --git a/drivers/raw/ntb_rawdev/Makefile b/drivers/raw/ntb_rawdev/Makefile\nindex da87a4610..74c045a86 100644\n--- a/drivers/raw/ntb_rawdev/Makefile\n+++ b/drivers/raw/ntb_rawdev/Makefile\n@@ -23,5 +23,6 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += ntb_rawdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV) += ntb_hw_intel.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/raw/ntb_rawdev/meson.build b/drivers/raw/ntb_rawdev/meson.build\nindex ca905049d..c696f60b3 100644\n--- a/drivers/raw/ntb_rawdev/meson.build\n+++ b/drivers/raw/ntb_rawdev/meson.build\n@@ -3,5 +3,6 @@\n \n deps += ['rawdev', 'mbuf', 'mempool',\n \t 'pci', 'bus_pci']\n-sources = files('ntb_rawdev.c')\n+sources = files('ntb_rawdev.c',\n+                'ntb_hw_intel.c')\n allow_experimental_apis = true\ndiff --git a/drivers/raw/ntb_rawdev/ntb_hw_intel.c b/drivers/raw/ntb_rawdev/ntb_hw_intel.c\nnew file mode 100644\nindex 000000000..1185cd189\n--- /dev/null\n+++ b/drivers/raw/ntb_rawdev/ntb_hw_intel.c\n@@ -0,0 +1,369 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation.\n+ */\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <errno.h>\n+\n+#include <rte_io.h>\n+#include <rte_eal.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+\n+#include \"ntb_rawdev.h\"\n+#include \"ntb_hw_intel.h\"\n+\n+enum xeon_ntb_bar {\n+\tXEON_NTB_BAR23 = 2,\n+\tXEON_NTB_BAR45 = 4,\n+};\n+\n+static enum xeon_ntb_bar intel_ntb_bar[] = {\n+\tXEON_NTB_BAR23,\n+\tXEON_NTB_BAR45,\n+};\n+\n+static int\n+intel_ntb_dev_init(struct rte_rawdev *dev)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint8_t reg_val, bar;\n+\tint ret, i;\n+\n+\tif (hw == NULL) {\n+\t\tNTB_LOG(ERR, \"Invalid device.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rte_pci_read_config(hw->pci_dev, &reg_val,\n+\t\t\t\t  sizeof(reg_val), XEON_PPD_OFFSET);\n+\tif (ret < 0) {\n+\t\tNTB_LOG(ERR, \"Cannot get NTB PPD (PCIe port definition).\");\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Check connection topo type. Only support B2B. */\n+\tswitch (reg_val & XEON_PPD_CONN_MASK) {\n+\tcase XEON_PPD_CONN_B2B:\n+\t\tNTB_LOG(INFO, \"Topo B2B (back to back) is using.\");\n+\t\tbreak;\n+\tcase XEON_PPD_CONN_TRANSPARENT:\n+\tcase XEON_PPD_CONN_RP:\n+\t\tNTB_LOG(ERR, \"Not supported conn topo. Please use B2B.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check device type. */\n+\tif (reg_val & XEON_PPD_DEV_DSD) {\n+\t\tNTB_LOG(INFO, \"DSD, Downstream Device.\");\n+\t\thw->topo = NTB_TOPO_B2B_DSD;\n+\t} else {\n+\t\tNTB_LOG(INFO, \"USD, Upstream device.\");\n+\t\thw->topo = NTB_TOPO_B2B_USD;\n+\t}\n+\n+\t/* Check if bar4 is split. Do not support split bar. */\n+\tif (reg_val & XEON_PPD_SPLIT_BAR_MASK) {\n+\t\tNTB_LOG(ERR, \"Do not support split bar.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw->hw_addr = (char *)hw->pci_dev->mem_resource[0].addr;\n+\n+\thw->mw_cnt = XEON_MW_COUNT;\n+\thw->db_cnt = XEON_DB_COUNT;\n+\thw->spad_cnt = XEON_SPAD_COUNT;\n+\n+\thw->mw_size = rte_zmalloc(\"uint64_t\",\n+\t\t\t\t  hw->mw_cnt * sizeof(uint64_t), 0);\n+\tfor (i = 0; i < hw->mw_cnt; i++) {\n+\t\tbar = intel_ntb_bar[i];\n+\t\thw->mw_size[i] = hw->pci_dev->mem_resource[bar].len;\n+\t}\n+\n+\t/* Reserve the last 2 spad registers for users. */\n+\tfor (i = 0; i < NTB_SPAD_USER_MAX_NUM; i++) {\n+\t\thw->spad_user_list[i] = hw->spad_cnt;\n+\t}\n+\thw->spad_user_list[0] = hw->spad_cnt - 2;\n+\thw->spad_user_list[1] = hw->spad_cnt - 1;\n+\n+\treturn 0;\n+}\n+\n+static void *\n+intel_ntb_get_peer_mw_addr(struct rte_rawdev *dev, int mw_idx)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint8_t bar;\n+\n+\tif (hw == NULL) {\n+\t\tNTB_LOG(ERR, \"Invalid device.\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (mw_idx < 0 || mw_idx >= hw->mw_cnt) {\n+\t\tNTB_LOG(ERR, \"Invalid memory window index (0 - %u).\",\n+\t\t\thw->mw_cnt - 1);\n+\t\treturn 0;\n+\t}\n+\n+\tbar = intel_ntb_bar[mw_idx];\n+\n+\treturn hw->pci_dev->mem_resource[bar].addr;\n+}\n+\n+static int\n+intel_ntb_mw_set_trans(struct rte_rawdev *dev, int mw_idx,\n+\t\t       uint64_t addr, uint64_t size)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tvoid *xlat_addr, *limit_addr;\n+\tuint64_t xlat_off, limit_off;\n+\tuint64_t base, limit;\n+\tuint8_t bar;\n+\n+\tif (hw == NULL) {\n+\t\tNTB_LOG(ERR, \"Invalid device.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mw_idx < 0 || mw_idx >= hw->mw_cnt) {\n+\t\tNTB_LOG(ERR, \"Invalid memory window index (0 - %u).\",\n+\t\t\thw->mw_cnt - 1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbar = intel_ntb_bar[mw_idx];\n+\n+\txlat_off = XEON_IMBAR1XBASE_OFFSET + mw_idx * XEON_BAR_INTERVAL_OFFSET;\n+\tlimit_off = XEON_IMBAR1XLMT_OFFSET + mw_idx * XEON_BAR_INTERVAL_OFFSET;\n+\txlat_addr = hw->hw_addr + xlat_off;\n+\tlimit_addr = hw->hw_addr + limit_off;\n+\n+\t/* Limit reg val should be EMBAR base address plus MW size. */\n+\tbase = addr;\n+\tlimit = hw->pci_dev->mem_resource[bar].phys_addr + size;\n+\trte_write64(base, xlat_addr);\n+\trte_write64(limit, limit_addr);\n+\n+\t/* Setup the external point so that remote can access. */\n+\txlat_off = XEON_EMBAR1_OFFSET + 8 * mw_idx;\n+\txlat_addr = hw->hw_addr + xlat_off;\n+\tlimit_off = XEON_EMBAR1XLMT_OFFSET + mw_idx * XEON_BAR_INTERVAL_OFFSET;\n+\tlimit_addr = hw->hw_addr + limit_off;\n+\tbase = rte_read64(xlat_addr);\n+\tbase &= ~0xf;\n+\tlimit = base + size;\n+\trte_write64(limit, limit_addr);\n+\n+\treturn 0;\n+}\n+\n+static int\n+intel_ntb_get_link_status(struct rte_rawdev *dev)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint16_t reg_val;\n+\tint ret;\n+\n+\tif (hw == NULL) {\n+\t\tNTB_LOG(ERR, \"Invalid device.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rte_pci_read_config(hw->pci_dev, &reg_val,\n+\t\t\t\t  sizeof(reg_val), XEON_LINK_STATUS_OFFSET);\n+\tif (ret < 0) {\n+\t\tNTB_LOG(ERR, \"Unable to get link status.\");\n+\t\treturn -EIO;\n+\t}\n+\n+\thw->link_status = NTB_LNK_STA_ACTIVE(reg_val);\n+\n+\tif (hw->link_status) {\n+\t\thw->link_speed = NTB_LNK_STA_SPEED(reg_val);\n+\t\thw->link_width = NTB_LNK_STA_WIDTH(reg_val);\n+\t} else {\n+\t\thw->link_speed = NTB_SPEED_NONE;\n+\t\thw->link_width = NTB_WIDTH_NONE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+intel_ntb_set_link(struct rte_rawdev *dev, bool up)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint32_t ntb_ctrl, reg_off;\n+\tvoid *reg_addr;\n+\n+\treg_off = XEON_NTBCNTL_OFFSET;\n+\treg_addr = hw->hw_addr + reg_off;\n+\tntb_ctrl = rte_read32(reg_addr);\n+\n+\tif (up) {\n+\t\tntb_ctrl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);\n+\t\tntb_ctrl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;\n+\t\tntb_ctrl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;\n+\t} else {\n+\t\tntb_ctrl &= ~(NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP);\n+\t\tntb_ctrl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP);\n+\t\tntb_ctrl |= NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK;\n+\t}\n+\n+\trte_write32(ntb_ctrl, reg_addr);\n+\n+\treturn 0;\n+}\n+\n+static uint32_t\n+intel_ntb_spad_read(struct rte_rawdev *dev, int spad, bool peer)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint32_t spad_v, reg_off;\n+\tvoid *reg_addr;\n+\n+\tif (spad < 0 || spad >= hw->spad_cnt) {\n+\t\tNTB_LOG(ERR, \"Invalid spad reg index.\");\n+\t\treturn 0;\n+\t}\n+\n+\t/* When peer is true, read peer spad reg */\n+\treg_off = peer ? XEON_B2B_SPAD_OFFSET : XEON_IM_SPAD_OFFSET;\n+\treg_addr = hw->hw_addr + reg_off + (spad << 2);\n+\tspad_v = rte_read32(reg_addr);\n+\n+\treturn spad_v;\n+}\n+\n+static int\n+intel_ntb_spad_write(struct rte_rawdev *dev, int spad,\n+\t\t     bool peer, uint32_t spad_v)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint32_t reg_off;\n+\tvoid *reg_addr;\n+\n+\tif (spad < 0 || spad >= hw->spad_cnt) {\n+\t\tNTB_LOG(ERR, \"Invalid spad reg index.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* When peer is true, write peer spad reg */\n+\treg_off = peer ? XEON_B2B_SPAD_OFFSET : XEON_IM_SPAD_OFFSET;\n+\treg_addr = hw->hw_addr + reg_off + (spad << 2);\n+\n+\trte_write32(spad_v, reg_addr);\n+\n+\treturn 0;\n+}\n+\n+static uint64_t\n+intel_ntb_db_read(struct rte_rawdev *dev)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint64_t db_off, db_bits;\n+\tvoid *db_addr;\n+\n+\tdb_off = XEON_IM_INT_STATUS_OFFSET;\n+\tdb_addr = hw->hw_addr + db_off;\n+\n+\tdb_bits = rte_read64(db_addr);\n+\n+\treturn db_bits;\n+}\n+\n+static int\n+intel_ntb_db_clear(struct rte_rawdev *dev, uint64_t db_bits)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint64_t db_off;\n+\tvoid *db_addr;\n+\n+\tdb_off = XEON_IM_INT_STATUS_OFFSET;\n+\tdb_addr = hw->hw_addr + db_off;\n+\n+\trte_write64(db_bits, db_addr);\n+\n+\treturn 0;\n+}\n+\n+static int\n+intel_ntb_db_set_mask(struct rte_rawdev *dev, uint64_t db_mask)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint64_t db_m_off;\n+\tvoid *db_m_addr;\n+\n+\tdb_m_off = XEON_IM_INT_DISABLE_OFFSET;\n+\tdb_m_addr = hw->hw_addr + db_m_off;\n+\n+\tdb_mask |= hw->db_mask;\n+\n+\trte_write64(db_mask, db_m_addr);\n+\n+\thw->db_mask = db_mask;\n+\n+\treturn 0;\n+}\n+\n+static int\n+intel_ntb_peer_db_set(struct rte_rawdev *dev, uint8_t db_idx)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint32_t db_off;\n+\tvoid *db_addr;\n+\n+\tif (((uint64_t)1 << db_idx) & ~hw->db_valid_mask) {\n+\t\tNTB_LOG(ERR, \"Invalid doorbell.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdb_off = XEON_IM_DOORBELL_OFFSET + db_idx * 4;\n+\tdb_addr = hw->hw_addr + db_off;\n+\n+\trte_write32(1, db_addr);\n+\n+\treturn 0;\n+}\n+\n+static int\n+intel_ntb_vector_bind(struct rte_rawdev *dev, uint8_t intr, uint8_t msix)\n+{\n+\tstruct ntb_hw *hw = dev->dev_private;\n+\tuint8_t reg_off;\n+\tvoid *reg_addr;\n+\n+\tif (intr >= hw->db_cnt) {\n+\t\tNTB_LOG(ERR, \"Invalid intr source.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Bind intr source to msix vector */\n+\treg_off = XEON_INTVEC_OFFSET;\n+\treg_addr = hw->hw_addr + reg_off + intr;\n+\n+\trte_write8(msix, reg_addr);\n+\n+\treturn 0;\n+}\n+\n+/* operations for primary side of local ntb */\n+const struct ntb_dev_ops intel_ntb_ops = {\n+\t.ntb_dev_init       = intel_ntb_dev_init,\n+\t.get_peer_mw_addr   = intel_ntb_get_peer_mw_addr,\n+\t.mw_set_trans       = intel_ntb_mw_set_trans,\n+\t.get_link_status    = intel_ntb_get_link_status,\n+\t.set_link           = intel_ntb_set_link,\n+\t.spad_read          = intel_ntb_spad_read,\n+\t.spad_write         = intel_ntb_spad_write,\n+\t.db_read            = intel_ntb_db_read,\n+\t.db_clear           = intel_ntb_db_clear,\n+\t.db_set_mask        = intel_ntb_db_set_mask,\n+\t.peer_db_set        = intel_ntb_peer_db_set,\n+\t.vector_bind        = intel_ntb_vector_bind,\n+};\ndiff --git a/drivers/raw/ntb_rawdev/ntb_hw_intel.h b/drivers/raw/ntb_rawdev/ntb_hw_intel.h\nnew file mode 100644\nindex 000000000..4d1e64504\n--- /dev/null\n+++ b/drivers/raw/ntb_rawdev/ntb_hw_intel.h\n@@ -0,0 +1,86 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation.\n+ */\n+\n+#ifndef _NTB_HW_INTEL_H_\n+#define _NTB_HW_INTEL_H_\n+\n+/* Ntb control and link status */\n+#define NTB_CTL_CFG_LOCK\t\t1\n+#define NTB_CTL_DISABLE\t\t\t2\n+#define NTB_CTL_S2P_BAR2_SNOOP\t\t(1 << 2)\n+#define NTB_CTL_P2S_BAR2_SNOOP\t\t(1 << 4)\n+#define NTB_CTL_S2P_BAR4_SNOOP\t\t(1 << 6)\n+#define NTB_CTL_P2S_BAR4_SNOOP\t\t(1 << 8)\n+#define NTB_CTL_S2P_BAR5_SNOOP\t\t(1 << 12)\n+#define NTB_CTL_P2S_BAR5_SNOOP\t\t(1 << 14)\n+\n+#define NTB_LNK_STA_ACTIVE_BIT\t\t0x2000\n+#define NTB_LNK_STA_SPEED_MASK\t\t0x000f\n+#define NTB_LNK_STA_WIDTH_MASK\t\t0x03f0\n+#define NTB_LNK_STA_ACTIVE(x)\t\t(!!((x) & NTB_LNK_STA_ACTIVE_BIT))\n+#define NTB_LNK_STA_SPEED(x)\t\t((x) & NTB_LNK_STA_SPEED_MASK)\n+#define NTB_LNK_STA_WIDTH(x)\t\t(((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)\n+\n+/* Intel Skylake Xeon hardware */\n+#define XEON_IMBAR1SZ_OFFSET\t\t0x00d0\n+#define XEON_IMBAR2SZ_OFFSET\t\t0x00d1\n+#define XEON_EMBAR1SZ_OFFSET\t\t0x00d2\n+#define XEON_EMBAR2SZ_OFFSET\t\t0x00d3\n+#define XEON_DEVCTRL_OFFSET\t\t0x0098\n+#define XEON_DEVSTS_OFFSET\t\t0x009a\n+#define XEON_UNCERRSTS_OFFSET\t\t0x014c\n+#define XEON_CORERRSTS_OFFSET\t\t0x0158\n+#define XEON_LINK_STATUS_OFFSET\t\t0x01a2\n+\n+#define XEON_NTBCNTL_OFFSET\t\t0x0000\n+#define XEON_BAR_INTERVAL_OFFSET\t0x0010\n+#define XEON_IMBAR1XBASE_OFFSET\t\t0x0010\t\t/* SBAR2XLAT */\n+#define XEON_IMBAR1XLMT_OFFSET\t\t0x0018\t\t/* SBAR2LMT */\n+#define XEON_IMBAR2XBASE_OFFSET\t\t0x0020\t\t/* SBAR4XLAT */\n+#define XEON_IMBAR2XLMT_OFFSET\t\t0x0028\t\t/* SBAR4LMT */\n+#define XEON_IM_INT_STATUS_OFFSET\t0x0040\n+#define XEON_IM_INT_DISABLE_OFFSET\t0x0048\n+#define XEON_IM_SPAD_OFFSET\t\t0x0080\t\t/* SPAD */\n+#define XEON_USMEMMISS_OFFSET\t\t0x0070\n+#define XEON_INTVEC_OFFSET\t\t0x00d0\n+#define XEON_IM_DOORBELL_OFFSET\t\t0x0100\t\t/* SDOORBELL0 */\n+#define XEON_B2B_SPAD_OFFSET\t\t0x0180\t\t/* B2B SPAD */\n+#define XEON_EMBAR0XBASE_OFFSET\t\t0x4008\t\t/* B2B_XLAT */\n+#define XEON_EMBAR1XBASE_OFFSET\t\t0x4010\t\t/* PBAR2XLAT */\n+#define XEON_EMBAR1XLMT_OFFSET\t\t0x4018\t\t/* PBAR2LMT */\n+#define XEON_EMBAR2XBASE_OFFSET\t\t0x4020\t\t/* PBAR4XLAT */\n+#define XEON_EMBAR2XLMT_OFFSET\t\t0x4028\t\t/* PBAR4LMT */\n+#define XEON_EM_INT_STATUS_OFFSET\t0x4040\n+#define XEON_EM_INT_DISABLE_OFFSET\t0x4048\n+#define XEON_EM_SPAD_OFFSET\t\t0x4080\t\t/* remote SPAD */\n+#define XEON_EM_DOORBELL_OFFSET\t\t0x4100\t\t/* PDOORBELL0 */\n+#define XEON_SPCICMD_OFFSET\t\t0x4504\t\t/* SPCICMD */\n+#define XEON_EMBAR0_OFFSET\t\t0x4510\t\t/* SBAR0BASE */\n+#define XEON_EMBAR1_OFFSET\t\t0x4518\t\t/* SBAR23BASE */\n+#define XEON_EMBAR2_OFFSET\t\t0x4520\t\t/* SBAR45BASE */\n+\n+#define XEON_PPD_OFFSET\t\t\t0x00d4\n+#define XEON_PPD_CONN_MASK\t\t0x03\n+#define XEON_PPD_CONN_TRANSPARENT\t0x00\n+#define XEON_PPD_CONN_B2B\t\t0x01\n+#define XEON_PPD_CONN_RP\t\t0x02\n+#define XEON_PPD_DEV_MASK\t\t0x10\n+#define XEON_PPD_DEV_USD\t\t0x00\n+#define XEON_PPD_DEV_DSD\t\t0x10\n+#define XEON_PPD_SPLIT_BAR_MASK\t\t0x40\n+\n+\n+#define XEON_MW_COUNT\t\t\t2\n+\n+#define XEON_DB_COUNT\t\t\t32\n+#define XEON_DB_LINK\t\t\t32\n+#define XEON_DB_LINK_BIT\t\t(1ULL << XEON_DB_LINK)\n+#define XEON_DB_MSIX_VECTOR_COUNT\t33\n+#define XEON_DB_MSIX_VECTOR_SHIFT\t1\n+#define XEON_DB_TOTAL_SHIFT\t\t33\n+#define XEON_SPAD_COUNT\t\t\t16\n+\n+extern const struct ntb_dev_ops intel_ntb_ops;\n+\n+#endif /* _NTB_HW_INTEL_H_ */\ndiff --git a/drivers/raw/ntb_rawdev/ntb_rawdev.c b/drivers/raw/ntb_rawdev/ntb_rawdev.c\nindex 07ad81d44..113ef0169 100644\n--- a/drivers/raw/ntb_rawdev/ntb_rawdev.c\n+++ b/drivers/raw/ntb_rawdev/ntb_rawdev.c\n@@ -18,11 +18,13 @@\n #include <rte_rawdev.h>\n #include <rte_rawdev_pmd.h>\n \n+#include \"ntb_hw_intel.h\"\n #include \"ntb_rawdev.h\"\n \n int ntb_logtype;\n \n static const struct rte_pci_id pci_id_ntb_map[] = {\n+\t{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_SKX) },\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n@@ -353,6 +355,9 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)\n \thw->link_width = NTB_WIDTH_NONE;\n \n \tswitch (pci_dev->id.device_id) {\n+\tcase NTB_INTEL_DEV_ID_B2B_SKX:\n+\t\thw->ntb_ops = &intel_ntb_ops;\n+\t\tbreak;\n \tdefault:\n \t\tNTB_LOG(ERR, \"Not supported device.\");\n \t\treturn -EINVAL;\n",
    "prefixes": [
        "v7",
        "2/6"
    ]
}