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{
    "id": 55036,
    "url": "http://patches.dpdk.org/api/patches/55036/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/19687c0b1cadc5b78c824fd03252c512145258dd.1560958308.git.xuanziyang2@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<19687c0b1cadc5b78c824fd03252c512145258dd.1560958308.git.xuanziyang2@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/19687c0b1cadc5b78c824fd03252c512145258dd.1560958308.git.xuanziyang2@huawei.com",
    "date": "2019-06-19T16:04:38",
    "name": "[v5,08/15] net/hinic/base: add nic business configurations",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "93a513d84ab9ba55af51aa9e977410ccea5d7220",
    "submitter": {
        "id": 1321,
        "url": "http://patches.dpdk.org/api/people/1321/?format=api",
        "name": "Ziyang Xuan",
        "email": "xuanziyang2@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/19687c0b1cadc5b78c824fd03252c512145258dd.1560958308.git.xuanziyang2@huawei.com/mbox/",
    "series": [
        {
            "id": 5084,
            "url": "http://patches.dpdk.org/api/series/5084/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5084",
            "date": "2019-06-19T15:45:20",
            "name": "A new net PMD - hinic",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/5084/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55036/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/55036/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 819E61D115;\n\tWed, 19 Jun 2019 17:53:13 +0200 (CEST)",
            "from huawei.com (szxga04-in.huawei.com [45.249.212.190])\n\tby dpdk.org (Postfix) with ESMTP id 5A50A1D0D0\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 17:52:51 +0200 (CEST)",
            "from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id 1B8EBC4A6D3E3D47ADCB\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 23:52:44 +0800 (CST)",
            "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP\n\tServer id 14.3.439.0; Wed, 19 Jun 2019 23:52:36 +0800"
        ],
        "From": "Ziyang Xuan <xuanziyang2@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <shahar.belkar@huawei.com>,\n\t<luoxianjun@huawei.com>, Ziyang Xuan <xuanziyang2@huawei.com>",
        "Date": "Thu, 20 Jun 2019 00:04:38 +0800",
        "Message-ID": "<19687c0b1cadc5b78c824fd03252c512145258dd.1560958308.git.xuanziyang2@huawei.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<cover.1560958308.git.xuanziyang2@huawei.com>",
        "References": "<cover.1560958308.git.xuanziyang2@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.175.119.39]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH v5 08/15] net/hinic/base: add nic business\n\tconfigurations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The items of configurations and queries for nic business include\nMAC, VLAN, MTU, RSS and so on. These configurations and queries\nare handled by mgmt module. This patch introduces related\ndata structures and function codes.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/base/hinic_pmd_niccfg.c | 1276 +++++++++++++++++++++\n drivers/net/hinic/base/hinic_pmd_niccfg.h |  658 +++++++++++\n 2 files changed, 1934 insertions(+)\n create mode 100644 drivers/net/hinic/base/hinic_pmd_niccfg.c\n create mode 100644 drivers/net/hinic/base/hinic_pmd_niccfg.h",
    "diff": "diff --git a/drivers/net/hinic/base/hinic_pmd_niccfg.c b/drivers/net/hinic/base/hinic_pmd_niccfg.c\nnew file mode 100644\nindex 000000000..7da0a8874\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_pmd_niccfg.c\n@@ -0,0 +1,1276 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#include \"hinic_compat.h\"\n+#include \"hinic_pmd_hwdev.h\"\n+#include \"hinic_pmd_hwif.h\"\n+#include \"hinic_pmd_eqs.h\"\n+#include \"hinic_pmd_wq.h\"\n+#include \"hinic_pmd_mgmt.h\"\n+#include \"hinic_pmd_cmdq.h\"\n+#include \"hinic_pmd_niccfg.h\"\n+\n+#define l2nic_msg_to_mgmt_sync(hwdev, cmd, buf_in,\t\t\\\n+\t\t\t       in_size, buf_out, out_size)\t\\\n+\thinic_msg_to_mgmt_sync(hwdev, HINIC_MOD_L2NIC, cmd,\t\\\n+\t\t\tbuf_in, in_size,\t\t\t\\\n+\t\t\tbuf_out, out_size, 0)\n+\n+int hinic_init_function_table(void *hwdev, u16 rx_buf_sz)\n+{\n+\tstruct hinic_function_table function_table;\n+\tu16 out_size = sizeof(function_table);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&function_table, 0, sizeof(function_table));\n+\tfunction_table.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tfunction_table.func_id = hinic_global_func_id(hwdev);\n+\tfunction_table.mtu = 0x3FFF;\t/* default, max mtu */\n+\tfunction_table.rx_wqe_buf_size = rx_buf_sz;\n+\n+\terr = hinic_msg_to_mgmt_sync(hwdev, HINIC_MOD_L2NIC,\n+\t\t\t\t     HINIC_PORT_CMD_INIT_FUNC,\n+\t\t\t\t     &function_table, sizeof(function_table),\n+\t\t\t\t     &function_table, &out_size, 0);\n+\tif (err || function_table.mgmt_msg_head.status || !out_size) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to init func table, ret = %d\",\n+\t\t\tfunction_table.mgmt_msg_head.status);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_get_base_qpn - get global number of queue\n+ * @hwdev: the hardware interface of a nic device\n+ * @global_qpn: vat page size\n+ * @return\n+ *   0 on success,\n+ *   negative error value otherwise.\n+ **/\n+int hinic_get_base_qpn(void *hwdev, u16 *global_qpn)\n+{\n+\tstruct hinic_cmd_qpn cmd_qpn;\n+\tu16 out_size = sizeof(cmd_qpn);\n+\tint err;\n+\n+\tif (!hwdev || !global_qpn) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or global_qpn is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&cmd_qpn, 0, sizeof(cmd_qpn));\n+\tcmd_qpn.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tcmd_qpn.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = hinic_msg_to_mgmt_sync(hwdev, HINIC_MOD_L2NIC,\n+\t\t\t\t     HINIC_PORT_CMD_GET_GLOBAL_QPN,\n+\t\t\t\t     &cmd_qpn, sizeof(cmd_qpn), &cmd_qpn,\n+\t\t\t\t     &out_size, 0);\n+\tif (err || !out_size || cmd_qpn.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to get base qpn, status(%d)\",\n+\t\t\tcmd_qpn.mgmt_msg_head.status);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*global_qpn = cmd_qpn.base_qpn;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_set_mac - Init mac_vlan table in NIC.\n+ * @hwdev: the hardware interface of a nic device\n+ * @mac_addr: mac address\n+ * @vlan_id: set 0 for mac_vlan table initialization\n+ * @func_id: global function id of NIC\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_set_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id)\n+{\n+\tstruct hinic_port_mac_set mac_info;\n+\tu16 out_size = sizeof(mac_info);\n+\tint err;\n+\n+\tif (!hwdev || !mac_addr) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or mac_addr is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&mac_info, 0, sizeof(mac_info));\n+\tmac_info.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tmac_info.func_id = func_id;\n+\tmac_info.vlan_id = vlan_id;\n+\tmemmove(mac_info.mac, mac_addr, ETH_ALEN);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_MAC, &mac_info,\n+\t\t\t\t     sizeof(mac_info), &mac_info, &out_size);\n+\tif (err || !out_size || (mac_info.mgmt_msg_head.status &&\n+\t    mac_info.mgmt_msg_head.status != HINIC_PF_SET_VF_ALREADY)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set MAC, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, mac_info.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (mac_info.mgmt_msg_head.status == HINIC_PF_SET_VF_ALREADY) {\n+\t\tPMD_DRV_LOG(WARNING, \"PF has already set vf mac, Ignore set operation.\");\n+\t\treturn HINIC_PF_SET_VF_ALREADY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_del_mac - Uninit mac_vlan table in NIC.\n+ * @hwdev: the hardware interface of a nic device\n+ * @mac_addr: mac address\n+ * @vlan_id: set 0 for mac_vlan table initialization\n+ * @func_id: global function id of NIC\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_del_mac(void *hwdev, u8 *mac_addr, u16 vlan_id,\n+\t\t  u16 func_id)\n+{\n+\tstruct hinic_port_mac_set mac_info;\n+\tu16 out_size = sizeof(mac_info);\n+\tint err;\n+\n+\tif (!hwdev || !mac_addr) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or mac_addr is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (vlan_id >= VLAN_N_VID) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid VLAN number\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&mac_info, 0, sizeof(mac_info));\n+\tmac_info.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tmac_info.func_id = func_id;\n+\tmac_info.vlan_id = vlan_id;\n+\tmemmove(mac_info.mac, mac_addr, ETH_ALEN);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_DEL_MAC, &mac_info,\n+\t\t\t\t     sizeof(mac_info), &mac_info, &out_size);\n+\tif (err || !out_size || (mac_info.mgmt_msg_head.status &&\n+\t\tmac_info.mgmt_msg_head.status != HINIC_PF_SET_VF_ALREADY)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to delete MAC, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, mac_info.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (mac_info.mgmt_msg_head.status == HINIC_PF_SET_VF_ALREADY) {\n+\t\tPMD_DRV_LOG(WARNING, \"PF has already set vf mac, Ignore delete operation.\");\n+\t\treturn HINIC_PF_SET_VF_ALREADY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_default_mac(void *hwdev, u8 *mac_addr)\n+{\n+\tstruct hinic_port_mac_set mac_info;\n+\tu16 out_size = sizeof(mac_info);\n+\tint err;\n+\n+\tif (!hwdev || !mac_addr) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or mac_addr is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&mac_info, 0, sizeof(mac_info));\n+\tmac_info.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tmac_info.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_MAC,\n+\t\t\t\t     &mac_info, sizeof(mac_info),\n+\t\t\t\t     &mac_info, &out_size);\n+\tif (err || !out_size || mac_info.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get mac, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, mac_info.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemmove(mac_addr, mac_info.mac, ETH_ALEN);\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_port_mtu(void *hwdev, u32 new_mtu)\n+{\n+\tstruct hinic_mtu mtu_info;\n+\tu16 out_size = sizeof(mtu_info);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&mtu_info, 0, sizeof(mtu_info));\n+\tmtu_info.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tmtu_info.func_id = hinic_global_func_id(hwdev);\n+\tmtu_info.mtu = new_mtu;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_CHANGE_MTU,\n+\t\t\t\t     &mtu_info, sizeof(mtu_info),\n+\t\t\t\t     &mtu_info, &out_size);\n+\tif (err || !out_size || mtu_info.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set mtu, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, mtu_info.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_link_status(void *hwdev, u8 *link_state)\n+{\n+\tstruct hinic_get_link get_link;\n+\tu16 out_size = sizeof(get_link);\n+\tint err;\n+\n+\tif (!hwdev || !link_state) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or link_state is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&get_link, 0, sizeof(get_link));\n+\tget_link.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tget_link.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_LINK_STATE,\n+\t\t\t\t     &get_link, sizeof(get_link),\n+\t\t\t\t     &get_link, &out_size);\n+\tif (err || !out_size || get_link.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get link state, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, get_link.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*link_state = get_link.link_status;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_set_vport_enable - Notify firmware that driver is ready or not.\n+ * @hwdev: the hardware interface of a nic device\n+ * @enable: 1: driver is ready; 0: driver is not ok.\n+ * Return: 0 on success and state is filled, negative error value otherwise.\n+ **/\n+int hinic_set_vport_enable(void *hwdev, bool enable)\n+{\n+\tstruct hinic_vport_state en_state;\n+\tu16 out_size = sizeof(en_state);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&en_state, 0, sizeof(en_state));\n+\ten_state.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ten_state.func_id = hinic_global_func_id(hwdev);\n+\ten_state.state = (enable ? 1 : 0);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_VPORT_ENABLE,\n+\t\t\t\t     &en_state, sizeof(en_state),\n+\t\t\t\t     &en_state, &out_size);\n+\tif (err || !out_size || en_state.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set vport state, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, en_state.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_set_port_enable - open MAG to receive packets.\n+ * @hwdev: the hardware interface of a nic device\n+ * @enable: 1: open MAG; 0: close MAG.\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_set_port_enable(void *hwdev, bool enable)\n+{\n+\tstruct hinic_port_state en_state;\n+\tu16 out_size = sizeof(en_state);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&en_state, 0, sizeof(en_state));\n+\ten_state.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ten_state.state = (enable ? HINIC_PORT_ENABLE : HINIC_PORT_DISABLE);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_PORT_ENABLE,\n+\t\t\t\t     &en_state, sizeof(en_state),\n+\t\t\t\t     &en_state, &out_size);\n+\tif (err || !out_size || en_state.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set phy port state, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, en_state.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_port_info(void *hwdev, struct nic_port_info *port_info)\n+{\n+\tstruct hinic_port_info port_msg;\n+\tu16 out_size = sizeof(port_msg);\n+\tint err;\n+\n+\tif (!hwdev || !port_info) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or port_info is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&port_msg, 0, sizeof(port_msg));\n+\tport_msg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tport_msg.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_PORT_INFO,\n+\t\t\t\t     &port_msg, sizeof(port_msg),\n+\t\t\t\t     &port_msg, &out_size);\n+\tif (err || !out_size || port_msg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to get port info, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, port_msg.mgmt_msg_head.status, out_size);\n+\t\treturn err;\n+\t}\n+\n+\tport_info->autoneg_cap = port_msg.autoneg_cap;\n+\tport_info->autoneg_state = port_msg.autoneg_state;\n+\tport_info->duplex = port_msg.duplex;\n+\tport_info->port_type = port_msg.port_type;\n+\tport_info->speed = port_msg.speed;\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_pause_config(void *hwdev, struct nic_pause_config nic_pause)\n+{\n+\tstruct hinic_pause_config pause_info;\n+\tu16 out_size = sizeof(pause_info);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&pause_info, 0, sizeof(pause_info));\n+\tpause_info.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tpause_info.func_id = hinic_global_func_id(hwdev);\n+\tpause_info.auto_neg = nic_pause.auto_neg;\n+\tpause_info.rx_pause = nic_pause.rx_pause;\n+\tpause_info.tx_pause = nic_pause.tx_pause;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_PAUSE_INFO,\n+\t\t\t\t     &pause_info, sizeof(pause_info),\n+\t\t\t\t     &pause_info, &out_size);\n+\tif (err || !out_size || pause_info.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set pause info, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, pause_info.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_dcb_set_ets(void *hwdev, u8 *up_tc, u8 *pg_bw,\n+\t\t      u8 *pgid, u8 *up_bw, u8 *prio)\n+{\n+\tstruct hinic_up_ets_cfg ets;\n+\tu16 out_size = sizeof(ets);\n+\tu16 up_bw_t = 0;\n+\tu8 pg_bw_t = 0;\n+\tint i, err;\n+\n+\tif (!hwdev || !up_tc || !pg_bw || !pgid || !up_bw || !prio) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev, up_tc, pg_bw, pgid, up_bw or prio is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < HINIC_DCB_TC_MAX; i++) {\n+\t\tup_bw_t += *(up_bw + i);\n+\t\tpg_bw_t += *(pg_bw + i);\n+\n+\t\tif (*(up_tc + i) > HINIC_DCB_TC_MAX) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Invalid up %d mapping tc: %d\", i,\n+\t\t\t\t*(up_tc + i));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (pg_bw_t != 100 || (up_bw_t % 100) != 0) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Invalid pg_bw: %d or up_bw: %d\", pg_bw_t, up_bw_t);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&ets, 0, sizeof(ets));\n+\tets.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tets.port_id = 0;    /* reserved */\n+\tmemcpy(ets.up_tc, up_tc, HINIC_DCB_TC_MAX);\n+\tmemcpy(ets.pg_bw, pg_bw, HINIC_DCB_UP_MAX);\n+\tmemcpy(ets.pgid, pgid, HINIC_DCB_UP_MAX);\n+\tmemcpy(ets.up_bw, up_bw, HINIC_DCB_UP_MAX);\n+\tmemcpy(ets.prio, prio, HINIC_DCB_UP_MAX);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_ETS,\n+\t\t\t\t     &ets, sizeof(ets), &ets, &out_size);\n+\tif (err || ets.mgmt_msg_head.status || !out_size) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set ets, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, ets.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_vport_stats(void *hwdev, struct hinic_vport_stats *stats)\n+{\n+\tstruct hinic_port_stats_info vport_stats_cmd;\n+\tstruct hinic_cmd_vport_stats vport_stats_rsp;\n+\tu16 out_size = sizeof(vport_stats_rsp);\n+\tint err;\n+\n+\tif (!hwdev || !stats) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or stats is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&vport_stats_rsp, 0, sizeof(vport_stats_rsp));\n+\tmemset(&vport_stats_cmd, 0, sizeof(vport_stats_cmd));\n+\tvport_stats_cmd.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tvport_stats_cmd.stats_version = HINIC_PORT_STATS_VERSION;\n+\tvport_stats_cmd.func_id = hinic_global_func_id(hwdev);\n+\tvport_stats_cmd.stats_size = sizeof(vport_stats_rsp);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_VPORT_STAT,\n+\t\t\t\t     &vport_stats_cmd, sizeof(vport_stats_cmd),\n+\t\t\t\t     &vport_stats_rsp, &out_size);\n+\tif (err || !out_size || vport_stats_rsp.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Get vport stats from fw failed, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, vport_stats_rsp.mgmt_msg_head.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmemcpy(stats, &vport_stats_rsp.stats, sizeof(*stats));\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_phy_port_stats(void *hwdev, struct hinic_phy_port_stats *stats)\n+{\n+\tstruct hinic_port_stats_info port_stats_cmd;\n+\tstruct hinic_port_stats port_stats_rsp;\n+\tu16 out_size = sizeof(port_stats_rsp);\n+\tint err;\n+\n+\tif (!hwdev || !stats) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or stats is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&port_stats_rsp, 0, sizeof(port_stats_rsp));\n+\tmemset(&port_stats_cmd, 0, sizeof(port_stats_cmd));\n+\tport_stats_cmd.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tport_stats_cmd.stats_version = HINIC_PORT_STATS_VERSION;\n+\tport_stats_cmd.stats_size = sizeof(port_stats_rsp);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_PORT_STATISTICS,\n+\t\t\t\t     &port_stats_cmd, sizeof(port_stats_cmd),\n+\t\t\t\t     &port_stats_rsp, &out_size);\n+\tif (err || !out_size || port_stats_rsp.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to get port statistics, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, port_stats_rsp.mgmt_msg_head.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmemcpy(stats, &port_stats_rsp.stats, sizeof(*stats));\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_rss_type(void *hwdev, u32 tmpl_idx, struct nic_rss_type rss_type)\n+{\n+\tstruct nic_rss_context_tbl *ctx_tbl;\n+\tstruct hinic_cmd_buf *cmd_buf;\n+\tu32 ctx = 0;\n+\tu64 out_param;\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcmd_buf = hinic_alloc_cmd_buf(hwdev);\n+\tif (!cmd_buf) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate cmd buf\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tctx |= HINIC_RSS_TYPE_SET(1, VALID) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.ipv4, IPV4) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.ipv6, IPV6) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.ipv6_ext, IPV6_EXT) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.tcp_ipv4, TCP_IPV4) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.tcp_ipv6, TCP_IPV6) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.tcp_ipv6_ext, TCP_IPV6_EXT) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.udp_ipv4, UDP_IPV4) |\n+\t\tHINIC_RSS_TYPE_SET(rss_type.udp_ipv6, UDP_IPV6);\n+\n+\tcmd_buf->size = sizeof(struct nic_rss_context_tbl);\n+\n+\tctx_tbl = (struct nic_rss_context_tbl *)cmd_buf->buf;\n+\tctx_tbl->group_index = cpu_to_be32(tmpl_idx);\n+\tctx_tbl->offset = 0;\n+\tctx_tbl->size = sizeof(u32);\n+\tctx_tbl->size = cpu_to_be32(ctx_tbl->size);\n+\tctx_tbl->rsvd = 0;\n+\tctx_tbl->ctx = cpu_to_be32(ctx);\n+\n+\t/* cfg the rss context table by command queue */\n+\terr = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,\n+\t\t\t\t     HINIC_MOD_L2NIC,\n+\t\t\t\t     HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,\n+\t\t\t\t     cmd_buf, &out_param, 0);\n+\n+\thinic_free_cmd_buf(hwdev, cmd_buf);\n+\n+\tif (err || out_param != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set rss context table\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_get_rss_type(void *hwdev, u32 tmpl_idx, struct nic_rss_type *rss_type)\n+{\n+\tstruct hinic_rss_context_table ctx_tbl;\n+\tu16 out_size = sizeof(ctx_tbl);\n+\tint err;\n+\n+\tif (!hwdev || !rss_type) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or rss_type is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tctx_tbl.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tctx_tbl.func_id = hinic_global_func_id(hwdev);\n+\tctx_tbl.template_id = (u8)tmpl_idx;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_RSS_CTX_TBL,\n+\t\t\t\t     &ctx_tbl, sizeof(ctx_tbl),\n+\t\t\t\t     &ctx_tbl, &out_size);\n+\tif (err || !out_size || ctx_tbl.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to get hash type, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, ctx_tbl.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trss_type->ipv4 = HINIC_RSS_TYPE_GET(ctx_tbl.context, IPV4);\n+\trss_type->ipv6 = HINIC_RSS_TYPE_GET(ctx_tbl.context, IPV6);\n+\trss_type->ipv6_ext = HINIC_RSS_TYPE_GET(ctx_tbl.context, IPV6_EXT);\n+\trss_type->tcp_ipv4 = HINIC_RSS_TYPE_GET(ctx_tbl.context, TCP_IPV4);\n+\trss_type->tcp_ipv6 = HINIC_RSS_TYPE_GET(ctx_tbl.context, TCP_IPV6);\n+\trss_type->tcp_ipv6_ext =\n+\t\t\tHINIC_RSS_TYPE_GET(ctx_tbl.context, TCP_IPV6_EXT);\n+\trss_type->udp_ipv4 = HINIC_RSS_TYPE_GET(ctx_tbl.context, UDP_IPV4);\n+\trss_type->udp_ipv6 = HINIC_RSS_TYPE_GET(ctx_tbl.context, UDP_IPV6);\n+\n+\treturn 0;\n+}\n+\n+int hinic_rss_set_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp)\n+{\n+\tstruct hinic_rss_template_key temp_key;\n+\tu16 out_size = sizeof(temp_key);\n+\tint err;\n+\n+\tif (!hwdev || !temp) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or temp is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&temp_key, 0, sizeof(temp_key));\n+\ttemp_key.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ttemp_key.func_id = hinic_global_func_id(hwdev);\n+\ttemp_key.template_id = (u8)tmpl_idx;\n+\tmemcpy(temp_key.key, temp, HINIC_RSS_KEY_SIZE);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL,\n+\t\t\t\t     &temp_key, sizeof(temp_key),\n+\t\t\t\t     &temp_key, &out_size);\n+\tif (err || !out_size || temp_key.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set hash key, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, temp_key.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_rss_get_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp)\n+{\n+\tstruct hinic_rss_template_key temp_key;\n+\tu16 out_size = sizeof(temp_key);\n+\tint err;\n+\n+\tif (!hwdev || !temp) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or temp is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&temp_key, 0, sizeof(temp_key));\n+\ttemp_key.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ttemp_key.func_id = hinic_global_func_id(hwdev);\n+\ttemp_key.template_id = (u8)tmpl_idx;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,\n+\t\t\t\t     &temp_key, sizeof(temp_key),\n+\t\t\t\t     &temp_key, &out_size);\n+\tif (err || !out_size || temp_key.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get hash key, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, temp_key.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemcpy(temp, temp_key.key, HINIC_RSS_KEY_SIZE);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_rss_set_hash_engine - Init rss hash function .\n+ * @hwdev: the hardware interface of a nic device\n+ * @tmpl_idx: index of rss template from NIC.\n+ * @type: hash function, such as Toeplitz or XOR.\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_rss_set_hash_engine(void *hwdev, u8 tmpl_idx, u8 type)\n+{\n+\tstruct hinic_rss_engine_type hash_type;\n+\tu16 out_size = sizeof(hash_type);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&hash_type, 0, sizeof(hash_type));\n+\thash_type.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\thash_type.func_id = hinic_global_func_id(hwdev);\n+\thash_type.hash_engine = type;\n+\thash_type.template_id = tmpl_idx;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,\n+\t\t\t\t     &hash_type, sizeof(hash_type),\n+\t\t\t\t     &hash_type, &out_size);\n+\tif (err || !out_size || hash_type.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get hash engine, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, hash_type.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_rss_set_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table)\n+{\n+\tstruct nic_rss_indirect_tbl *indir_tbl;\n+\tstruct hinic_cmd_buf *cmd_buf;\n+\tint i;\n+\tu32 *temp;\n+\tu32 indir_size;\n+\tu64 out_param;\n+\tint err;\n+\n+\tif (!hwdev || !indir_table) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or indir_table is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcmd_buf = hinic_alloc_cmd_buf(hwdev);\n+\tif (!cmd_buf) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate cmd buf\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tcmd_buf->size = sizeof(struct nic_rss_indirect_tbl);\n+\tindir_tbl = cmd_buf->buf;\n+\tindir_tbl->group_index = cpu_to_be32(tmpl_idx);\n+\n+\tfor (i = 0; i < HINIC_RSS_INDIR_SIZE; i++) {\n+\t\tindir_tbl->entry[i] = (u8)(*(indir_table + i));\n+\n+\t\tif (0x3 == (i & 0x3)) {\n+\t\t\ttemp = (u32 *)&indir_tbl->entry[i - 3];\n+\t\t\t*temp = cpu_to_be32(*temp);\n+\t\t}\n+\t}\n+\n+\t/* configure the rss indirect table by command queue */\n+\tindir_size = HINIC_RSS_INDIR_SIZE / 2;\n+\tindir_tbl->offset = 0;\n+\tindir_tbl->size = cpu_to_be32(indir_size);\n+\n+\terr = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,\n+\t\t\t\t     HINIC_MOD_L2NIC,\n+\t\t\t\t     HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,\n+\t\t\t\t     cmd_buf, &out_param, 0);\n+\tif (err || out_param != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set rss indir table\");\n+\t\terr = -EFAULT;\n+\t\tgoto free_buf;\n+\t}\n+\n+\tindir_tbl->offset = cpu_to_be32(indir_size);\n+\tindir_tbl->size = cpu_to_be32(indir_size);\n+\tmemcpy(indir_tbl->entry, &indir_tbl->entry[indir_size], indir_size);\n+\n+\terr = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,\n+\t\t\t\t     HINIC_MOD_L2NIC,\n+\t\t\t\t     HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,\n+\t\t\t\t     cmd_buf, &out_param, 0);\n+\tif (err || out_param != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set rss indir table\");\n+\t\terr = -EFAULT;\n+\t}\n+\n+free_buf:\n+\thinic_free_cmd_buf(hwdev, cmd_buf);\n+\n+\treturn err;\n+}\n+\n+int hinic_rss_get_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table)\n+{\n+\tstruct hinic_rss_indir_table rss_cfg;\n+\tu16 out_size = sizeof(rss_cfg);\n+\tint err = 0, i;\n+\n+\tif (!hwdev || !indir_table) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or indir_table is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&rss_cfg, 0, sizeof(rss_cfg));\n+\trss_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\trss_cfg.func_id = hinic_global_func_id(hwdev);\n+\trss_cfg.template_id = (u8)tmpl_idx;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev,\n+\t\t\t\t     HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL,\n+\t\t\t\t     &rss_cfg, sizeof(rss_cfg), &rss_cfg,\n+\t\t\t\t     &out_size);\n+\tif (err || !out_size || rss_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get indir table, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, rss_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thinic_be32_to_cpu(rss_cfg.indir, HINIC_RSS_INDIR_SIZE);\n+\tfor (i = 0; i < HINIC_RSS_INDIR_SIZE; i++)\n+\t\tindir_table[i] = rss_cfg.indir[i];\n+\n+\treturn 0;\n+}\n+\n+int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc)\n+{\n+\tstruct hinic_rss_config rss_cfg;\n+\tu16 out_size = sizeof(rss_cfg);\n+\tint err;\n+\n+\t/* micro code required: number of TC should be power of 2 */\n+\tif (!hwdev || !prio_tc || (tc_num & (tc_num - 1))) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or prio_tc is NULL, or tc_num: %u Not power of 2\",\n+\t\t\ttc_num);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&rss_cfg, 0, sizeof(rss_cfg));\n+\trss_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\trss_cfg.func_id = hinic_global_func_id(hwdev);\n+\trss_cfg.rss_en = rss_en;\n+\trss_cfg.template_id = tmpl_idx;\n+\trss_cfg.rq_priority_number = tc_num ? (u8)ilog2(tc_num) : 0;\n+\n+\tmemcpy(rss_cfg.prio_tc, prio_tc, HINIC_DCB_UP_MAX);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_RSS_CFG,\n+\t\t\t\t     &rss_cfg, sizeof(rss_cfg), &rss_cfg,\n+\t\t\t\t     &out_size);\n+\tif (err || !out_size || rss_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set rss cfg, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, rss_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_rss_template_alloc - get rss template id from the chip,\n+ *\t\t\t      all functions share 96 templates.\n+ * @hwdev: the pointer to the private hardware device object\n+ * @tmpl_idx: index of rss template from chip.\n+ * Return: 0 on success and stats is filled, negative error value otherwise.\n+ **/\n+int hinic_rss_template_alloc(void *hwdev, u8 *tmpl_idx)\n+{\n+\tstruct hinic_rss_template_mgmt template_mgmt;\n+\tu16 out_size = sizeof(template_mgmt);\n+\tint err;\n+\n+\tif (!hwdev || !tmpl_idx) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev or tmpl_idx is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&template_mgmt, 0, sizeof(template_mgmt));\n+\ttemplate_mgmt.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ttemplate_mgmt.func_id = hinic_global_func_id(hwdev);\n+\ttemplate_mgmt.cmd = NIC_RSS_CMD_TEMP_ALLOC;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_RSS_TEMP_MGR,\n+\t\t\t\t     &template_mgmt, sizeof(template_mgmt),\n+\t\t\t\t     &template_mgmt, &out_size);\n+\tif (err || !out_size || template_mgmt.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to alloc rss template, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, template_mgmt.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*tmpl_idx = template_mgmt.template_id;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_rss_template_alloc - free rss template id to the chip\n+ * @hwdev: the hardware interface of a nic device\n+ * @tmpl_idx: index of rss template from NIC.\n+ * Return: 0 on success and stats is filled, negative error value otherwise.\n+ **/\n+int hinic_rss_template_free(void *hwdev, u8 tmpl_idx)\n+{\n+\tstruct hinic_rss_template_mgmt template_mgmt;\n+\tu16 out_size = sizeof(template_mgmt);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&template_mgmt, 0, sizeof(template_mgmt));\n+\ttemplate_mgmt.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\ttemplate_mgmt.func_id = hinic_global_func_id(hwdev);\n+\ttemplate_mgmt.template_id = tmpl_idx;\n+\ttemplate_mgmt.cmd = NIC_RSS_CMD_TEMP_FREE;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_RSS_TEMP_MGR,\n+\t\t\t\t     &template_mgmt, sizeof(template_mgmt),\n+\t\t\t\t     &template_mgmt, &out_size);\n+\tif (err || !out_size || template_mgmt.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to free rss template, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, template_mgmt.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_set_rx_vhd_mode - change rx buffer size after initialization,\n+ * @hwdev: the hardware interface of a nic device\n+ * @mode: not needed.\n+ * @rx_buf_sz: receive buffer size.\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_set_rx_vhd_mode(void *hwdev, u16 vhd_mode, u16 rx_buf_sz)\n+{\n+\tstruct hinic_set_vhd_mode vhd_mode_cfg;\n+\tu16 out_size = sizeof(vhd_mode_cfg);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&vhd_mode_cfg, 0, sizeof(vhd_mode_cfg));\n+\n+\tvhd_mode_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tvhd_mode_cfg.func_id = hinic_global_func_id(hwdev);\n+\tvhd_mode_cfg.vhd_type = vhd_mode;\n+\tvhd_mode_cfg.rx_wqe_buffer_size = rx_buf_sz;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_VHD_CFG,\n+\t\t\t\t     &vhd_mode_cfg, sizeof(vhd_mode_cfg),\n+\t\t\t\t     &vhd_mode_cfg, &out_size);\n+\tif (err || !out_size || vhd_mode_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set vhd mode, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, vhd_mode_cfg.mgmt_msg_head.status, out_size);\n+\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_rx_mode(void *hwdev, u32 enable)\n+{\n+\tstruct hinic_rx_mode_config rx_mode_cfg;\n+\tu16 out_size = sizeof(rx_mode_cfg);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&rx_mode_cfg, 0, sizeof(rx_mode_cfg));\n+\trx_mode_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\trx_mode_cfg.func_id = hinic_global_func_id(hwdev);\n+\trx_mode_cfg.rx_mode = enable;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_RX_MODE,\n+\t\t\t\t     &rx_mode_cfg, sizeof(rx_mode_cfg),\n+\t\t\t\t     &rx_mode_cfg, &out_size);\n+\tif (err || !out_size || rx_mode_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set rx mode, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, rx_mode_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_rx_csum_offload(void *hwdev, u32 en)\n+{\n+\tstruct hinic_checksum_offload rx_csum_cfg;\n+\tu16 out_size = sizeof(rx_csum_cfg);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&rx_csum_cfg, 0, sizeof(rx_csum_cfg));\n+\trx_csum_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\trx_csum_cfg.func_id = hinic_global_func_id(hwdev);\n+\trx_csum_cfg.rx_csum_offload = en;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_RX_CSUM,\n+\t\t\t\t     &rx_csum_cfg, sizeof(rx_csum_cfg),\n+\t\t\t\t     &rx_csum_cfg, &out_size);\n+\tif (err || !out_size || rx_csum_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set rx csum offload, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, rx_csum_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_rx_lro(void *hwdev, u8 ipv4_en, u8 ipv6_en, u8 max_wqe_num)\n+{\n+\tstruct hinic_lro_config lro_cfg;\n+\tu16 out_size = sizeof(lro_cfg);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&lro_cfg, 0, sizeof(lro_cfg));\n+\tlro_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tlro_cfg.func_id = hinic_global_func_id(hwdev);\n+\tlro_cfg.lro_ipv4_en = ipv4_en;\n+\tlro_cfg.lro_ipv6_en = ipv6_en;\n+\tlro_cfg.lro_max_wqe_num = max_wqe_num;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_LRO,\n+\t\t\t\t     &lro_cfg, sizeof(lro_cfg), &lro_cfg,\n+\t\t\t\t     &out_size);\n+\tif (err || !out_size || lro_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to set lro offload, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, lro_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_anti_attack(void *hwdev, bool enable)\n+{\n+\tstruct hinic_port_anti_attack_rate rate;\n+\tu16 out_size = sizeof(rate);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&rate, 0, sizeof(rate));\n+\trate.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\trate.func_id = hinic_global_func_id(hwdev);\n+\trate.enable = enable;\n+\trate.cir = ANTI_ATTACK_DEFAULT_CIR;\n+\trate.xir = ANTI_ATTACK_DEFAULT_XIR;\n+\trate.cbs = ANTI_ATTACK_DEFAULT_CBS;\n+\trate.xbs = ANTI_ATTACK_DEFAULT_XBS;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE,\n+\t\t\t\t     &rate, sizeof(rate), &rate,\n+\t\t\t\t     &out_size);\n+\tif (err || !out_size || rate.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"can't %s port Anti-Attack rate limit, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\t(enable ? \"enable\" : \"disable\"), err,\n+\t\t\trate.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Set autoneg status and restart port link status */\n+int hinic_reset_port_link_cfg(void *hwdev)\n+{\n+\tstruct hinic_reset_link_cfg reset_cfg;\n+\tu16 out_size = sizeof(reset_cfg);\n+\tint err;\n+\n+\tmemset(&reset_cfg, 0, sizeof(reset_cfg));\n+\treset_cfg.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\treset_cfg.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_RESET_LINK_CFG,\n+\t\t\t\t     &reset_cfg, sizeof(reset_cfg),\n+\t\t\t\t     &reset_cfg, &out_size);\n+\tif (err || !out_size || reset_cfg.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Reset port link configure failed, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, reset_cfg.mgmt_msg_head.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int hinic_set_fast_recycle_mode(void *hwdev, u8 mode)\n+{\n+\tstruct hinic_fast_recycled_mode fast_recycled_mode;\n+\tu16 out_size = sizeof(fast_recycled_mode);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&fast_recycled_mode, 0, sizeof(fast_recycled_mode));\n+\tfast_recycled_mode.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tfast_recycled_mode.func_id = hinic_global_func_id(hwdev);\n+\tfast_recycled_mode.fast_recycled_mode = mode;\n+\n+\terr = hinic_msg_to_mgmt_sync(hwdev, HINIC_MOD_COMM,\n+\t\t\t\t     HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET,\n+\t\t\t\t     &fast_recycled_mode,\n+\t\t\t\t     sizeof(fast_recycled_mode),\n+\t\t\t\t     &fast_recycled_mode, &out_size, 0);\n+\tif (err || fast_recycled_mode.mgmt_msg_head.status || !out_size) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set recycle mode, ret = %d\",\n+\t\t\tfast_recycled_mode.mgmt_msg_head.status);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void hinic_clear_vport_stats(struct hinic_hwdev *hwdev)\n+{\n+\tstruct hinic_clear_vport_stats clear_vport_stats;\n+\tu16 out_size = sizeof(clear_vport_stats);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tmemset(&clear_vport_stats, 0, sizeof(clear_vport_stats));\n+\tclear_vport_stats.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tclear_vport_stats.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_CLEAN_VPORT_STAT,\n+\t\t\t\t     &clear_vport_stats,\n+\t\t\t\t     sizeof(clear_vport_stats),\n+\t\t\t\t     &clear_vport_stats, &out_size);\n+\tif (err || !out_size || clear_vport_stats.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to clear vport statistics, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, clear_vport_stats.mgmt_msg_head.status, out_size);\n+\t}\n+}\n+\n+void hinic_clear_phy_port_stats(struct hinic_hwdev *hwdev)\n+{\n+\tstruct hinic_clear_port_stats clear_phy_port_stats;\n+\tu16 out_size = sizeof(clear_phy_port_stats);\n+\tint err;\n+\n+\tif (!hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwdev is NULL\");\n+\t\treturn;\n+\t}\n+\n+\tmemset(&clear_phy_port_stats, 0, sizeof(clear_phy_port_stats));\n+\tclear_phy_port_stats.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tclear_phy_port_stats.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev,\n+\t\t\t\t     HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,\n+\t\t\t\t     &clear_phy_port_stats,\n+\t\t\t\t     sizeof(clear_phy_port_stats),\n+\t\t\t\t     &clear_phy_port_stats, &out_size);\n+\tif (err || !out_size || clear_phy_port_stats.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to clear phy port statistics, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, clear_phy_port_stats.mgmt_msg_head.status,\n+\t\t\tout_size);\n+\t}\n+}\n+\n+int hinic_set_link_status_follow(void *hwdev,\n+\t\t\t\t enum hinic_link_follow_status status)\n+{\n+\tstruct hinic_set_link_follow follow;\n+\tu16 out_size = sizeof(follow);\n+\tint err;\n+\n+\tif (!hwdev)\n+\t\treturn -EINVAL;\n+\n+\tif (status >= HINIC_LINK_FOLLOW_STATUS_MAX) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Invalid link follow status: %d\", status);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(&follow, 0, sizeof(follow));\n+\tfollow.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tfollow.func_id = hinic_global_func_id(hwdev);\n+\tfollow.follow_status = status;\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_SET_LINK_FOLLOW,\n+\t\t\t\t     &follow, sizeof(follow),\n+\t\t\t\t     &follow, &out_size);\n+\tif ((follow.mgmt_msg_head.status != HINIC_MGMT_CMD_UNSUPPORTED &&\n+\t     follow.mgmt_msg_head.status) || err || !out_size) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to set link status follow phy port status, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, follow.mgmt_msg_head.status, out_size);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn follow.mgmt_msg_head.status;\n+}\n+\n+int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised)\n+{\n+\tstruct hinic_link_mode_cmd link_mode;\n+\tu16 out_size = sizeof(link_mode);\n+\tint err;\n+\n+\tif (!hwdev || !supported || !advertised)\n+\t\treturn -EINVAL;\n+\n+\tmemset(&link_mode, 0, sizeof(link_mode));\n+\tlink_mode.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tlink_mode.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_GET_LINK_MODE,\n+\t\t\t\t     &link_mode, sizeof(link_mode),\n+\t\t\t\t     &link_mode, &out_size);\n+\tif (err || !out_size || link_mode.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Failed to get link mode, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, link_mode.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*supported = link_mode.supported;\n+\t*advertised = link_mode.advertised;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * hinic_flush_qp_res - Flush tx && rx chip resources in case of set vport fake\n+ * failed when device start.\n+ * @hwdev: the hardware interface of a nic device\n+ * Return: 0 on success, negative error value otherwise.\n+ **/\n+int hinic_flush_qp_res(void *hwdev)\n+{\n+\tstruct hinic_clear_qp_resource qp_res;\n+\tu16 out_size = sizeof(qp_res);\n+\tint err;\n+\n+\tmemset(&qp_res, 0, sizeof(qp_res));\n+\tqp_res.mgmt_msg_head.resp_aeq_num = HINIC_AEQ1;\n+\tqp_res.func_id = hinic_global_func_id(hwdev);\n+\n+\terr = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_CLEAR_QP_RES,\n+\t\t\t\t     &qp_res, sizeof(qp_res), &qp_res,\n+\t\t\t\t     &out_size);\n+\tif (err || !out_size || qp_res.mgmt_msg_head.status) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to clear sq resources, err: %d, status: 0x%x, out size: 0x%x\",\n+\t\t\terr, qp_res.mgmt_msg_head.status, out_size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/hinic/base/hinic_pmd_niccfg.h b/drivers/net/hinic/base/hinic_pmd_niccfg.h\nnew file mode 100644\nindex 000000000..eaa3f2aba\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_pmd_niccfg.h\n@@ -0,0 +1,658 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PMD_NICCFG_H_\n+#define _HINIC_PMD_NICCFG_H_\n+\n+#define OS_VF_ID_TO_HW(os_vf_id) ((os_vf_id) + 1)\n+#define HW_VF_ID_TO_OS(hw_vf_id) ((hw_vf_id) - 1)\n+\n+#define HINIC_VLAN_PRIORITY_SHIFT\t13\n+\n+#define HINIC_RSS_INDIR_SIZE\t\t256\n+#define HINIC_DCB_TC_MAX\t\t0x8\n+#define HINIC_DCB_UP_MAX\t\t0x8\n+#define HINIC_DCB_PG_MAX\t\t0x8\n+#define HINIC_RSS_KEY_SIZE\t\t40\n+\n+#define HINIC_MAX_NUM_RQ\t\t64\n+\n+#define ANTI_ATTACK_DEFAULT_CIR\t\t500000\n+#define ANTI_ATTACK_DEFAULT_XIR\t\t600000\n+#define ANTI_ATTACK_DEFAULT_CBS\t\t10000000\n+#define ANTI_ATTACK_DEFAULT_XBS\t\t12000000\n+\n+#define NIC_RSS_INDIR_SIZE\t\t256\n+#define NIC_RSS_KEY_SIZE\t\t40\n+#define NIC_RSS_CMD_TEMP_ALLOC\t\t0x01\n+#define NIC_RSS_CMD_TEMP_FREE\t\t0x02\n+#define NIC_DCB_UP_MAX\t\t\t0x8\n+\n+enum hinic_rss_hash_type {\n+\tHINIC_RSS_HASH_ENGINE_TYPE_XOR = 0,\n+\tHINIC_RSS_HASH_ENGINE_TYPE_TOEP,\n+\n+\tHINIC_RSS_HASH_ENGINE_TYPE_MAX,\n+};\n+\n+struct nic_port_info {\n+\tu8\tport_type;\n+\tu8\tautoneg_cap;\n+\tu8\tautoneg_state;\n+\tu8\tduplex;\n+\tu8\tspeed;\n+};\n+\n+enum nic_speed_level {\n+\tLINK_SPEED_10MB = 0,\n+\tLINK_SPEED_100MB,\n+\tLINK_SPEED_1GB,\n+\tLINK_SPEED_10GB,\n+\tLINK_SPEED_25GB,\n+\tLINK_SPEED_40GB,\n+\tLINK_SPEED_100GB,\n+\tLINK_SPEED_MAX\n+};\n+\n+enum hinic_link_status {\n+\tHINIC_LINK_DOWN = 0,\n+\tHINIC_LINK_UP\n+};\n+\n+struct hinic_up_ets_cfg {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu8 port_id;\n+\tu8 rsvd1[3];\n+\tu8 up_tc[HINIC_DCB_UP_MAX];\n+\tu8 pg_bw[HINIC_DCB_PG_MAX];\n+\tu8 pgid[HINIC_DCB_UP_MAX];\n+\tu8 up_bw[HINIC_DCB_UP_MAX];\n+\tu8 prio[HINIC_DCB_PG_MAX];\n+};\n+\n+struct nic_pause_config {\n+\tu32 auto_neg;\n+\tu32 rx_pause;\n+\tu32 tx_pause;\n+};\n+\n+struct nic_rss_type {\n+\tu8 tcp_ipv6_ext;\n+\tu8 ipv6_ext;\n+\tu8 tcp_ipv6;\n+\tu8 ipv6;\n+\tu8 tcp_ipv4;\n+\tu8 ipv4;\n+\tu8 udp_ipv6;\n+\tu8 udp_ipv4;\n+};\n+\n+enum hinic_rx_mod {\n+\tHINIC_RX_MODE_UC = 1 << 0,\n+\tHINIC_RX_MODE_MC = 1 << 1,\n+\tHINIC_RX_MODE_BC = 1 << 2,\n+\tHINIC_RX_MODE_MC_ALL = 1 << 3,\n+\tHINIC_RX_MODE_PROMISC = 1 << 4,\n+};\n+\n+enum hinic_link_mode {\n+\tHINIC_10GE_BASE_KR = 0,\n+\tHINIC_40GE_BASE_KR4 = 1,\n+\tHINIC_40GE_BASE_CR4 = 2,\n+\tHINIC_100GE_BASE_KR4 = 3,\n+\tHINIC_100GE_BASE_CR4 = 4,\n+\tHINIC_25GE_BASE_KR_S = 5,\n+\tHINIC_25GE_BASE_CR_S = 6,\n+\tHINIC_25GE_BASE_KR = 7,\n+\tHINIC_25GE_BASE_CR = 8,\n+\tHINIC_GE_BASE_KX = 9,\n+\tHINIC_LINK_MODE_NUMBERS,\n+\n+\tHINIC_SUPPORTED_UNKNOWN = 0xFFFF,\n+};\n+\n+#define HINIC_DEFAULT_RX_MODE\t(HINIC_RX_MODE_UC | HINIC_RX_MODE_MC |\t\\\n+\t\t\t\tHINIC_RX_MODE_BC)\n+\n+#define HINIC_MAX_MTU_SIZE\t\t(9600)\n+#define HINIC_MIN_MTU_SIZE\t\t(256)\n+\n+/* MIN_MTU + ETH_HLEN + CRC (256+14+4) */\n+#define HINIC_MIN_FRAME_SIZE\t\t274\n+\n+/* MAX_MTU + ETH_HLEN + CRC + VLAN(9600+14+4+4) */\n+#define HINIC_MAX_JUMBO_FRAME_SIZE\t(9622)\n+\n+#define HINIC_PORT_DISABLE\t\t0x0\n+#define HINIC_PORT_ENABLE\t\t0x3\n+\n+struct hinic_vport_stats {\n+\tu64 tx_unicast_pkts_vport;\n+\tu64 tx_unicast_bytes_vport;\n+\tu64 tx_multicast_pkts_vport;\n+\tu64 tx_multicast_bytes_vport;\n+\tu64 tx_broadcast_pkts_vport;\n+\tu64 tx_broadcast_bytes_vport;\n+\n+\tu64 rx_unicast_pkts_vport;\n+\tu64 rx_unicast_bytes_vport;\n+\tu64 rx_multicast_pkts_vport;\n+\tu64 rx_multicast_bytes_vport;\n+\tu64 rx_broadcast_pkts_vport;\n+\tu64 rx_broadcast_bytes_vport;\n+\n+\tu64 tx_discard_vport;\n+\tu64 rx_discard_vport;\n+\tu64 tx_err_vport;\n+\tu64 rx_err_vport; /* rx checksum err pkts in ucode */\n+};\n+\n+struct hinic_phy_port_stats {\n+\tu64 mac_rx_total_pkt_num;\n+\tu64 mac_rx_total_oct_num;\n+\tu64 mac_rx_bad_pkt_num;\n+\tu64 mac_rx_bad_oct_num;\n+\tu64 mac_rx_good_pkt_num;\n+\tu64 mac_rx_good_oct_num;\n+\tu64 mac_rx_uni_pkt_num;\n+\tu64 mac_rx_multi_pkt_num;\n+\tu64 mac_rx_broad_pkt_num;\n+\n+\tu64 mac_tx_total_pkt_num;\n+\tu64 mac_tx_total_oct_num;\n+\tu64 mac_tx_bad_pkt_num;\n+\tu64 mac_tx_bad_oct_num;\n+\tu64 mac_tx_good_pkt_num;\n+\tu64 mac_tx_good_oct_num;\n+\tu64 mac_tx_uni_pkt_num;\n+\tu64 mac_tx_multi_pkt_num;\n+\tu64 mac_tx_broad_pkt_num;\n+\n+\tu64 mac_rx_fragment_pkt_num;\n+\tu64 mac_rx_undersize_pkt_num;\n+\tu64 mac_rx_undermin_pkt_num;\n+\tu64 mac_rx_64_oct_pkt_num;\n+\tu64 mac_rx_65_127_oct_pkt_num;\n+\tu64 mac_rx_128_255_oct_pkt_num;\n+\tu64 mac_rx_256_511_oct_pkt_num;\n+\tu64 mac_rx_512_1023_oct_pkt_num;\n+\tu64 mac_rx_1024_1518_oct_pkt_num;\n+\tu64 mac_rx_1519_2047_oct_pkt_num;\n+\tu64 mac_rx_2048_4095_oct_pkt_num;\n+\tu64 mac_rx_4096_8191_oct_pkt_num;\n+\tu64 mac_rx_8192_9216_oct_pkt_num;\n+\tu64 mac_rx_9217_12287_oct_pkt_num;\n+\tu64 mac_rx_12288_16383_oct_pkt_num;\n+\tu64 mac_rx_1519_max_bad_pkt_num;\n+\tu64 mac_rx_1519_max_good_pkt_num;\n+\tu64 mac_rx_oversize_pkt_num;\n+\tu64 mac_rx_jabber_pkt_num;\n+\n+\tu64 mac_rx_mac_pause_num;\n+\tu64 mac_rx_pfc_pkt_num;\n+\tu64 mac_rx_pfc_pri0_pkt_num;\n+\tu64 mac_rx_pfc_pri1_pkt_num;\n+\tu64 mac_rx_pfc_pri2_pkt_num;\n+\tu64 mac_rx_pfc_pri3_pkt_num;\n+\tu64 mac_rx_pfc_pri4_pkt_num;\n+\tu64 mac_rx_pfc_pri5_pkt_num;\n+\tu64 mac_rx_pfc_pri6_pkt_num;\n+\tu64 mac_rx_pfc_pri7_pkt_num;\n+\tu64 mac_rx_mac_control_pkt_num;\n+\tu64 mac_rx_y1731_pkt_num;\n+\tu64 mac_rx_sym_err_pkt_num;\n+\tu64 mac_rx_fcs_err_pkt_num;\n+\tu64 mac_rx_send_app_good_pkt_num;\n+\tu64 mac_rx_send_app_bad_pkt_num;\n+\n+\tu64 mac_tx_fragment_pkt_num;\n+\tu64 mac_tx_undersize_pkt_num;\n+\tu64 mac_tx_undermin_pkt_num;\n+\tu64 mac_tx_64_oct_pkt_num;\n+\tu64 mac_tx_65_127_oct_pkt_num;\n+\tu64 mac_tx_128_255_oct_pkt_num;\n+\tu64 mac_tx_256_511_oct_pkt_num;\n+\tu64 mac_tx_512_1023_oct_pkt_num;\n+\tu64 mac_tx_1024_1518_oct_pkt_num;\n+\tu64 mac_tx_1519_2047_oct_pkt_num;\n+\tu64 mac_tx_2048_4095_oct_pkt_num;\n+\tu64 mac_tx_4096_8191_oct_pkt_num;\n+\tu64 mac_tx_8192_9216_oct_pkt_num;\n+\tu64 mac_tx_9217_12287_oct_pkt_num;\n+\tu64 mac_tx_12288_16383_oct_pkt_num;\n+\tu64 mac_tx_1519_max_bad_pkt_num;\n+\tu64 mac_tx_1519_max_good_pkt_num;\n+\tu64 mac_tx_oversize_pkt_num;\n+\tu64 mac_trans_jabber_pkt_num;\n+\n+\tu64 mac_tx_mac_pause_num;\n+\tu64 mac_tx_pfc_pkt_num;\n+\tu64 mac_tx_pfc_pri0_pkt_num;\n+\tu64 mac_tx_pfc_pri1_pkt_num;\n+\tu64 mac_tx_pfc_pri2_pkt_num;\n+\tu64 mac_tx_pfc_pri3_pkt_num;\n+\tu64 mac_tx_pfc_pri4_pkt_num;\n+\tu64 mac_tx_pfc_pri5_pkt_num;\n+\tu64 mac_tx_pfc_pri6_pkt_num;\n+\tu64 mac_tx_pfc_pri7_pkt_num;\n+\tu64 mac_tx_mac_control_pkt_num;\n+\tu64 mac_tx_y1731_pkt_num;\n+\tu64 mac_tx_1588_pkt_num;\n+\tu64 mac_tx_err_all_pkt_num;\n+\tu64 mac_tx_from_app_good_pkt_num;\n+\tu64 mac_tx_from_app_bad_pkt_num;\n+\n+\tu64 rx_higig2_ext_pkts_port;\n+\tu64 rx_higig2_message_pkts_port;\n+\tu64 rx_higig2_error_pkts_port;\n+\tu64 rx_higig2_cpu_ctrl_pkts_port;\n+\tu64 rx_higig2_unicast_pkts_port;\n+\tu64 rx_higig2_broadcast_pkts_port;\n+\tu64 rx_higig2_l2_multicast_pkts;\n+\tu64 rx_higig2_l3_multicast_pkts;\n+\n+\tu64 tx_higig2_message_pkts_port;\n+\tu64 tx_higig2_ext_pkts_port;\n+\tu64 tx_higig2_cpu_ctrl_pkts_port;\n+\tu64 tx_higig2_unicast_pkts_port;\n+\tu64 tx_higig2_broadcast_pkts_port;\n+\tu64 tx_higig2_l2_multicast_pkts;\n+\tu64 tx_higig2_l3_multicast_pkts;\n+};\n+\n+enum hinic_link_follow_status {\n+\tHINIC_LINK_FOLLOW_DEFAULT,\n+\tHINIC_LINK_FOLLOW_PORT,\n+\tHINIC_LINK_FOLLOW_SEPARATE,\n+\tHINIC_LINK_FOLLOW_STATUS_MAX,\n+};\n+\n+#define HINIC_PORT_STATS_VERSION\t0\n+struct hinic_port_stats_info {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16 func_id;\n+\tu16 rsvd1;\n+\tu32 stats_version;\n+\tu32 stats_size;\n+};\n+\n+struct hinic_port_stats {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tstruct hinic_phy_port_stats stats;\n+};\n+\n+struct hinic_cmd_vport_stats {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tstruct hinic_vport_stats stats;\n+};\n+\n+struct hinic_clear_port_stats {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16 func_id;\n+\tu16 rsvd;\n+\tu32  stats_version;\n+\tu32  stats_size;\n+};\n+\n+struct hinic_clear_vport_stats {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16 func_id;\n+\tu16 rsvd;\n+\tu32  stats_version;\n+\tu32  stats_size;\n+};\n+\n+struct hinic_fast_recycled_mode {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16 func_id;\n+\t/*\n+\t * 1: enable fast recycle, available in dpdk mode,\n+\t * 0: normal mode, available in kernel nic mode\n+\t */\n+\tu8 fast_recycled_mode;\n+\tu8 rsvd1;\n+};\n+\n+struct hinic_function_table {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trx_wqe_buf_size;\n+\tu32\tmtu;\n+};\n+\n+struct hinic_cmd_qpn {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\tbase_qpn;\n+};\n+\n+struct hinic_port_mac_set {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\tvlan_id;\n+\tu16\trsvd1;\n+\tu8\tmac[ETH_ALEN];\n+};\n+\n+struct hinic_port_mac_update {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\tvlan_id;\n+\tu16\trsvd1;\n+\tu8\told_mac[ETH_ALEN];\n+\tu16\trsvd2;\n+\tu8\tnew_mac[ETH_ALEN];\n+};\n+\n+struct hinic_vport_state {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu8\tstate;\n+\tu8\trsvd2[3];\n+};\n+\n+struct hinic_port_state {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu8\tstate;\n+\tu8\trsvd1[3];\n+};\n+\n+struct hinic_mtu {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu32\tmtu;\n+};\n+\n+struct hinic_get_link {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\tlink_status;\n+\tu8\trsvd1;\n+};\n+\n+#define HINIC_DEFAUT_PAUSE_CONFIG 1\n+struct hinic_pause_config {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu32\tauto_neg;\n+\tu32\trx_pause;\n+\tu32\ttx_pause;\n+};\n+\n+struct hinic_port_info {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu8\tport_type;\n+\tu8\tautoneg_cap;\n+\tu8\tautoneg_state;\n+\tu8\tduplex;\n+\tu8\tspeed;\n+\tu8\tresv2[3];\n+};\n+\n+struct hinic_tso_config {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu8\ttso_en;\n+\tu8\tresv2[3];\n+};\n+\n+struct hinic_lro_config {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu8\tlro_ipv4_en;\n+\tu8\tlro_ipv6_en;\n+\tu8\tlro_max_wqe_num;\n+\tu8\tresv2[13];\n+};\n+\n+struct hinic_checksum_offload {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu32\trx_csum_offload;\n+};\n+\n+struct hinic_rx_mode_config {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu32\trx_mode;\n+};\n+\n+/* rss */\n+struct nic_rss_indirect_tbl {\n+\tu32 group_index;\n+\tu32 offset;\n+\tu32 size;\n+\tu32 rsvd;\n+\tu8 entry[NIC_RSS_INDIR_SIZE];\n+};\n+\n+struct nic_rss_context_tbl {\n+\tu32 group_index;\n+\tu32 offset;\n+\tu32 size;\n+\tu32 rsvd;\n+\tu32 ctx;\n+};\n+\n+struct hinic_rss_config {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\trss_en;\n+\tu8\ttemplate_id;\n+\tu8\trq_priority_number;\n+\tu8\trsvd1[3];\n+\tu8\tprio_tc[NIC_DCB_UP_MAX];\n+};\n+\n+struct hinic_rss_template_mgmt {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\tcmd;\n+\tu8\ttemplate_id;\n+\tu8\trsvd1[4];\n+};\n+\n+struct hinic_rss_indir_table {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\ttemplate_id;\n+\tu8\trsvd1;\n+\tu8\tindir[NIC_RSS_INDIR_SIZE];\n+};\n+\n+struct hinic_rss_template_key {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\ttemplate_id;\n+\tu8\trsvd1;\n+\tu8\tkey[NIC_RSS_KEY_SIZE];\n+};\n+\n+struct hinic_rss_engine_type {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\ttemplate_id;\n+\tu8\thash_engine;\n+\tu8\trsvd1[4];\n+};\n+\n+struct hinic_rss_context_table {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu8\ttemplate_id;\n+\tu8\trsvd1;\n+\tu32\tcontext;\n+};\n+\n+struct hinic_reset_link_cfg {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+};\n+\n+struct hinic_set_vhd_mode {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16 func_id;\n+\tu16 vhd_type;\n+\tu16 rx_wqe_buffer_size;\n+\tu16 rsvd;\n+};\n+\n+struct hinic_set_link_follow {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd0;\n+\tu8\tfollow_status;\n+\tu8\trsvd1[3];\n+};\n+\n+struct hinic_link_mode_cmd {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+\tu16\tsupported;\t/* 0xFFFF represent Invalid value */\n+\tu16\tadvertised;\n+};\n+\n+struct hinic_clear_qp_resource {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\trsvd1;\n+};\n+\n+/* set physical port Anti-Attack rate */\n+struct hinic_port_anti_attack_rate {\n+\tstruct hinic_mgmt_msg_head mgmt_msg_head;\n+\n+\tu16\tfunc_id;\n+\tu16\tenable; /* 1: enable rate-limiting, 0: disable rate-limiting */\n+\tu32\tcir;\t/* Committed Information Rate */\n+\tu32\txir;\t/* eXtended Information Rate */\n+\tu32\tcbs;\t/* Committed Burst Size */\n+\tu32\txbs;\t/* eXtended Burst Size */\n+};\n+\n+int hinic_set_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id);\n+\n+int hinic_del_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id);\n+\n+int hinic_update_mac(void *hwdev, u8 *old_mac, u8 *new_mac, u16 vlan_id,\n+\t\t     u16 func_id);\n+\n+int hinic_get_default_mac(void *hwdev, u8 *mac_addr);\n+\n+int hinic_set_port_mtu(void *hwdev, u32 new_mtu);\n+\n+int hinic_set_vport_enable(void *hwdev, bool enable);\n+\n+int hinic_set_port_enable(void *hwdev, bool enable);\n+\n+int hinic_get_link_status(void *hwdev, u8 *link_state);\n+\n+int hinic_get_port_info(void *hwdev, struct nic_port_info *port_info);\n+\n+int hinic_set_rx_vhd_mode(void *hwdev, u16 vhd_mode, u16 rx_buf_sz);\n+\n+int hinic_set_pause_config(void *hwdev, struct nic_pause_config nic_pause);\n+\n+int hinic_reset_port_link_cfg(void *hwdev);\n+\n+int hinic_dcb_set_ets(void *hwdev, u8 *up_tc, u8 *pg_bw, u8 *pgid, u8 *up_bw,\n+\t\t      u8 *prio);\n+\n+int hinic_set_anti_attack(void *hwdev, bool enable);\n+\n+/* offload feature */\n+int hinic_set_rx_lro(void *hwdev, u8 ipv4_en, u8 ipv6_en, u8 max_wqe_num);\n+\n+int hinic_get_vport_stats(void *hwdev, struct hinic_vport_stats *stats);\n+\n+int hinic_get_phy_port_stats(void *hwdev, struct hinic_phy_port_stats *stats);\n+\n+/* rss */\n+int hinic_set_rss_type(void *hwdev, u32 tmpl_idx,\n+\t\t       struct nic_rss_type rss_type);\n+\n+int hinic_get_rss_type(void *hwdev, u32 tmpl_idx,\n+\t\t       struct nic_rss_type *rss_type);\n+\n+int hinic_rss_set_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp);\n+\n+int hinic_rss_get_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp);\n+\n+int hinic_rss_set_hash_engine(void *hwdev, u8 tmpl_idx, u8 type);\n+\n+int hinic_rss_get_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table);\n+\n+int hinic_rss_set_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table);\n+\n+int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc);\n+\n+int hinic_rss_template_alloc(void *hwdev, u8 *tmpl_idx);\n+\n+int hinic_rss_template_free(void *hwdev, u8 tmpl_idx);\n+\n+int hinic_set_rx_mode(void *hwdev, u32 enable);\n+\n+int hinic_set_rx_csum_offload(void *hwdev, u32 en);\n+\n+int hinic_set_link_status_follow(void *hwdev,\n+\t\t\t\t enum hinic_link_follow_status status);\n+\n+int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised);\n+\n+int hinic_flush_qp_res(void *hwdev);\n+\n+int hinic_init_function_table(void *hwdev, u16 rx_buf_sz);\n+\n+int hinic_set_fast_recycle_mode(void *hwdev, u8 mode);\n+\n+int hinic_get_base_qpn(void *hwdev, u16 *global_qpn);\n+\n+void hinic_clear_vport_stats(struct hinic_hwdev *hwdev);\n+\n+void hinic_clear_phy_port_stats(struct hinic_hwdev *hwdev);\n+\n+#endif /* _HINIC_PMD_NICCFG_H_ */\n",
    "prefixes": [
        "v5",
        "08/15"
    ]
}