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GET /api/patches/55010/?format=api
{ "id": 55010, "url": "http://patches.dpdk.org/api/patches/55010/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/aaa912bda9d42422776822dd29620d974827f713.1560958308.git.xuanziyang2@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<aaa912bda9d42422776822dd29620d974827f713.1560958308.git.xuanziyang2@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/aaa912bda9d42422776822dd29620d974827f713.1560958308.git.xuanziyang2@huawei.com", "date": "2019-06-19T15:50:39", "name": "[v5,02/15] net/hinic/base: add HW interfaces of bar operation", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "26539bed4169839a48ef8deb53a882888bb82946", "submitter": { "id": 1321, "url": "http://patches.dpdk.org/api/people/1321/?format=api", "name": "Ziyang Xuan", "email": "xuanziyang2@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/aaa912bda9d42422776822dd29620d974827f713.1560958308.git.xuanziyang2@huawei.com/mbox/", "series": [ { "id": 5084, "url": "http://patches.dpdk.org/api/series/5084/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5084", "date": "2019-06-19T15:45:20", "name": "A new net PMD - hinic", "version": 5, "mbox": "http://patches.dpdk.org/series/5084/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55010/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E3BB61D057;\n\tWed, 19 Jun 2019 17:41:41 +0200 (CEST)", "from huawei.com (szxga04-in.huawei.com [45.249.212.190])\n\tby dpdk.org (Postfix) with ESMTP id 5865E1C449\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 17:38:57 +0200 (CEST)", "from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id ECFA6A3E81D935229DB1\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 23:38:49 +0800 (CST)", "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP\n\tServer id 14.3.439.0; Wed, 19 Jun 2019 23:38:39 +0800" ], "From": "Ziyang Xuan <xuanziyang2@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <shahar.belkar@huawei.com>,\n\t<luoxianjun@huawei.com>, Ziyang Xuan <xuanziyang2@huawei.com>", "Date": "Wed, 19 Jun 2019 23:50:39 +0800", "Message-ID": "<aaa912bda9d42422776822dd29620d974827f713.1560958308.git.xuanziyang2@huawei.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<cover.1560958308.git.xuanziyang2@huawei.com>", "References": "<cover.1560958308.git.xuanziyang2@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.175.119.39]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v5 02/15] net/hinic/base: add HW interfaces of\n\tbar operation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds some HW interfaces for bar operatioin interfaces,\nincluding: mapped bar address geeting, HW attributes getting,\nmsi-x reg operation, function type getting and so on.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/base/hinic_pmd_hwif.c | 474 ++++++++++++++++++++++++\n drivers/net/hinic/base/hinic_pmd_hwif.h | 119 ++++++\n 2 files changed, 593 insertions(+)\n create mode 100644 drivers/net/hinic/base/hinic_pmd_hwif.c\n create mode 100644 drivers/net/hinic/base/hinic_pmd_hwif.h", "diff": "diff --git a/drivers/net/hinic/base/hinic_pmd_hwif.c b/drivers/net/hinic/base/hinic_pmd_hwif.c\nnew file mode 100644\nindex 000000000..a5e223b21\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_pmd_hwif.c\n@@ -0,0 +1,474 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#include <rte_bus_pci.h>\n+\n+#include \"hinic_compat.h\"\n+#include \"hinic_csr.h\"\n+#include \"hinic_pmd_hwdev.h\"\n+#include \"hinic_pmd_hwif.h\"\n+\n+#define HINIC_CFG_REGS_BAR\t0\n+#define HINIC_INTR_MSI_BAR\t2\n+#define HINIC_DB_MEM_BAR\t4\n+\n+#define\tHINIC_MSIX_CNT_RESEND_TIMER_SHIFT\t29\n+#define\tHINIC_MSIX_CNT_RESEND_TIMER_MASK\t0x7U\n+\n+#define HINIC_MSIX_CNT_SET(val, member)\t\t\\\n+\t\t(((val) & HINIC_MSIX_CNT_##member##_MASK) << \\\n+\t\tHINIC_MSIX_CNT_##member##_SHIFT)\n+\n+/**\n+ * hwif_ready - test if the HW initialization passed\n+ * @hwdev: the pointer to the private hardware device object\n+ * Return: 0 - success, negative - failure\n+ **/\n+static int hwif_ready(struct hinic_hwdev *hwdev)\n+{\n+\tu32 addr, attr1;\n+\n+\taddr = HINIC_CSR_FUNC_ATTR1_ADDR;\n+\tattr1 = hinic_hwif_read_reg(hwdev->hwif, addr);\n+\n+\tif (!HINIC_AF1_GET(attr1, MGMT_INIT_STATUS))\n+\t\treturn -EBUSY;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * set_hwif_attr - set the attributes as members in hwif\n+ * @hwif: the hardware interface of a pci function device\n+ * @attr0: the first attribute that was read from the hw\n+ * @attr1: the second attribute that was read from the hw\n+ * @attr2: the third attribute that was read from the hw\n+ **/\n+static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1,\n+\t\t\t u32 attr2)\n+{\n+\thwif->attr.func_global_idx = HINIC_AF0_GET(attr0, FUNC_GLOBAL_IDX);\n+\thwif->attr.port_to_port_idx = HINIC_AF0_GET(attr0, P2P_IDX);\n+\thwif->attr.pci_intf_idx = HINIC_AF0_GET(attr0, PCI_INTF_IDX);\n+\thwif->attr.vf_in_pf = HINIC_AF0_GET(attr0, VF_IN_PF);\n+\thwif->attr.func_type = HINIC_AF0_GET(attr0, FUNC_TYPE);\n+\n+\thwif->attr.ppf_idx = HINIC_AF1_GET(attr1, PPF_IDX);\n+\n+\thwif->attr.num_aeqs = BIT(HINIC_AF1_GET(attr1, AEQS_PER_FUNC));\n+\thwif->attr.num_ceqs = BIT(HINIC_AF1_GET(attr1, CEQS_PER_FUNC));\n+\thwif->attr.num_irqs = BIT(HINIC_AF1_GET(attr1, IRQS_PER_FUNC));\n+\thwif->attr.num_dma_attr = BIT(HINIC_AF1_GET(attr1, DMA_ATTR_PER_FUNC));\n+\n+\thwif->attr.global_vf_id_of_pf = HINIC_AF2_GET(attr2,\n+\t\t\t\t\t\t GLOBAL_VF_ID_OF_PF);\n+}\n+\n+/**\n+ * get_hwif_attr - read and set the attributes as members in hwif\n+ * @hwif: the hardware interface of a pci function device\n+ **/\n+static void get_hwif_attr(struct hinic_hwif *hwif)\n+{\n+\tu32 addr, attr0, attr1, attr2;\n+\n+\taddr = HINIC_CSR_FUNC_ATTR0_ADDR;\n+\tattr0 = hinic_hwif_read_reg(hwif, addr);\n+\n+\taddr = HINIC_CSR_FUNC_ATTR1_ADDR;\n+\tattr1 = hinic_hwif_read_reg(hwif, addr);\n+\n+\taddr = HINIC_CSR_FUNC_ATTR2_ADDR;\n+\tattr2 = hinic_hwif_read_reg(hwif, addr);\n+\n+\tset_hwif_attr(hwif, attr0, attr1, attr2);\n+}\n+\n+void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status)\n+{\n+\tu32 attr5 = HINIC_AF5_SET(status, PF_STATUS);\n+\tu32 addr = HINIC_CSR_FUNC_ATTR5_ADDR;\n+\n+\thinic_hwif_write_reg(hwif, addr, attr5);\n+}\n+\n+enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif)\n+{\n+\tu32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR);\n+\n+\treturn HINIC_AF5_GET(attr5, PF_STATUS);\n+}\n+\n+static enum hinic_doorbell_ctrl\n+hinic_get_doorbell_ctrl_status(struct hinic_hwif *hwif)\n+{\n+\tu32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);\n+\n+\treturn HINIC_AF4_GET(attr4, DOORBELL_CTRL);\n+}\n+\n+static enum hinic_outbound_ctrl\n+hinic_get_outbound_ctrl_status(struct hinic_hwif *hwif)\n+{\n+\tu32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);\n+\n+\treturn HINIC_AF4_GET(attr4, OUTBOUND_CTRL);\n+}\n+\n+void hinic_enable_doorbell(struct hinic_hwif *hwif)\n+{\n+\tu32 addr, attr4;\n+\n+\taddr = HINIC_CSR_FUNC_ATTR4_ADDR;\n+\tattr4 = hinic_hwif_read_reg(hwif, addr);\n+\n+\tattr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);\n+\tattr4 |= HINIC_AF4_SET(ENABLE_DOORBELL, DOORBELL_CTRL);\n+\n+\thinic_hwif_write_reg(hwif, addr, attr4);\n+}\n+\n+void hinic_disable_doorbell(struct hinic_hwif *hwif)\n+{\n+\tu32 addr, attr4;\n+\n+\taddr = HINIC_CSR_FUNC_ATTR4_ADDR;\n+\tattr4 = hinic_hwif_read_reg(hwif, addr);\n+\n+\tattr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);\n+\tattr4 |= HINIC_AF4_SET(DISABLE_DOORBELL, DOORBELL_CTRL);\n+\n+\thinic_hwif_write_reg(hwif, addr, attr4);\n+}\n+\n+/**\n+ * set_ppf - try to set hwif as ppf and set the type of hwif in this case\n+ * @hwif: the hardware interface of a pci function device\n+ **/\n+static void set_ppf(struct hinic_hwif *hwif)\n+{\n+\tstruct hinic_func_attr *attr = &hwif->attr;\n+\tu32 addr, val, ppf_election;\n+\n+\t/* Read Modify Write */\n+\taddr = HINIC_CSR_PPF_ELECTION_ADDR;\n+\n+\tval = hinic_hwif_read_reg(hwif, addr);\n+\tval = HINIC_PPF_ELECTION_CLEAR(val, IDX);\n+\n+\tppf_election = HINIC_PPF_ELECTION_SET(attr->func_global_idx, IDX);\n+\tval |= ppf_election;\n+\n+\thinic_hwif_write_reg(hwif, addr, val);\n+\n+\t/* Check PPF */\n+\tval = hinic_hwif_read_reg(hwif, addr);\n+\n+\tattr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX);\n+\tif (attr->ppf_idx == attr->func_global_idx)\n+\t\tattr->func_type = TYPE_PPF;\n+}\n+\n+static void init_db_area_idx(struct hinic_free_db_area *free_db_area)\n+{\n+\tu32 i;\n+\n+\tfor (i = 0; i < HINIC_DB_MAX_AREAS; i++)\n+\t\tfree_db_area->db_idx[i] = i;\n+\n+\tfree_db_area->alloc_pos = 0;\n+\tfree_db_area->return_pos = 0;\n+\n+\tfree_db_area->num_free = HINIC_DB_MAX_AREAS;\n+\n+\tspin_lock_init(&free_db_area->idx_lock);\n+}\n+\n+static int get_db_idx(struct hinic_hwif *hwif, u32 *idx)\n+{\n+\tstruct hinic_free_db_area *free_db_area = &hwif->free_db_area;\n+\tu32 pos;\n+\tu32 pg_idx;\n+\n+\tspin_lock(&free_db_area->idx_lock);\n+\n+\tif (free_db_area->num_free == 0) {\n+\t\tspin_unlock(&free_db_area->idx_lock);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tfree_db_area->num_free--;\n+\n+\tpos = free_db_area->alloc_pos++;\n+\tpos &= HINIC_DB_MAX_AREAS - 1;\n+\n+\tpg_idx = free_db_area->db_idx[pos];\n+\n+\tfree_db_area->db_idx[pos] = 0xFFFFFFFF;\n+\n+\tspin_unlock(&free_db_area->idx_lock);\n+\n+\t*idx = pg_idx;\n+\n+\treturn 0;\n+}\n+\n+static void free_db_idx(struct hinic_hwif *hwif, u32 idx)\n+{\n+\tstruct hinic_free_db_area *free_db_area = &hwif->free_db_area;\n+\tu32 pos;\n+\n+\tspin_lock(&free_db_area->idx_lock);\n+\n+\tpos = free_db_area->return_pos++;\n+\tpos &= HINIC_DB_MAX_AREAS - 1;\n+\n+\tfree_db_area->db_idx[pos] = idx;\n+\n+\tfree_db_area->num_free++;\n+\n+\tspin_unlock(&free_db_area->idx_lock);\n+}\n+\n+void hinic_free_db_addr(void *hwdev, void __iomem *db_base)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\tu32 idx = DB_IDX(db_base, hwif->db_base);\n+\n+\tfree_db_idx(hwif, idx);\n+}\n+\n+int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\tu32 idx;\n+\tint err;\n+\n+\terr = get_db_idx(hwif, &idx);\n+\tif (err)\n+\t\treturn -EFAULT;\n+\n+\t*db_base = hwif->db_base + idx * HINIC_DB_PAGE_SIZE;\n+\n+\treturn 0;\n+}\n+\n+void hinic_set_msix_state(void *hwdev, u16 msix_idx, enum hinic_msix_state flag)\n+{\n+\tstruct hinic_hwdev *hw = hwdev;\n+\tstruct hinic_hwif *hwif = hw->hwif;\n+\tu32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE\n+\t\t+ HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL;\n+\tu32 mask_bits;\n+\n+\t/* vfio-pci does not mmap msi-x vector table to user space,\n+\t * we can not access the space when kernel driver is vfio-pci\n+\t */\n+\tif (hw->pcidev_hdl->kdrv == RTE_KDRV_VFIO)\n+\t\treturn;\n+\n+\tmask_bits = readl(hwif->intr_regs_base + offset);\n+\tmask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;\n+\tif (flag)\n+\t\tmask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;\n+\n+\twritel(mask_bits, hwif->intr_regs_base + offset);\n+}\n+\n+static void disable_all_msix(struct hinic_hwdev *hwdev)\n+{\n+\tu16 num_irqs = hwdev->hwif->attr.num_irqs;\n+\tu16 i;\n+\n+\tfor (i = 0; i < num_irqs; i++)\n+\t\thinic_set_msix_state(hwdev, i, HINIC_MSIX_DISABLE);\n+}\n+\n+static int wait_until_doorbell_and_outbound_enabled(struct hinic_hwif *hwif)\n+{\n+\tunsigned long end;\n+\tenum hinic_doorbell_ctrl db_ctrl;\n+\tenum hinic_outbound_ctrl outbound_ctrl;\n+\n+\tend = jiffies +\n+\t\tmsecs_to_jiffies(HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT);\n+\tdo {\n+\t\tdb_ctrl = hinic_get_doorbell_ctrl_status(hwif);\n+\t\toutbound_ctrl = hinic_get_outbound_ctrl_status(hwif);\n+\n+\t\tif (outbound_ctrl == ENABLE_OUTBOUND &&\n+\t\t db_ctrl == ENABLE_DOORBELL)\n+\t\t\treturn 0;\n+\n+\t\trte_delay_ms(1);\n+\t} while (time_before(jiffies, end));\n+\n+\treturn -EFAULT;\n+}\n+\n+u16 hinic_global_func_id(void *hwdev)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.func_global_idx;\n+}\n+\n+enum func_type hinic_func_type(void *hwdev)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.func_type;\n+}\n+\n+u8 hinic_ppf_idx(void *hwdev)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\n+\treturn hwif->attr.ppf_idx;\n+}\n+\n+/**\n+ * hinic_init_hwif - initialize the hw interface\n+ * @hwdev: the pointer to the private hardware device object\n+ * @cfg_reg_base: base physical address of configuration registers\n+ * @intr_reg_base: base physical address of msi-x vector table\n+ * @db_base_phy: base physical address of doorbell registers\n+ * @db_base: base virtual address of doorbell registers\n+ * @dwqe_mapping: direct wqe io mapping address\n+ * Return: 0 - success, negative - failure\n+ **/\n+static int hinic_init_hwif(struct hinic_hwdev *hwdev, void *cfg_reg_base,\n+\t\t void *intr_reg_base, u64 db_base_phy,\n+\t\t void *db_base, __rte_unused void *dwqe_mapping)\n+{\n+\tstruct hinic_hwif *hwif;\n+\tint err;\n+\n+\thwif = hwdev->hwif;\n+\n+\thwif->cfg_regs_base = (u8 __iomem *)cfg_reg_base;\n+\thwif->intr_regs_base = (u8 __iomem *)intr_reg_base;\n+\n+\thwif->db_base_phy = db_base_phy;\n+\thwif->db_base = (u8 __iomem *)db_base;\n+\tinit_db_area_idx(&hwif->free_db_area);\n+\n+\tget_hwif_attr(hwif);\n+\n+\terr = hwif_ready(hwdev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Hwif is not ready\");\n+\t\tgoto hwif_ready_err;\n+\t}\n+\n+\terr = wait_until_doorbell_and_outbound_enabled(hwif);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Hw doorbell/outbound is disabled\");\n+\t\tgoto hwif_ready_err;\n+\t}\n+\n+\tif (!HINIC_IS_VF(hwdev))\n+\t\tset_ppf(hwif);\n+\n+\treturn 0;\n+\n+hwif_ready_err:\n+\tspin_lock_deinit(&hwif->free_db_area.idx_lock);\n+\n+\treturn err;\n+}\n+\n+#define HINIC_HWIF_ATTR_REG_PRINT_NUM (6)\n+#define HINIC_HWIF_APICMD_REG_PRINT_NUM (2)\n+#define HINIC_HWIF_EQ_REG_PRINT_NUM (2)\n+\n+static void hinic_parse_hwif_attr(struct hinic_hwdev *hwdev)\n+{\n+\tstruct hinic_hwif *hwif = hwdev->hwif;\n+\n+\tPMD_DRV_LOG(INFO, \"Device %s hwif attribute:\", hwdev->pcidev_hdl->name);\n+\tPMD_DRV_LOG(INFO, \"func_idx:%u, p2p_idx:%u, pciintf_idx:%u, \"\n+\t\t \"vf_in_pf:%u, ppf_idx:%u, global_vf_id:%u, func_type:%u\",\n+\t\t hwif->attr.func_global_idx,\n+\t\t hwif->attr.port_to_port_idx, hwif->attr.pci_intf_idx,\n+\t\t hwif->attr.vf_in_pf, hwif->attr.ppf_idx,\n+\t\t hwif->attr.global_vf_id_of_pf, hwif->attr.func_type);\n+\tPMD_DRV_LOG(INFO, \"num_aeqs:%u, num_ceqs:%u, num_irqs:%u, dma_attr:%u\",\n+\t\t hwif->attr.num_aeqs, hwif->attr.num_ceqs,\n+\t\t hwif->attr.num_irqs, hwif->attr.num_dma_attr);\n+}\n+\n+static void hinic_get_mmio(struct hinic_hwdev *hwdev, void **cfg_regs_base,\n+\t\t\t void **intr_base, void **db_base)\n+{\n+\tstruct rte_pci_device *pci_dev = hwdev->pcidev_hdl;\n+\n+\t*cfg_regs_base = pci_dev->mem_resource[HINIC_CFG_REGS_BAR].addr;\n+\t*intr_base = pci_dev->mem_resource[HINIC_INTR_MSI_BAR].addr;\n+\t*db_base = pci_dev->mem_resource[HINIC_DB_MEM_BAR].addr;\n+}\n+\n+void hinic_hwif_res_free(struct hinic_hwdev *hwdev)\n+{\n+\trte_free(hwdev->hwif);\n+\thwdev->hwif = NULL;\n+}\n+\n+int hinic_hwif_res_init(struct hinic_hwdev *hwdev)\n+{\n+\tint err = HINIC_ERROR;\n+\tvoid *cfg_regs_base, *db_base, *intr_base = NULL;\n+\n+\t/* hinic related init */\n+\thwdev->hwif = rte_zmalloc(\"hinic_hwif\", sizeof(*hwdev->hwif),\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!hwdev->hwif) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate hwif failed, dev_name: %s\",\n+\t\t\t hwdev->pcidev_hdl->name);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\thinic_get_mmio(hwdev, &cfg_regs_base, &intr_base, &db_base);\n+\n+\terr = hinic_init_hwif(hwdev, cfg_regs_base,\n+\t\t\t intr_base, 0, db_base, NULL);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize hwif failed, dev_name: %s\",\n+\t\t\t hwdev->pcidev_hdl->name);\n+\t\tgoto init_hwif_err;\n+\t}\n+\n+\t/* disable msix interrupt in hw device */\n+\tdisable_all_msix(hwdev);\n+\n+\t/* print hwif attributes */\n+\thinic_parse_hwif_attr(hwdev);\n+\n+\treturn HINIC_OK;\n+\n+init_hwif_err:\n+\trte_free(hwdev->hwif);\n+\thwdev->hwif = NULL;\n+\n+\treturn err;\n+}\n+\n+/**\n+ * hinic_misx_intr_clear_resend_bit - clear interrupt resend configuration\n+ * @hwdev: the hardware interface of a nic device\n+ * @msix_idx: Index of msix interrupt\n+ * @clear_resend_en: enable flag of clear resend configuration\n+ **/\n+void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,\n+\t\t\t\t u8 clear_resend_en)\n+{\n+\tstruct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;\n+\tu32 msix_ctrl = 0, addr;\n+\n+\tmsix_ctrl = HINIC_MSIX_CNT_SET(clear_resend_en, RESEND_TIMER);\n+\n+\taddr = HINIC_CSR_MSIX_CNT_ADDR(msix_idx);\n+\n+\thinic_hwif_write_reg(hwif, addr, msix_ctrl);\n+}\ndiff --git a/drivers/net/hinic/base/hinic_pmd_hwif.h b/drivers/net/hinic/base/hinic_pmd_hwif.h\nnew file mode 100644\nindex 000000000..c1289b57f\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_pmd_hwif.h\n@@ -0,0 +1,119 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PMD_HWIF_H_\n+#define _HINIC_PMD_HWIF_H_\n+\n+#define HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT\t30000\n+\n+#define HINIC_HWIF_NUM_AEQS(hwif)\t\t((hwif)->attr.num_aeqs)\n+#define HINIC_HWIF_NUM_CEQS(hwif)\t\t((hwif)->attr.num_ceqs)\n+#define HINIC_HWIF_NUM_IRQS(hwif)\t\t((hwif)->attr.num_irqs)\n+#define HINIC_HWIF_GLOBAL_IDX(hwif)\t\t((hwif)->attr.func_global_idx)\n+#define HINIC_HWIF_GLOBAL_VF_OFFSET(hwif) ((hwif)->attr.global_vf_id_of_pf)\n+#define HINIC_HWIF_PPF_IDX(hwif)\t\t((hwif)->attr.ppf_idx)\n+#define HINIC_PCI_INTF_IDX(hwif)\t\t((hwif)->attr.pci_intf_idx)\n+\n+#define HINIC_FUNC_TYPE(dev)\t\t((dev)->hwif->attr.func_type)\n+#define HINIC_IS_PF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_PF)\n+#define HINIC_IS_VF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_VF)\n+#define HINIC_IS_PPF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_PPF)\n+\n+enum func_type {\n+\tTYPE_PF,\n+\tTYPE_VF,\n+\tTYPE_PPF,\n+};\n+\n+enum hinic_msix_state {\n+\tHINIC_MSIX_ENABLE,\n+\tHINIC_MSIX_DISABLE,\n+};\n+\n+/* Defines the IRQ information structure*/\n+struct irq_info {\n+\tu16 msix_entry_idx; /* IRQ corresponding index number */\n+\tu32 irq_id; /* the IRQ number from OS */\n+};\n+\n+struct hinic_free_db_area {\n+\tu32\t\tdb_idx[HINIC_DB_MAX_AREAS];\n+\n+\tu32\t\tnum_free;\n+\n+\tu32\t\talloc_pos;\n+\tu32\t\treturn_pos;\n+\t/* spinlock for idx */\n+\tspinlock_t\tidx_lock;\n+};\n+\n+struct hinic_func_attr {\n+\tu16\t\t\tfunc_global_idx;\n+\tu8\t\t\tport_to_port_idx;\n+\tu8\t\t\tpci_intf_idx;\n+\tu8\t\t\tvf_in_pf;\n+\tenum func_type\t\tfunc_type;\n+\n+\tu8\t\t\tmpf_idx;\n+\n+\tu8\t\t\tppf_idx;\n+\n+\tu16\t\t\tnum_irqs;\t\t/* max: 2 ^ 15 */\n+\tu8\t\t\tnum_aeqs;\t\t/* max: 2 ^ 3 */\n+\tu8\t\t\tnum_ceqs;\t\t/* max: 2 ^ 7 */\n+\n+\tu8\t\t\tnum_dma_attr;\t\t/* max: 2 ^ 6 */\n+\n+\tu16\t\t\tglobal_vf_id_of_pf;\n+};\n+\n+struct hinic_hwif {\n+\tu8 __iomem\t\t\t*cfg_regs_base;\n+\tu8 __iomem\t\t\t*intr_regs_base;\n+\tu64\t\t\t\tdb_base_phy;\n+\tu8 __iomem\t\t\t*db_base;\n+\tstruct hinic_free_db_area\tfree_db_area;\n+\tstruct hinic_func_attr\t\tattr;\n+};\n+\n+static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg)\n+{\n+\treturn be32_to_cpu(readl(hwif->cfg_regs_base + reg));\n+}\n+\n+static inline void\n+hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, u32 val)\n+{\n+\twritel(cpu_to_be32(val), hwif->cfg_regs_base + reg);\n+}\n+\n+u16 hinic_global_func_id(void *hwdev);\t/* func_attr.glb_func_idx */\n+\n+enum func_type hinic_func_type(void *hwdev);\n+\n+void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status);\n+\n+enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif);\n+\n+void hinic_enable_doorbell(struct hinic_hwif *hwif);\n+\n+void hinic_disable_doorbell(struct hinic_hwif *hwif);\n+\n+int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base);\n+\n+void hinic_free_db_addr(void *hwdev, void __iomem *db_base);\n+\n+void hinic_set_msix_state(void *hwdev, u16 msix_idx,\n+\t\t\t enum hinic_msix_state flag);\n+\n+void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,\n+\t\t\t\t u8 clear_resend_en);\n+\n+u8 hinic_ppf_idx(void *hwdev);\n+\n+int hinic_hwif_res_init(struct hinic_hwdev *hwdev);\n+\n+void hinic_hwif_res_free(struct hinic_hwdev *hwdev);\n+\n+#endif /* _HINIC_PMD_HWIF_H_ */\n", "prefixes": [ "v5", "02/15" ] }