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{
    "id": 54997,
    "url": "http://patches.dpdk.org/api/patches/54997/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/77307b1fb7ec974c6dc00a8e94e576b9e259ea63.1560958308.git.xuanziyang2@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<77307b1fb7ec974c6dc00a8e94e576b9e259ea63.1560958308.git.xuanziyang2@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/77307b1fb7ec974c6dc00a8e94e576b9e259ea63.1560958308.git.xuanziyang2@huawei.com",
    "date": "2019-06-19T15:46:20",
    "name": "[v5,01/15] net/hinic/base: add HW registers definition",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "99b62e22f3471a3178f47b7c0a6fb0ffee2ac42f",
    "submitter": {
        "id": 1321,
        "url": "http://patches.dpdk.org/api/people/1321/?format=api",
        "name": "Ziyang Xuan",
        "email": "xuanziyang2@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/77307b1fb7ec974c6dc00a8e94e576b9e259ea63.1560958308.git.xuanziyang2@huawei.com/mbox/",
    "series": [
        {
            "id": 5084,
            "url": "http://patches.dpdk.org/api/series/5084/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5084",
            "date": "2019-06-19T15:45:20",
            "name": "A new net PMD - hinic",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/5084/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54997/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/54997/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AB52C1C433;\n\tWed, 19 Jun 2019 17:34:31 +0200 (CEST)",
            "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 606B21C3C8\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 17:34:27 +0200 (CEST)",
            "from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id 4B395D9112E829068D9A\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 23:34:25 +0800 (CST)",
            "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP\n\tServer id 14.3.439.0; Wed, 19 Jun 2019 23:34:17 +0800"
        ],
        "From": "Ziyang Xuan <xuanziyang2@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <shahar.belkar@huawei.com>,\n\t<luoxianjun@huawei.com>, Ziyang Xuan <xuanziyang2@huawei.com>",
        "Date": "Wed, 19 Jun 2019 23:46:20 +0800",
        "Message-ID": "<77307b1fb7ec974c6dc00a8e94e576b9e259ea63.1560958308.git.xuanziyang2@huawei.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<cover.1560958308.git.xuanziyang2@huawei.com>",
        "References": "<cover.1560958308.git.xuanziyang2@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.175.119.39]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH v5 01/15] net/hinic/base: add HW registers\n\tdefinition",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add HW registers definition header file for Hi1822 NIC.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/base/hinic_csr.h | 160 +++++++++++++++++++++++++++++\n 1 file changed, 160 insertions(+)\n create mode 100644 drivers/net/hinic/base/hinic_csr.h",
    "diff": "diff --git a/drivers/net/hinic/base/hinic_csr.h b/drivers/net/hinic/base/hinic_csr.h\nnew file mode 100644\nindex 000000000..b63e52b1c\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_csr.h\n@@ -0,0 +1,160 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_CSR_H_\n+#define _HINIC_CSR_H_\n+\n+#define HINIC_CSR_GLOBAL_BASE_ADDR\t\t\t0x4000\n+\n+/* HW interface registers */\n+#define HINIC_CSR_FUNC_ATTR0_ADDR\t\t\t0x0\n+#define HINIC_CSR_FUNC_ATTR1_ADDR\t\t\t0x4\n+#define HINIC_CSR_FUNC_ATTR2_ADDR\t\t\t0x8\n+#define HINIC_CSR_FUNC_ATTR4_ADDR\t\t\t0x10\n+#define HINIC_CSR_FUNC_ATTR5_ADDR\t\t\t0x14\n+\n+#define HINIC_FUNC_CSR_MAILBOX_DATA_OFF\t\t\t0x80\n+#define HINIC_FUNC_CSR_MAILBOX_CONTROL_OFF\t\t0x0100\n+#define HINIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF\t\t0x0104\n+#define HINIC_FUNC_CSR_MAILBOX_RESULT_H_OFF\t\t0x0108\n+#define HINIC_FUNC_CSR_MAILBOX_RESULT_L_OFF\t\t0x010C\n+\n+#define HINIC_CSR_DMA_ATTR_TBL_BASE\t\t\t0xC80\n+\n+#define HINIC_ELECTION_BASE\t\t\t\t0x200\n+\n+#define HINIC_CSR_DMA_ATTR_TBL_STRIDE\t\t\t0x4\n+#define HINIC_CSR_DMA_ATTR_TBL_ADDR(idx)\t\t\\\n+\t\t\t(HINIC_CSR_DMA_ATTR_TBL_BASE\t\\\n+\t\t\t+ (idx) * HINIC_CSR_DMA_ATTR_TBL_STRIDE)\n+\n+#define HINIC_PPF_ELECTION_STRIDE\t\t\t0x4\n+#define HINIC_CSR_MAX_PORTS\t\t\t\t4\n+#define HINIC_CSR_PPF_ELECTION_ADDR\t\t\\\n+\t\t\t(HINIC_CSR_GLOBAL_BASE_ADDR + HINIC_ELECTION_BASE)\n+\n+/* MSI-X registers */\n+#define HINIC_CSR_MSIX_CTRL_BASE\t\t\t0x2000\n+#define HINIC_CSR_MSIX_CNT_BASE\t\t\t\t0x2004\n+\n+#define HINIC_CSR_MSIX_STRIDE\t\t\t\t0x8\n+\n+#define HINIC_CSR_MSIX_CTRL_ADDR(idx)\t\t\t\\\n+\t(HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)\n+\n+#define HINIC_CSR_MSIX_CNT_ADDR(idx)\t\t\t\\\n+\t(HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)\n+\n+/* EQ registers */\n+#define HINIC_AEQ_MTT_OFF_BASE_ADDR\t\t\t0x200\n+#define HINIC_CEQ_MTT_OFF_BASE_ADDR\t\t\t0x400\n+\n+#define HINIC_EQ_MTT_OFF_STRIDE\t\t\t\t0x40\n+\n+#define HINIC_CSR_AEQ_MTT_OFF(id)\t\t\t\\\n+\t(HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)\n+\n+#define HINIC_CSR_CEQ_MTT_OFF(id)\t\t\t\\\n+\t(HINIC_CEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)\n+\n+#define HINIC_CSR_EQ_PAGE_OFF_STRIDE\t\t\t8\n+\n+#define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)\t\\\n+\t\t(HINIC_CSR_AEQ_MTT_OFF(q_id) + \\\n+\t\t(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)\n+\n+#define HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)\t\\\n+\t\t(HINIC_CSR_AEQ_MTT_OFF(q_id) + \\\n+\t\t(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)\n+\n+#define HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)\t\\\n+\t\t(HINIC_CSR_CEQ_MTT_OFF(q_id) + \\\n+\t\t(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)\n+\n+#define HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)\t\\\n+\t\t(HINIC_CSR_CEQ_MTT_OFF(q_id) + \\\n+\t\t(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)\n+\n+#define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num)\t\\\n+\t\t((u32)((type == HINIC_AEQ) ? \\\n+\t\tHINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) : \\\n+\t\tHINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))\n+\n+#define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num)\t\\\n+\t\t((u32)((type == HINIC_AEQ) ? \\\n+\t\tHINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) : \\\n+\t\tHINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))\n+\n+#define HINIC_AEQ_CTRL_0_ADDR_BASE\t\t\t0xE00\n+#define HINIC_AEQ_CTRL_1_ADDR_BASE\t\t\t0xE04\n+#define HINIC_AEQ_CONS_IDX_0_ADDR_BASE\t\t\t0xE08\n+#define HINIC_AEQ_CONS_IDX_1_ADDR_BASE\t\t\t0xE0C\n+\n+#define HINIC_EQ_OFF_STRIDE\t\t\t\t0x80\n+\n+#define HINIC_CSR_AEQ_CTRL_0_ADDR(idx) \\\n+\t(HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+#define HINIC_CSR_AEQ_CTRL_1_ADDR(idx) \\\n+\t(HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+#define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx) \\\n+\t(HINIC_AEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+#define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \\\n+\t(HINIC_AEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+#define HINIC_CEQ_CONS_IDX_0_ADDR_BASE\t\t\t0x1008\n+#define HINIC_CEQ_CONS_IDX_1_ADDR_BASE\t\t\t0x100C\n+\n+#define HINIC_CSR_CEQ_CONS_IDX_ADDR(idx) \\\n+\t(HINIC_CEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+#define HINIC_CSR_CEQ_PROD_IDX_ADDR(idx) \\\n+\t(HINIC_CEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)\n+\n+/* API CMD registers */\n+#define HINIC_CSR_API_CMD_BASE\t\t\t\t0xF000\n+\n+#define HINIC_CSR_API_CMD_STRIDE\t\t\t0x100\n+\n+#define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx)\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx)\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx)\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+#define HINIC_CSR_API_CMD_STATUS_0_ADDR(idx)\t\t\\\n+\t(HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)\n+\n+/* VF control registers in pf */\n+#define HINIC_PF_CSR_VF_FLUSH_BASE\t\t0x1F400\n+#define HINIC_PF_CSR_VF_FLUSH_STRIDE\t\t0x4\n+\n+#define HINIC_GLB_DMA_SO_RO_REPLACE_ADDR\t0x488C\n+\n+#define HINIC_ICPL_RESERVD_ADDR\t\t\t0x9204\n+\n+#define HINIC_PF_CSR_VF_FLUSH_OFF(idx)\t\t\t\\\n+\t(HINIC_PF_CSR_VF_FLUSH_BASE + (idx) * HINIC_PF_CSR_VF_FLUSH_STRIDE)\n+\n+#endif /* _HINIC_CSR_H_ */\n",
    "prefixes": [
        "v5",
        "01/15"
    ]
}