Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/54972/?format=api
{ "id": 54972, "url": "http://patches.dpdk.org/api/patches/54972/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1560957293-17294-19-git-send-email-ndragazis@arrikto.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1560957293-17294-19-git-send-email-ndragazis@arrikto.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1560957293-17294-19-git-send-email-ndragazis@arrikto.com", "date": "2019-06-19T15:14:43", "name": "[18/28] drivers/virtio_vhost_user: add virtio PCI framework", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "e4aeeea9725a6597a6091a9391e8c3414254c81f", "submitter": { "id": 1339, "url": "http://patches.dpdk.org/api/people/1339/?format=api", "name": "Nikos Dragazis", "email": "ndragazis@arrikto.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1560957293-17294-19-git-send-email-ndragazis@arrikto.com/mbox/", "series": [ { "id": 5082, "url": "http://patches.dpdk.org/api/series/5082/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5082", "date": "2019-06-19T15:14:25", "name": "vhost: add virtio-vhost-user transport", "version": 1, "mbox": "http://patches.dpdk.org/series/5082/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54972/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5A5AB1C418;\n\tWed, 19 Jun 2019 17:16:34 +0200 (CEST)", "from mx0.arrikto.com (mx0.arrikto.com [212.71.252.59])\n\tby dpdk.org (Postfix) with ESMTP id C8FA21C398\n\tfor <dev@dpdk.org>; Wed, 19 Jun 2019 17:15:44 +0200 (CEST)", "from troi.prod.arr (mail.arr [10.99.0.5])\n\tby mx0.arrikto.com (Postfix) with ESMTP id 89CE0182016;\n\tWed, 19 Jun 2019 18:15:44 +0300 (EEST)", "from localhost.localdomain (unknown [10.89.50.133])\n\tby troi.prod.arr (Postfix) with ESMTPSA id 2888D394;\n\tWed, 19 Jun 2019 18:15:43 +0300 (EEST)" ], "From": "Nikos Dragazis <ndragazis@arrikto.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n\tTiwei Bie <tiwei.bie@intel.com>, Zhihong Wang <zhihong.wang@intel.com>,\n\tStefan Hajnoczi <stefanha@redhat.com>, Wei Wang <wei.w.wang@intel.com>,\n\tStojaczyk Dariusz <dariusz.stojaczyk@intel.com>,\n\tVangelis Koukis <vkoukis@arrikto.com>", "Date": "Wed, 19 Jun 2019 18:14:43 +0300", "Message-Id": "<1560957293-17294-19-git-send-email-ndragazis@arrikto.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560957293-17294-1-git-send-email-ndragazis@arrikto.com>", "References": "<1560957293-17294-1-git-send-email-ndragazis@arrikto.com>", "Subject": "[dpdk-dev] [PATCH 18/28] drivers/virtio_vhost_user: add virtio PCI\n\tframework", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The virtio-vhost-user transport requires a driver for the\nvirtio-vhost-user PCI device, hence it needs a virtio-pci driver. There\nis currently no librte_virtio API that we can use.\n\nThis commit is a hack that duplicates the virtio pci code from\ndrivers/net/ into drivers/virtio_vhost_user/. A better solution would\nbe to extract the code cleanly from drivers/net/ and share it. Or\nperhaps we could backport SPDK's lib/virtio/.\n\ndrivers/virtio_vhost_user/ will host the virtio-vhost-user transport\nimplementation in the upcoming patches.\n\nSigned-off-by: Nikos Dragazis <ndragazis@arrikto.com>\nSigned-off-by: Stefan Hajnoczi <stefanha@redhat.com>\n---\n drivers/virtio_vhost_user/virtio_pci.c | 504 +++++++++++++++++++++++++++++++++\n drivers/virtio_vhost_user/virtio_pci.h | 270 ++++++++++++++++++\n drivers/virtio_vhost_user/virtqueue.h | 181 ++++++++++++\n 3 files changed, 955 insertions(+)\n create mode 100644 drivers/virtio_vhost_user/virtio_pci.c\n create mode 100644 drivers/virtio_vhost_user/virtio_pci.h\n create mode 100644 drivers/virtio_vhost_user/virtqueue.h", "diff": "diff --git a/drivers/virtio_vhost_user/virtio_pci.c b/drivers/virtio_vhost_user/virtio_pci.c\nnew file mode 100644\nindex 0000000..9c2c981\n--- /dev/null\n+++ b/drivers/virtio_vhost_user/virtio_pci.c\n@@ -0,0 +1,504 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2014 Intel Corporation\n+ */\n+#include <stdint.h>\n+\n+/* XXX This file is based on drivers/net/virtio/virtio_pci.c. It would be\n+ * better to create a shared rte_virtio library instead of duplicating this\n+ * code.\n+ */\n+\n+#ifdef RTE_EXEC_ENV_LINUX\n+ #include <dirent.h>\n+ #include <fcntl.h>\n+#endif\n+\n+#include <rte_io.h>\n+#include <rte_bus.h>\n+\n+#include \"virtio_pci.h\"\n+#include \"virtqueue.h\"\n+\n+/*\n+ * Following macros are derived from linux/pci_regs.h, however,\n+ * we can't simply include that header here, as there is no such\n+ * file for non-Linux platform.\n+ */\n+#define PCI_CAPABILITY_LIST\t0x34\n+#define PCI_CAP_ID_VNDR\t\t0x09\n+#define PCI_CAP_ID_MSIX\t\t0x11\n+\n+/*\n+ * The remaining space is defined by each driver as the per-driver\n+ * configuration space.\n+ */\n+#define VIRTIO_PCI_CONFIG(hw) \\\n+\t\t(((hw)->use_msix == VIRTIO_MSIX_ENABLED) ? 24 : 20)\n+\n+static inline int\n+check_vq_phys_addr_ok(struct virtqueue *vq)\n+{\n+\t/* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,\n+\t * and only accepts 32 bit page frame number.\n+\t * Check if the allocated physical memory exceeds 16TB.\n+\t */\n+\tif ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>\n+\t\t\t(VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {\n+\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG, \"vring address shouldn't be above 16TB!\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+static inline void\n+io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)\n+{\n+\trte_write32(val & ((1ULL << 32) - 1), lo);\n+\trte_write32(val >> 32,\t\t hi);\n+}\n+\n+static void\n+modern_read_dev_config(struct virtio_hw *hw, size_t offset,\n+\t\t void *dst, int length)\n+{\n+\tint i;\n+\tuint8_t *p;\n+\tuint8_t old_gen, new_gen;\n+\n+\tdo {\n+\t\told_gen = rte_read8(&hw->common_cfg->config_generation);\n+\n+\t\tp = dst;\n+\t\tfor (i = 0; i < length; i++)\n+\t\t\t*p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);\n+\n+\t\tnew_gen = rte_read8(&hw->common_cfg->config_generation);\n+\t} while (old_gen != new_gen);\n+}\n+\n+static void\n+modern_write_dev_config(struct virtio_hw *hw, size_t offset,\n+\t\t\tconst void *src, int length)\n+{\n+\tint i;\n+\tconst uint8_t *p = src;\n+\n+\tfor (i = 0; i < length; i++)\n+\t\trte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));\n+}\n+\n+static uint64_t\n+modern_get_features(struct virtio_hw *hw)\n+{\n+\tuint32_t features_lo, features_hi;\n+\n+\trte_write32(0, &hw->common_cfg->device_feature_select);\n+\tfeatures_lo = rte_read32(&hw->common_cfg->device_feature);\n+\n+\trte_write32(1, &hw->common_cfg->device_feature_select);\n+\tfeatures_hi = rte_read32(&hw->common_cfg->device_feature);\n+\n+\treturn ((uint64_t)features_hi << 32) | features_lo;\n+}\n+\n+static void\n+modern_set_features(struct virtio_hw *hw, uint64_t features)\n+{\n+\trte_write32(0, &hw->common_cfg->guest_feature_select);\n+\trte_write32(features & ((1ULL << 32) - 1),\n+\t\t &hw->common_cfg->guest_feature);\n+\n+\trte_write32(1, &hw->common_cfg->guest_feature_select);\n+\trte_write32(features >> 32,\n+\t\t &hw->common_cfg->guest_feature);\n+}\n+\n+static uint8_t\n+modern_get_status(struct virtio_hw *hw)\n+{\n+\treturn rte_read8(&hw->common_cfg->device_status);\n+}\n+\n+static void\n+modern_set_status(struct virtio_hw *hw, uint8_t status)\n+{\n+\trte_write8(status, &hw->common_cfg->device_status);\n+}\n+\n+static void\n+modern_reset(struct virtio_hw *hw)\n+{\n+\tmodern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);\n+\tmodern_get_status(hw);\n+}\n+\n+static uint8_t\n+modern_get_isr(struct virtio_hw *hw)\n+{\n+\treturn rte_read8(hw->isr);\n+}\n+\n+static uint16_t\n+modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)\n+{\n+\trte_write16(vec, &hw->common_cfg->msix_config);\n+\treturn rte_read16(&hw->common_cfg->msix_config);\n+}\n+\n+static uint16_t\n+modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)\n+{\n+\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\trte_write16(vec, &hw->common_cfg->queue_msix_vector);\n+\treturn rte_read16(&hw->common_cfg->queue_msix_vector);\n+}\n+\n+static uint16_t\n+modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)\n+{\n+\trte_write16(queue_id, &hw->common_cfg->queue_select);\n+\treturn rte_read16(&hw->common_cfg->queue_size);\n+}\n+\n+static int\n+modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)\n+{\n+\tuint64_t desc_addr, avail_addr, used_addr;\n+\tuint16_t notify_off;\n+\n+\tif (!check_vq_phys_addr_ok(vq))\n+\t\treturn -1;\n+\n+\tdesc_addr = vq->vq_ring_mem;\n+\tavail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);\n+\tused_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,\n+\t\t\t\t\t\t\t ring[vq->vq_nentries]),\n+\t\t\t\t VIRTIO_PCI_VRING_ALIGN);\n+\n+\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\n+\tio_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,\n+\t\t\t\t &hw->common_cfg->queue_desc_hi);\n+\tio_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,\n+\t\t\t\t &hw->common_cfg->queue_avail_hi);\n+\tio_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,\n+\t\t\t\t &hw->common_cfg->queue_used_hi);\n+\n+\tnotify_off = rte_read16(&hw->common_cfg->queue_notify_off);\n+\tvq->notify_addr = (void *)((uint8_t *)hw->notify_base +\n+\t\t\t\tnotify_off * hw->notify_off_multiplier);\n+\n+\trte_write16(1, &hw->common_cfg->queue_enable);\n+\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"queue %u addresses:\\n\", vq->vq_queue_index);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"\\t desc_addr: %\" PRIx64 \"\\n\", desc_addr);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"\\t aval_addr: %\" PRIx64 \"\\n\", avail_addr);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"\\t used_addr: %\" PRIx64 \"\\n\", used_addr);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"\\t notify addr: %p (notify offset: %u)\\n\",\n+\t\tvq->notify_addr, notify_off);\n+\n+\treturn 0;\n+}\n+\n+static void\n+modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)\n+{\n+\trte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);\n+\n+\tio_write64_twopart(0, &hw->common_cfg->queue_desc_lo,\n+\t\t\t\t &hw->common_cfg->queue_desc_hi);\n+\tio_write64_twopart(0, &hw->common_cfg->queue_avail_lo,\n+\t\t\t\t &hw->common_cfg->queue_avail_hi);\n+\tio_write64_twopart(0, &hw->common_cfg->queue_used_lo,\n+\t\t\t\t &hw->common_cfg->queue_used_hi);\n+\n+\trte_write16(0, &hw->common_cfg->queue_enable);\n+}\n+\n+static void\n+modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)\n+{\n+\trte_write16(vq->vq_queue_index, vq->notify_addr);\n+}\n+\n+const struct virtio_pci_ops virtio_pci_modern_ops = {\n+\t.read_dev_cfg\t= modern_read_dev_config,\n+\t.write_dev_cfg\t= modern_write_dev_config,\n+\t.reset\t\t= modern_reset,\n+\t.get_status\t= modern_get_status,\n+\t.set_status\t= modern_set_status,\n+\t.get_features\t= modern_get_features,\n+\t.set_features\t= modern_set_features,\n+\t.get_isr\t= modern_get_isr,\n+\t.set_config_irq\t= modern_set_config_irq,\n+\t.set_queue_irq = modern_set_queue_irq,\n+\t.get_queue_num\t= modern_get_queue_num,\n+\t.setup_queue\t= modern_setup_queue,\n+\t.del_queue\t= modern_del_queue,\n+\t.notify_queue\t= modern_notify_queue,\n+};\n+\n+\n+void\n+virtio_pci_read_dev_config(struct virtio_hw *hw, size_t offset,\n+\t\t void *dst, int length)\n+{\n+\tVTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);\n+}\n+\n+void\n+virtio_pci_write_dev_config(struct virtio_hw *hw, size_t offset,\n+\t\t const void *src, int length)\n+{\n+\tVTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);\n+}\n+\n+uint64_t\n+virtio_pci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)\n+{\n+\tuint64_t features;\n+\n+\t/*\n+\t * Limit negotiated features to what the driver, virtqueue, and\n+\t * host all support.\n+\t */\n+\tfeatures = host_features & hw->guest_features;\n+\tVTPCI_OPS(hw)->set_features(hw, features);\n+\n+\treturn features;\n+}\n+\n+void\n+virtio_pci_reset(struct virtio_hw *hw)\n+{\n+\tVTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);\n+\t/* flush status write */\n+\tVTPCI_OPS(hw)->get_status(hw);\n+}\n+\n+void\n+virtio_pci_reinit_complete(struct virtio_hw *hw)\n+{\n+\tvirtio_pci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);\n+}\n+\n+void\n+virtio_pci_set_status(struct virtio_hw *hw, uint8_t status)\n+{\n+\tif (status != VIRTIO_CONFIG_STATUS_RESET)\n+\t\tstatus |= VTPCI_OPS(hw)->get_status(hw);\n+\n+\tVTPCI_OPS(hw)->set_status(hw, status);\n+}\n+\n+uint8_t\n+virtio_pci_get_status(struct virtio_hw *hw)\n+{\n+\treturn VTPCI_OPS(hw)->get_status(hw);\n+}\n+\n+uint8_t\n+virtio_pci_isr(struct virtio_hw *hw)\n+{\n+\treturn VTPCI_OPS(hw)->get_isr(hw);\n+}\n+\n+static void *\n+get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)\n+{\n+\tuint8_t bar = cap->bar;\n+\tuint32_t length = cap->length;\n+\tuint32_t offset = cap->offset;\n+\tuint8_t *base;\n+\n+\tif (bar >= PCI_MAX_RESOURCE) {\n+\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG, \"invalid bar: %u\\n\", bar);\n+\t\treturn NULL;\n+\t}\n+\n+\tif (offset + length < offset) {\n+\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG, \"offset(%u) + length(%u) overflows\\n\",\n+\t\t\toffset, length);\n+\t\treturn NULL;\n+\t}\n+\n+\tif (offset + length > dev->mem_resource[bar].len) {\n+\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG,\n+\t\t\t\"invalid cap: overflows bar space: %u > %\" PRIu64 \"\\n\",\n+\t\t\toffset + length, dev->mem_resource[bar].len);\n+\t\treturn NULL;\n+\t}\n+\n+\tbase = dev->mem_resource[bar].addr;\n+\tif (base == NULL) {\n+\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG, \"bar %u base addr is NULL\\n\", bar);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn base + offset;\n+}\n+\n+#define PCI_MSIX_ENABLE 0x8000\n+\n+static int\n+virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)\n+{\n+\tuint8_t pos;\n+\tstruct virtio_pci_cap cap;\n+\tint ret;\n+\n+\tif (rte_pci_map_device(dev)) {\n+\t\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"failed to map pci device!\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"failed to read pci capability list\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\twhile (pos) {\n+\t\tret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);\n+\t\tif (ret < 0) {\n+\t\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG,\n+\t\t\t\t\"failed to read pci cap at pos: %x\\n\", pos);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (cap.cap_vndr == PCI_CAP_ID_MSIX) {\n+\t\t\t/* Transitional devices would also have this capability,\n+\t\t\t * that's why we also check if msix is enabled.\n+\t\t\t * 1st byte is cap ID; 2nd byte is the position of next\n+\t\t\t * cap; next two bytes are the flags.\n+\t\t\t */\n+\t\t\tuint16_t flags = ((uint16_t *)&cap)[1];\n+\n+\t\t\tif (flags & PCI_MSIX_ENABLE)\n+\t\t\t\thw->use_msix = VIRTIO_MSIX_ENABLED;\n+\t\t\telse\n+\t\t\t\thw->use_msix = VIRTIO_MSIX_DISABLED;\n+\t\t}\n+\n+\t\tif (cap.cap_vndr != PCI_CAP_ID_VNDR) {\n+\t\t\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG,\n+\t\t\t\t\"[%2x] skipping non VNDR cap id: %02x\\n\",\n+\t\t\t\tpos, cap.cap_vndr);\n+\t\t\tgoto next;\n+\t\t}\n+\n+\t\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG,\n+\t\t\t\"[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u\\n\",\n+\t\t\tpos, cap.cfg_type, cap.bar, cap.offset, cap.length);\n+\n+\t\tswitch (cap.cfg_type) {\n+\t\tcase VIRTIO_PCI_CAP_COMMON_CFG:\n+\t\t\thw->common_cfg = get_cfg_addr(dev, &cap);\n+\t\t\tbreak;\n+\t\tcase VIRTIO_PCI_CAP_NOTIFY_CFG:\n+\t\t\trte_pci_read_config(dev, &hw->notify_off_multiplier,\n+\t\t\t\t\t4, pos + sizeof(cap));\n+\t\t\thw->notify_base = get_cfg_addr(dev, &cap);\n+\t\t\tbreak;\n+\t\tcase VIRTIO_PCI_CAP_DEVICE_CFG:\n+\t\t\thw->dev_cfg = get_cfg_addr(dev, &cap);\n+\t\t\tbreak;\n+\t\tcase VIRTIO_PCI_CAP_ISR_CFG:\n+\t\t\thw->isr = get_cfg_addr(dev, &cap);\n+\t\t\tbreak;\n+\t\t}\n+\n+next:\n+\t\tpos = cap.cap_next;\n+\t}\n+\n+\tif (hw->common_cfg == NULL || hw->notify_base == NULL ||\n+\t hw->dev_cfg == NULL || hw->isr == NULL) {\n+\t\tRTE_LOG(INFO, VIRTIO_PCI_CONFIG, \"no modern virtio pci device found.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tRTE_LOG(INFO, VIRTIO_PCI_CONFIG, \"found modern virtio pci device.\\n\");\n+\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"common cfg mapped at: %p\\n\", hw->common_cfg);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"device cfg mapped at: %p\\n\", hw->dev_cfg);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"isr cfg mapped at: %p\\n\", hw->isr);\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"notify base: %p, notify off multiplier: %u\\n\",\n+\t\thw->notify_base, hw->notify_off_multiplier);\n+\n+\treturn 0;\n+}\n+\n+struct virtio_hw_internal virtio_pci_hw_internal[8];\n+\n+/*\n+ * Return -1:\n+ * if there is error mapping with VFIO/UIO.\n+ * if port map error when driver type is KDRV_NONE.\n+ * if whitelisted but driver type is KDRV_UNKNOWN.\n+ * Return 1 if kernel driver is managing the device.\n+ * Return 0 on success.\n+ */\n+int\n+virtio_pci_init(struct rte_pci_device *dev, struct virtio_hw *hw)\n+{\n+\tstatic size_t internal_id;\n+\n+\tif (internal_id >=\n+\t sizeof(virtio_pci_hw_internal) / sizeof(*virtio_pci_hw_internal)) {\n+\t\tRTE_LOG(INFO, VIRTIO_PCI_CONFIG, \"too many virtio pci devices.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/*\n+\t * Try if we can succeed reading virtio pci caps, which exists\n+\t * only on modern pci device.\n+\t */\n+\tif (virtio_read_caps(dev, hw) != 0) {\n+\t\tRTE_LOG(INFO, VIRTIO_PCI_CONFIG, \"legacy virtio pci is not supported.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tRTE_LOG(INFO, VIRTIO_PCI_CONFIG, \"modern virtio pci detected.\\n\");\n+\thw->internal_id = internal_id++;\n+\tvirtio_pci_hw_internal[hw->internal_id].vtpci_ops =\n+\t\t&virtio_pci_modern_ops;\n+\treturn 0;\n+}\n+\n+enum virtio_msix_status\n+virtio_pci_msix_detect(struct rte_pci_device *dev)\n+{\n+\tuint8_t pos;\n+\tstruct virtio_pci_cap cap;\n+\tint ret;\n+\n+\tret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \"failed to read pci capability list\\n\");\n+\t\treturn VIRTIO_MSIX_NONE;\n+\t}\n+\n+\twhile (pos) {\n+\t\tret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);\n+\t\tif (ret < 0) {\n+\t\t\tRTE_LOG(ERR, VIRTIO_PCI_CONFIG,\n+\t\t\t\t\"failed to read pci cap at pos: %x\\n\", pos);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (cap.cap_vndr == PCI_CAP_ID_MSIX) {\n+\t\t\tuint16_t flags = ((uint16_t *)&cap)[1];\n+\n+\t\t\tif (flags & PCI_MSIX_ENABLE)\n+\t\t\t\treturn VIRTIO_MSIX_ENABLED;\n+\t\t\telse\n+\t\t\t\treturn VIRTIO_MSIX_DISABLED;\n+\t\t}\n+\n+\t\tpos = cap.cap_next;\n+\t}\n+\n+\treturn VIRTIO_MSIX_NONE;\n+}\ndiff --git a/drivers/virtio_vhost_user/virtio_pci.h b/drivers/virtio_vhost_user/virtio_pci.h\nnew file mode 100644\nindex 0000000..018e0b7\n--- /dev/null\n+++ b/drivers/virtio_vhost_user/virtio_pci.h\n@@ -0,0 +1,270 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2014 Intel Corporation\n+ */\n+\n+/* XXX This file is based on drivers/net/virtio/virtio_pci.h. It would be\n+ * better to create a shared rte_virtio library instead of duplicating this\n+ * code.\n+ */\n+\n+#ifndef _VIRTIO_PCI_H_\n+#define _VIRTIO_PCI_H_\n+\n+#include <stdint.h>\n+\n+#include <rte_log.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_spinlock.h>\n+\n+/* Macros for printing using RTE_LOG */\n+#define RTE_LOGTYPE_VIRTIO_PCI_CONFIG RTE_LOGTYPE_USER2\n+\n+struct virtqueue;\n+\n+/* VirtIO PCI vendor/device ID. */\n+#define VIRTIO_PCI_VENDORID 0x1AF4\n+#define VIRTIO_PCI_LEGACY_DEVICEID_VHOST_USER 0x1017\n+#define VIRTIO_PCI_MODERN_DEVICEID_VHOST_USER 0x1058\n+\n+/* VirtIO ABI version, this must match exactly. */\n+#define VIRTIO_PCI_ABI_VERSION 0\n+\n+/*\n+ * VirtIO Header, located in BAR 0.\n+ */\n+#define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/\n+#define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */\n+#define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */\n+#define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */\n+#define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */\n+#define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */\n+#define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */\n+#define VIRTIO_PCI_ISR\t\t 19 /* interrupt status register, reading\n+\t\t\t\t * also clears the register (8, RO) */\n+/* Only if MSIX is enabled: */\n+#define VIRTIO_MSI_CONFIG_VECTOR 20 /* configuration change vector (16, RW) */\n+#define VIRTIO_MSI_QUEUE_VECTOR\t 22 /* vector for selected VQ notifications\n+\t\t\t\t (16, RW) */\n+\n+/* The bit of the ISR which indicates a device has an interrupt. */\n+#define VIRTIO_PCI_ISR_INTR 0x1\n+/* The bit of the ISR which indicates a device configuration change. */\n+#define VIRTIO_PCI_ISR_CONFIG 0x2\n+/* Vector value used to disable MSI for queue. */\n+#define VIRTIO_MSI_NO_VECTOR 0xFFFF\n+\n+/* VirtIO device IDs. */\n+#define VIRTIO_ID_VHOST_USER 0x18\n+\n+/* Status byte for guest to report progress. */\n+#define VIRTIO_CONFIG_STATUS_RESET 0x00\n+#define VIRTIO_CONFIG_STATUS_ACK 0x01\n+#define VIRTIO_CONFIG_STATUS_DRIVER 0x02\n+#define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04\n+#define VIRTIO_CONFIG_STATUS_FEATURES_OK 0x08\n+#define VIRTIO_CONFIG_STATUS_FAILED 0x80\n+\n+/*\n+ * Each virtqueue indirect descriptor list must be physically contiguous.\n+ * To allow us to malloc(9) each list individually, limit the number\n+ * supported to what will fit in one page. With 4KB pages, this is a limit\n+ * of 256 descriptors. If there is ever a need for more, we can switch to\n+ * contigmalloc(9) for the larger allocations, similar to what\n+ * bus_dmamem_alloc(9) does.\n+ *\n+ * Note the sizeof(struct vring_desc) is 16 bytes.\n+ */\n+#define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16))\n+\n+/* Do we get callbacks when the ring is completely used, even if we've\n+ * suppressed them? */\n+#define VIRTIO_F_NOTIFY_ON_EMPTY\t24\n+\n+/* Can the device handle any descriptor layout? */\n+#define VIRTIO_F_ANY_LAYOUT\t\t27\n+\n+/* We support indirect buffer descriptors */\n+#define VIRTIO_RING_F_INDIRECT_DESC\t28\n+\n+#define VIRTIO_F_VERSION_1\t\t32\n+#define VIRTIO_F_IOMMU_PLATFORM\t33\n+\n+/*\n+ * Some VirtIO feature bits (currently bits 28 through 31) are\n+ * reserved for the transport being used (eg. virtio_ring), the\n+ * rest are per-device feature bits.\n+ */\n+#define VIRTIO_TRANSPORT_F_START 28\n+\n+#ifndef VIRTIO_TRANSPORT_F_END\n+#define VIRTIO_TRANSPORT_F_END 34\n+#endif\n+\n+/* The Guest publishes the used index for which it expects an interrupt\n+ * at the end of the avail ring. Host should ignore the avail->flags field. */\n+/* The Host publishes the avail index for which it expects a kick\n+ * at the end of the used ring. Guest should ignore the used->flags field. */\n+#define VIRTIO_RING_F_EVENT_IDX\t\t29\n+\n+/* Common configuration */\n+#define VIRTIO_PCI_CAP_COMMON_CFG\t1\n+/* Notifications */\n+#define VIRTIO_PCI_CAP_NOTIFY_CFG\t2\n+/* ISR Status */\n+#define VIRTIO_PCI_CAP_ISR_CFG\t\t3\n+/* Device specific configuration */\n+#define VIRTIO_PCI_CAP_DEVICE_CFG\t4\n+/* PCI configuration access */\n+#define VIRTIO_PCI_CAP_PCI_CFG\t\t5\n+\n+/* This is the PCI capability header: */\n+struct virtio_pci_cap {\n+\tuint8_t cap_vndr;\t\t/* Generic PCI field: PCI_CAP_ID_VNDR */\n+\tuint8_t cap_next;\t\t/* Generic PCI field: next ptr. */\n+\tuint8_t cap_len;\t\t/* Generic PCI field: capability length */\n+\tuint8_t cfg_type;\t\t/* Identifies the structure. */\n+\tuint8_t bar;\t\t\t/* Where to find it. */\n+\tuint8_t padding[3];\t\t/* Pad to full dword. */\n+\tuint32_t offset;\t\t/* Offset within bar. */\n+\tuint32_t length;\t\t/* Length of the structure, in bytes. */\n+};\n+\n+struct virtio_pci_notify_cap {\n+\tstruct virtio_pci_cap cap;\n+\tuint32_t notify_off_multiplier;\t/* Multiplier for queue_notify_off. */\n+};\n+\n+/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */\n+struct virtio_pci_common_cfg {\n+\t/* About the whole device. */\n+\tuint32_t device_feature_select;\t/* read-write */\n+\tuint32_t device_feature;\t/* read-only */\n+\tuint32_t guest_feature_select;\t/* read-write */\n+\tuint32_t guest_feature;\t\t/* read-write */\n+\tuint16_t msix_config;\t\t/* read-write */\n+\tuint16_t num_queues;\t\t/* read-only */\n+\tuint8_t device_status;\t\t/* read-write */\n+\tuint8_t config_generation;\t/* read-only */\n+\n+\t/* About a specific virtqueue. */\n+\tuint16_t queue_select;\t\t/* read-write */\n+\tuint16_t queue_size;\t\t/* read-write, power of 2. */\n+\tuint16_t queue_msix_vector;\t/* read-write */\n+\tuint16_t queue_enable;\t\t/* read-write */\n+\tuint16_t queue_notify_off;\t/* read-only */\n+\tuint32_t queue_desc_lo;\t\t/* read-write */\n+\tuint32_t queue_desc_hi;\t\t/* read-write */\n+\tuint32_t queue_avail_lo;\t/* read-write */\n+\tuint32_t queue_avail_hi;\t/* read-write */\n+\tuint32_t queue_used_lo;\t\t/* read-write */\n+\tuint32_t queue_used_hi;\t\t/* read-write */\n+};\n+\n+struct virtio_hw;\n+\n+struct virtio_pci_ops {\n+\tvoid (*read_dev_cfg)(struct virtio_hw *hw, size_t offset,\n+\t\t\t void *dst, int len);\n+\tvoid (*write_dev_cfg)(struct virtio_hw *hw, size_t offset,\n+\t\t\t const void *src, int len);\n+\tvoid (*reset)(struct virtio_hw *hw);\n+\n+\tuint8_t (*get_status)(struct virtio_hw *hw);\n+\tvoid (*set_status)(struct virtio_hw *hw, uint8_t status);\n+\n+\tuint64_t (*get_features)(struct virtio_hw *hw);\n+\tvoid (*set_features)(struct virtio_hw *hw, uint64_t features);\n+\n+\tuint8_t (*get_isr)(struct virtio_hw *hw);\n+\n+\tuint16_t (*set_config_irq)(struct virtio_hw *hw, uint16_t vec);\n+\n+\tuint16_t (*set_queue_irq)(struct virtio_hw *hw, struct virtqueue *vq,\n+\t\t\tuint16_t vec);\n+\n+\tuint16_t (*get_queue_num)(struct virtio_hw *hw, uint16_t queue_id);\n+\tint (*setup_queue)(struct virtio_hw *hw, struct virtqueue *vq);\n+\tvoid (*del_queue)(struct virtio_hw *hw, struct virtqueue *vq);\n+\tvoid (*notify_queue)(struct virtio_hw *hw, struct virtqueue *vq);\n+};\n+\n+struct virtio_hw {\n+\tuint64_t guest_features;\n+\tuint32_t max_queue_pairs;\n+\tuint16_t started;\n+\tuint8_t\t use_msix;\n+\tuint16_t internal_id;\n+\tuint32_t notify_off_multiplier;\n+\tuint8_t *isr;\n+\tuint16_t *notify_base;\n+\tstruct virtio_pci_common_cfg *common_cfg;\n+\tvoid\t *dev_cfg;\n+\t/*\n+\t * App management thread and virtio interrupt handler thread\n+\t * both can change device state, this lock is meant to avoid\n+\t * such a contention.\n+\t */\n+\trte_spinlock_t state_lock;\n+\n+\tstruct virtqueue **vqs;\n+};\n+\n+/*\n+ * While virtio_hw is stored in shared memory, this structure stores\n+ * some infos that may vary in the multiple process model locally.\n+ * For example, the vtpci_ops pointer.\n+ */\n+struct virtio_hw_internal {\n+\tconst struct virtio_pci_ops *vtpci_ops;\n+};\n+\n+#define VTPCI_OPS(hw)\t(virtio_pci_hw_internal[(hw)->internal_id].vtpci_ops)\n+\n+extern struct virtio_hw_internal virtio_pci_hw_internal[8];\n+\n+/*\n+ * How many bits to shift physical queue address written to QUEUE_PFN.\n+ * 12 is historical, and due to x86 page size.\n+ */\n+#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12\n+\n+/* The alignment to use between consumer and producer parts of vring. */\n+#define VIRTIO_PCI_VRING_ALIGN 4096\n+\n+enum virtio_msix_status {\n+\tVIRTIO_MSIX_NONE = 0,\n+\tVIRTIO_MSIX_DISABLED = 1,\n+\tVIRTIO_MSIX_ENABLED = 2\n+};\n+\n+static inline int\n+virtio_pci_with_feature(struct virtio_hw *hw, uint64_t bit)\n+{\n+\treturn (hw->guest_features & (1ULL << bit)) != 0;\n+}\n+\n+/*\n+ * Function declaration from virtio_pci.c\n+ */\n+int virtio_pci_init(struct rte_pci_device *dev, struct virtio_hw *hw);\n+void virtio_pci_reset(struct virtio_hw *);\n+\n+void virtio_pci_reinit_complete(struct virtio_hw *);\n+\n+uint8_t virtio_pci_get_status(struct virtio_hw *);\n+void virtio_pci_set_status(struct virtio_hw *, uint8_t);\n+\n+uint64_t virtio_pci_negotiate_features(struct virtio_hw *, uint64_t);\n+\n+void virtio_pci_write_dev_config(struct virtio_hw *, size_t, const void *, int);\n+\n+void virtio_pci_read_dev_config(struct virtio_hw *, size_t, void *, int);\n+\n+uint8_t virtio_pci_isr(struct virtio_hw *);\n+\n+enum virtio_msix_status virtio_pci_msix_detect(struct rte_pci_device *dev);\n+\n+extern const struct virtio_pci_ops virtio_pci_modern_ops;\n+\n+#endif /* _VIRTIO_PCI_H_ */\ndiff --git a/drivers/virtio_vhost_user/virtqueue.h b/drivers/virtio_vhost_user/virtqueue.h\nnew file mode 100644\nindex 0000000..e2ac78e\n--- /dev/null\n+++ b/drivers/virtio_vhost_user/virtqueue.h\n@@ -0,0 +1,181 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2014 Intel Corporation\n+ */\n+\n+/* XXX This file is based on drivers/net/virtio/virtqueue.h. It would be\n+ * better to create a shared rte_virtio library instead of duplicating this\n+ * code.\n+ */\n+\n+#ifndef _VIRTQUEUE_H_\n+#define _VIRTQUEUE_H_\n+\n+#include <stdint.h>\n+#include <linux/virtio_ring.h>\n+\n+#include <rte_atomic.h>\n+#include <rte_memory.h>\n+#include <rte_mempool.h>\n+\n+#include \"virtio_pci.h\"\n+\n+/*\n+ * Per virtio_config.h in Linux.\n+ * For virtio_pci on SMP, we don't need to order with respect to MMIO\n+ * accesses through relaxed memory I/O windows, so smp_mb() et al are\n+ * sufficient.\n+ *\n+ */\n+#define virtio_mb()\trte_smp_mb()\n+#define virtio_rmb()\trte_smp_rmb()\n+#define virtio_wmb()\trte_smp_wmb()\n+\n+#define VIRTQUEUE_MAX_NAME_SZ 32\n+\n+/**\n+ * The maximum virtqueue size is 2^15. Use that value as the end of\n+ * descriptor chain terminator since it will never be a valid index\n+ * in the descriptor table. This is used to verify we are correctly\n+ * handling vq_free_cnt.\n+ */\n+#define VQ_RING_DESC_CHAIN_END 32768\n+\n+struct vq_desc_extra {\n+\tvoid *cookie;\n+\tuint16_t ndescs;\n+};\n+\n+struct virtqueue {\n+\tstruct virtio_hw *hw; /**< virtio_hw structure pointer. */\n+\tstruct vring vq_ring; /**< vring keeping desc, used and avail */\n+\t/**\n+\t * Last consumed descriptor in the used table,\n+\t * trails vq_ring.used->idx.\n+\t */\n+\tuint16_t vq_used_cons_idx;\n+\tuint16_t vq_nentries; /**< vring desc numbers */\n+\tuint16_t vq_free_cnt; /**< num of desc available */\n+\tuint16_t vq_avail_idx; /**< sync until needed */\n+\tuint16_t vq_free_thresh; /**< free threshold */\n+\n+\tvoid *vq_ring_virt_mem; /**< linear address of vring*/\n+\tunsigned int vq_ring_size;\n+\n+\trte_iova_t vq_ring_mem; /**< physical address of vring */\n+\n+\tconst struct rte_memzone *mz; /**< memzone backing vring */\n+\n+\t/**\n+\t * Head of the free chain in the descriptor table. If\n+\t * there are no free descriptors, this will be set to\n+\t * VQ_RING_DESC_CHAIN_END.\n+\t */\n+\tuint16_t vq_desc_head_idx;\n+\tuint16_t vq_desc_tail_idx;\n+\tuint16_t vq_queue_index; /**< PCI queue index */\n+\tuint16_t *notify_addr;\n+\tstruct vq_desc_extra vq_descx[0];\n+};\n+\n+/* Chain all the descriptors in the ring with an END */\n+static inline void\n+vring_desc_init(struct vring_desc *dp, uint16_t n)\n+{\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < n - 1; i++)\n+\t\tdp[i].next = (uint16_t)(i + 1);\n+\tdp[i].next = VQ_RING_DESC_CHAIN_END;\n+}\n+\n+/**\n+ * Tell the backend not to interrupt us.\n+ */\n+static inline void\n+virtqueue_disable_intr(struct virtqueue *vq)\n+{\n+\tvq->vq_ring.avail->flags |= VRING_AVAIL_F_NO_INTERRUPT;\n+}\n+\n+/**\n+ * Tell the backend to interrupt us.\n+ */\n+static inline void\n+virtqueue_enable_intr(struct virtqueue *vq)\n+{\n+\tvq->vq_ring.avail->flags &= (~VRING_AVAIL_F_NO_INTERRUPT);\n+}\n+\n+/**\n+ * Dump virtqueue internal structures, for debug purpose only.\n+ */\n+void virtqueue_dump(struct virtqueue *vq);\n+\n+static inline int\n+virtqueue_full(const struct virtqueue *vq)\n+{\n+\treturn vq->vq_free_cnt == 0;\n+}\n+\n+#define VIRTQUEUE_NUSED(vq) ((uint16_t)((vq)->vq_ring.used->idx - (vq)->vq_used_cons_idx))\n+\n+static inline void\n+vq_update_avail_idx(struct virtqueue *vq)\n+{\n+\tvirtio_wmb();\n+\tvq->vq_ring.avail->idx = vq->vq_avail_idx;\n+}\n+\n+static inline void\n+vq_update_avail_ring(struct virtqueue *vq, uint16_t desc_idx)\n+{\n+\tuint16_t avail_idx;\n+\t/*\n+\t * Place the head of the descriptor chain into the next slot and make\n+\t * it usable to the host. The chain is made available now rather than\n+\t * deferring to virtqueue_notify() in the hopes that if the host is\n+\t * currently running on another CPU, we can keep it processing the new\n+\t * descriptor.\n+\t */\n+\tavail_idx = (uint16_t)(vq->vq_avail_idx & (vq->vq_nentries - 1));\n+\tif (unlikely(vq->vq_ring.avail->ring[avail_idx] != desc_idx))\n+\t\tvq->vq_ring.avail->ring[avail_idx] = desc_idx;\n+\tvq->vq_avail_idx++;\n+}\n+\n+static inline int\n+virtqueue_kick_prepare(struct virtqueue *vq)\n+{\n+\treturn !(vq->vq_ring.used->flags & VRING_USED_F_NO_NOTIFY);\n+}\n+\n+static inline void\n+virtqueue_notify(struct virtqueue *vq)\n+{\n+\t/*\n+\t * Ensure updated avail->idx is visible to host.\n+\t * For virtio on IA, the notificaiton is through io port operation\n+\t * which is a serialization instruction itself.\n+\t */\n+\tVTPCI_OPS(vq->hw)->notify_queue(vq->hw, vq);\n+}\n+\n+#ifdef RTE_LIBRTE_VIRTIO_DEBUG_DUMP\n+#define VIRTQUEUE_DUMP(vq) do { \\\n+\tuint16_t used_idx, nused; \\\n+\tused_idx = (vq)->vq_ring.used->idx; \\\n+\tnused = (uint16_t)(used_idx - (vq)->vq_used_cons_idx); \\\n+\tRTE_LOG(DEBUG, VIRTIO_PCI_CONFIG, \\\n+\t \"VQ: - size=%d; free=%d; used=%d; desc_head_idx=%d;\" \\\n+\t \" avail.idx=%d; used_cons_idx=%d; used.idx=%d;\" \\\n+\t \" avail.flags=0x%x; used.flags=0x%x\\n\", \\\n+\t (vq)->vq_nentries, (vq)->vq_free_cnt, nused, \\\n+\t (vq)->vq_desc_head_idx, (vq)->vq_ring.avail->idx, \\\n+\t (vq)->vq_used_cons_idx, (vq)->vq_ring.used->idx, \\\n+\t (vq)->vq_ring.avail->flags, (vq)->vq_ring.used->flags); \\\n+} while (0)\n+#else\n+#define VIRTQUEUE_DUMP(vq) do { } while (0)\n+#endif\n+\n+#endif /* _VIRTQUEUE_H_ */\n", "prefixes": [ "18/28" ] }