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GET /api/patches/54868/?format=api
{ "id": 54868, "url": "http://patches.dpdk.org/api/patches/54868/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-19-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190617155537.36144-19-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190617155537.36144-19-jerinj@marvell.com", "date": "2019-06-17T15:55:28", "name": "[v3,18/27] mempool/octeontx2: add NPA HW operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "57f1141e7c34f7b906f4cffb3867cf2fb6e87c2c", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-19-jerinj@marvell.com/mbox/", "series": [ { "id": 5036, "url": "http://patches.dpdk.org/api/series/5036/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5036", "date": "2019-06-17T15:55:10", "name": "OCTEON TX2 common and mempool driver", "version": 3, "mbox": "http://patches.dpdk.org/series/5036/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54868/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/54868/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BA4C01BFB8;\n\tMon, 17 Jun 2019 17:57:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9394E1BF87\n\tfor <dev@dpdk.org>; Mon, 17 Jun 2019 17:56:47 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5HFprCV001049 for <dev@dpdk.org>; Mon, 17 Jun 2019 08:56:47 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2t506hyb1a-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Mon, 17 Jun 2019 08:56:46 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tMon, 17 Jun 2019 08:56:45 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Mon, 17 Jun 2019 08:56:45 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 904E53F7040;\n\tMon, 17 Jun 2019 08:56:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=n//xOsoCq7QWzfqAT50Hxj+CLCwJmhcdLcYHfysEmmI=;\n\tb=UjPE7QnfAivlskHDQPdjzFTMCfeBmX78unpc8pEqFyy64SBhJskkfRVXgid09CTahkQv\n\thGoXB3CKJt9xZIzromlHUxiVkUq21kGKCrNQ035DGeu9C+Zg+EIVrtshdTVJyvX5q+mb\n\tHHO4dQRY5kV22DWC1q+iult8lGSO7n+6c36l9pAVq0A7wMnlHJixShRAVL7w1+5VGl7f\n\tc0ztlTjOYeJ1F/rhYeP036r6qf8Vj/kBA9waid7xIk+zQgfKZabJaDjhcCcx4Pk2WckU\n\tYdz7hPwRCP9mdtGaTbVwlTlDgGuhhGTLBIyXGRv4d+CVDiyCvVWvGhgyPie1huRMX4By\n\t/Q== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "CC": "Kiran Kumar K <kirankumark@marvell.com>", "Date": "Mon, 17 Jun 2019 21:25:28 +0530", "Message-ID": "<20190617155537.36144-19-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190617155537.36144-1-jerinj@marvell.com>", "References": "<20190601014905.45531-1-jerinj@marvell.com>\n\t<20190617155537.36144-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-17_07:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 18/27] mempool/octeontx2: add NPA HW operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nImplement the low-level NPA HW operations such as\nalloc, free memory, etc.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n drivers/mempool/octeontx2/otx2_mempool.h | 146 +++++++++++++++++++++++\n 1 file changed, 146 insertions(+)", "diff": "diff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h\nindex e1c255c60..871b45870 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.h\n+++ b/drivers/mempool/octeontx2/otx2_mempool.h\n@@ -48,6 +48,152 @@ struct otx2_npa_lf {\n \n #define AURA_ID_MASK (BIT_ULL(16) - 1)\n \n+/*\n+ * Generate 64bit handle to have optimized alloc and free aura operation.\n+ * 0 - AURA_ID_MASK for storing the aura_id.\n+ * AURA_ID_MASK+1 - (2^64 - 1) for storing the lf base address.\n+ * This scheme is valid when OS can give AURA_ID_MASK\n+ * aligned address for lf base address.\n+ */\n+static inline uint64_t\n+npa_lf_aura_handle_gen(uint32_t aura_id, uintptr_t addr)\n+{\n+\tuint64_t val;\n+\n+\tval = aura_id & AURA_ID_MASK;\n+\treturn (uint64_t)addr | val;\n+}\n+\n+static inline uint64_t\n+npa_lf_aura_handle_to_aura(uint64_t aura_handle)\n+{\n+\treturn aura_handle & AURA_ID_MASK;\n+}\n+\n+static inline uintptr_t\n+npa_lf_aura_handle_to_base(uint64_t aura_handle)\n+{\n+\treturn (uintptr_t)(aura_handle & ~AURA_ID_MASK);\n+}\n+\n+static inline uint64_t\n+npa_lf_aura_op_alloc(uint64_t aura_handle, const int drop)\n+{\n+\tuint64_t wdata = npa_lf_aura_handle_to_aura(aura_handle);\n+\n+\tif (drop)\n+\t\twdata |= BIT_ULL(63); /* DROP */\n+\n+\treturn otx2_atomic64_add_nosync(wdata,\n+\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n+\t\tNPA_LF_AURA_OP_ALLOCX(0)));\n+}\n+\n+static inline void\n+npa_lf_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova)\n+{\n+\tuint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);\n+\n+\tif (fabs)\n+\t\treg |= BIT_ULL(63); /* FABS */\n+\n+\totx2_store_pair(iova, reg,\n+\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0);\n+}\n+\n+static inline uint64_t\n+npa_lf_aura_op_cnt_get(uint64_t aura_handle)\n+{\n+\tuint64_t wdata;\n+\tuint64_t reg;\n+\n+\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n+\n+\treg = otx2_atomic64_add_nosync(wdata,\n+\t\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n+\t\t\t NPA_LF_AURA_OP_CNT));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */)\n+\t\treturn 0;\n+\telse\n+\t\treturn reg & 0xFFFFFFFFF;\n+}\n+\n+static inline void\n+npa_lf_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)\n+{\n+\tuint64_t reg = count & (BIT_ULL(36) - 1);\n+\n+\tif (sign)\n+\t\treg |= BIT_ULL(43); /* CNT_ADD */\n+\n+\treg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);\n+\n+\totx2_write64(reg,\n+\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT);\n+}\n+\n+static inline uint64_t\n+npa_lf_aura_op_limit_get(uint64_t aura_handle)\n+{\n+\tuint64_t wdata;\n+\tuint64_t reg;\n+\n+\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n+\n+\treg = otx2_atomic64_add_nosync(wdata,\n+\t\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n+\t\t\t NPA_LF_AURA_OP_LIMIT));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */)\n+\t\treturn 0;\n+\telse\n+\t\treturn reg & 0xFFFFFFFFF;\n+}\n+\n+static inline void\n+npa_lf_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)\n+{\n+\tuint64_t reg = limit & (BIT_ULL(36) - 1);\n+\n+\treg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);\n+\n+\totx2_write64(reg,\n+\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT);\n+}\n+\n+static inline uint64_t\n+npa_lf_aura_op_available(uint64_t aura_handle)\n+{\n+\tuint64_t wdata;\n+\tuint64_t reg;\n+\n+\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n+\n+\treg = otx2_atomic64_add_nosync(wdata,\n+\t\t\t (int64_t *)(npa_lf_aura_handle_to_base(\n+\t\t\t aura_handle) + NPA_LF_POOL_OP_AVAILABLE));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */)\n+\t\treturn 0;\n+\telse\n+\t\treturn reg & 0xFFFFFFFFF;\n+}\n+\n+static inline void\n+npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,\n+\t\t\t\tuint64_t end_iova)\n+{\n+\tuint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);\n+\n+\totx2_store_pair(start_iova, reg,\n+\t\t\tnpa_lf_aura_handle_to_base(aura_handle) +\n+\t\t\tNPA_LF_POOL_OP_PTR_START0);\n+\totx2_store_pair(end_iova, reg,\n+\t\t\tnpa_lf_aura_handle_to_base(aura_handle) +\n+\t\t\tNPA_LF_POOL_OP_PTR_END0);\n+}\n+\n /* NPA LF */\n int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n int otx2_npa_lf_fini(void);\n", "prefixes": [ "v3", "18/27" ] }