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GET /api/patches/54866/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54866,
    "url": "http://patches.dpdk.org/api/patches/54866/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-18-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190617155537.36144-18-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190617155537.36144-18-jerinj@marvell.com",
    "date": "2019-06-17T15:55:27",
    "name": "[v3,17/27] drivers: add init and fini on octeontx2 NPA object",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "f20b58a5929b788564197f7eeadcf334e511f77f",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-18-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5036,
            "url": "http://patches.dpdk.org/api/series/5036/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5036",
            "date": "2019-06-17T15:55:10",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5036/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54866/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/54866/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5ABE71BFB2;\n\tMon, 17 Jun 2019 17:57:09 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 8849F1BEEC\n\tfor <dev@dpdk.org>; Mon, 17 Jun 2019 17:56:45 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5HForA2000541 for <dev@dpdk.org>; Mon, 17 Jun 2019 08:56:44 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2t68rp9bg2-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Mon, 17 Jun 2019 08:56:44 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tMon, 17 Jun 2019 08:56:42 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Mon, 17 Jun 2019 08:56:42 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id DA3913F7041;\n\tMon, 17 Jun 2019 08:56:40 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : subject\n\t: date : message-id : in-reply-to : references : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=iBEiBmRISVXNHPIaWIAZkTkAtZbJ2RJUE1hQY8UshjU=;\n\tb=ar3fl4s+zt9ZzcM4cwYwldRrZdXcSyv6lHhCrJraSXNhsD2SneWGax7c44J/vUiW5M7T\n\tkQ3lLFOeDUNzP/Q0lDP5fCz/LkeNZSRYZrdNiDxbQSSmRUhiZaQU++piobBYI5y1rkAx\n\tFaM18prb4a3YQOiLWmz64YvE4boI5iVYNPUnBwMyXQEF+svbmnup1YcHcQFpdTmHMPRN\n\tPLjQTwZUUGg4JqxjFKyEXoh1Y50uM7LYB8QAt91NgnK+3tKVQlUJBkuwE6BL/oH2TBdK\n\t8vBQ/B1MOurDV6vsUhe2JTAvkqmb1qesYcjM2WTuvCUXYFSUY5cX66Bm3Dp9s+fLy4ez\n\tmA== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "Date": "Mon, 17 Jun 2019 21:25:27 +0530",
        "Message-ID": "<20190617155537.36144-18-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190617155537.36144-1-jerinj@marvell.com>",
        "References": "<20190601014905.45531-1-jerinj@marvell.com>\n\t<20190617155537.36144-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-17_07:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v3 17/27] drivers: add init and fini on octeontx2\n\tNPA object",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nNPA object needs to initialize memory for queue interrupts context,\npool resource management, etc. This patch adds support for initializing\nand finalizing the NPA object.\n\nThis patch also updates the otx2_npa_lf definition to meet the init/fini\nrequirements.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/common/octeontx2/Makefile             |   1 +\n drivers/common/octeontx2/meson.build          |   2 +-\n drivers/common/octeontx2/otx2_common.h        |   7 +-\n drivers/common/octeontx2/otx2_dev.h           |   1 +\n drivers/mempool/octeontx2/otx2_mempool.c      | 344 +++++++++++++++++-\n drivers/mempool/octeontx2/otx2_mempool.h      |  55 +++\n .../rte_mempool_octeontx2_version.map         |   4 +\n 7 files changed, 403 insertions(+), 11 deletions(-)\n create mode 100644 drivers/mempool/octeontx2/otx2_mempool.h",
    "diff": "diff --git a/drivers/common/octeontx2/Makefile b/drivers/common/octeontx2/Makefile\nindex 78243e555..fabc32537 100644\n--- a/drivers/common/octeontx2/Makefile\n+++ b/drivers/common/octeontx2/Makefile\n@@ -11,6 +11,7 @@ LIB = librte_common_octeontx2.a\n \n CFLAGS += $(WERROR_FLAGS)\n CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n CFLAGS += -I$(RTE_SDK)/drivers/bus/pci\n \n ifneq ($(CONFIG_RTE_ARCH_64),y)\ndiff --git a/drivers/common/octeontx2/meson.build b/drivers/common/octeontx2/meson.build\nindex 44ac90085..b79145788 100644\n--- a/drivers/common/octeontx2/meson.build\n+++ b/drivers/common/octeontx2/meson.build\n@@ -22,4 +22,4 @@ endforeach\n \n deps = ['eal', 'pci', 'ethdev']\n includes += include_directories('../../common/octeontx2',\n-\t\t'../../bus/pci')\n+\t\t'../../mempool/octeontx2', '../../bus/pci')\ndiff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h\nindex cbc5c65a7..cdb25d9ed 100644\n--- a/drivers/common/octeontx2/otx2_common.h\n+++ b/drivers/common/octeontx2/otx2_common.h\n@@ -37,12 +37,7 @@\n #endif\n \n /* Intra device related functions */\n-struct otx2_npa_lf {\n-\tstruct otx2_mbox *mbox;\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct rte_intr_handle *intr_handle;\n-};\n-\n+struct otx2_npa_lf;\n struct otx2_idev_cfg {\n \tuint16_t sso_pf_func;\n \tuint16_t npa_pf_func;\ndiff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h\nindex 8fa5f32d2..be862ad1b 100644\n--- a/drivers/common/octeontx2/otx2_dev.h\n+++ b/drivers/common/octeontx2/otx2_dev.h\n@@ -10,6 +10,7 @@\n #include \"otx2_common.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_mbox.h\"\n+#include \"otx2_mempool.h\"\n \n /* Common HWCAP flags. Use from LSB bits */\n #define OTX2_HWCAP_F_VF\t\tBIT_ULL(0) /* VF device */\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c\nindex fd8e147f5..fa74b7532 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool.c\n@@ -2,12 +2,350 @@\n  * Copyright(C) 2019 Marvell International Ltd.\n  */\n \n+#include <rte_atomic.h>\n #include <rte_bus_pci.h>\n #include <rte_common.h>\n #include <rte_eal.h>\n+#include <rte_io.h>\n+#include <rte_malloc.h>\n+#include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n #include \"otx2_common.h\"\n+#include \"otx2_dev.h\"\n+#include \"otx2_mempool.h\"\n+\n+#define OTX2_NPA_DEV_NAME\tRTE_STR(otx2_npa_dev_)\n+#define OTX2_NPA_DEV_NAME_LEN\t(sizeof(OTX2_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)\n+\n+static inline int\n+npa_lf_alloc(struct otx2_npa_lf *lf)\n+{\n+\tstruct otx2_mbox *mbox = lf->mbox;\n+\tstruct npa_lf_alloc_req *req;\n+\tstruct npa_lf_alloc_rsp *rsp;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_npa_lf_alloc(mbox);\n+\treq->aura_sz = lf->aura_sz;\n+\treq->nr_pools = lf->nr_pools;\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn NPA_LF_ERR_ALLOC;\n+\n+\tlf->stack_pg_ptrs = rsp->stack_pg_ptrs;\n+\tlf->stack_pg_bytes = rsp->stack_pg_bytes;\n+\tlf->qints = rsp->qints;\n+\n+\treturn 0;\n+}\n+\n+static int\n+npa_lf_free(struct otx2_mbox *mbox)\n+{\n+\totx2_mbox_alloc_msg_npa_lf_free(mbox);\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static int\n+npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz,\n+\t    uint32_t nr_pools, struct otx2_mbox *mbox)\n+{\n+\tuint32_t i, bmp_sz;\n+\tint rc;\n+\n+\t/* Sanity checks */\n+\tif (!lf || !base || !mbox || !nr_pools)\n+\t\treturn NPA_LF_ERR_PARAM;\n+\n+\tif (base & AURA_ID_MASK)\n+\t\treturn NPA_LF_ERR_BASE_INVALID;\n+\n+\tif (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)\n+\t\treturn NPA_LF_ERR_PARAM;\n+\n+\tmemset(lf, 0x0, sizeof(*lf));\n+\tlf->base = base;\n+\tlf->aura_sz = aura_sz;\n+\tlf->nr_pools = nr_pools;\n+\tlf->mbox = mbox;\n+\n+\trc = npa_lf_alloc(lf);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\tbmp_sz = rte_bitmap_get_memory_footprint(nr_pools);\n+\n+\t/* Allocate memory for bitmap */\n+\tlf->npa_bmp_mem = rte_zmalloc(\"npa_bmp_mem\", bmp_sz,\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (lf->npa_bmp_mem == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto lf_free;\n+\t}\n+\n+\t/* Initialize pool resource bitmap array */\n+\tlf->npa_bmp = rte_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);\n+\tif (lf->npa_bmp == NULL) {\n+\t\trc = -EINVAL;\n+\t\tgoto bmap_mem_free;\n+\t}\n+\n+\t/* Mark all pools available */\n+\tfor (i = 0; i < nr_pools; i++)\n+\t\trte_bitmap_set(lf->npa_bmp, i);\n+\n+\t/* Allocate memory for qint context */\n+\tlf->npa_qint_mem = rte_zmalloc(\"npa_qint_mem\",\n+\t\t\tsizeof(struct otx2_npa_qint) * nr_pools, 0);\n+\tif (lf->npa_qint_mem == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto bmap_free;\n+\t}\n+\n+\treturn 0;\n+\n+bmap_free:\n+\trte_bitmap_free(lf->npa_bmp);\n+bmap_mem_free:\n+\trte_free(lf->npa_bmp_mem);\n+lf_free:\n+\tnpa_lf_free(lf->mbox);\n+exit:\n+\treturn rc;\n+}\n+\n+static int\n+npa_lf_fini(struct otx2_npa_lf *lf)\n+{\n+\tif (!lf)\n+\t\treturn NPA_LF_ERR_PARAM;\n+\n+\trte_free(lf->npa_qint_mem);\n+\trte_bitmap_free(lf->npa_bmp);\n+\trte_free(lf->npa_bmp_mem);\n+\n+\treturn npa_lf_free(lf->mbox);\n+\n+}\n+\n+static inline uint32_t\n+otx2_aura_size_to_u32(uint8_t val)\n+{\n+\tif (val == NPA_AURA_SZ_0)\n+\t\treturn 128;\n+\tif (val >= NPA_AURA_SZ_MAX)\n+\t\treturn BIT_ULL(20);\n+\n+\treturn 1 << (val + 6);\n+}\n+\n+static inline int\n+npa_lf_attach(struct otx2_mbox *mbox)\n+{\n+\tstruct rsrc_attach_req *req;\n+\n+\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n+\treq->npalf = true;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static inline int\n+npa_lf_detach(struct otx2_mbox *mbox)\n+{\n+\tstruct rsrc_detach_req *req;\n+\n+\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n+\treq->npalf = true;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static inline int\n+npa_lf_get_msix_offset(struct otx2_mbox *mbox, uint16_t *npa_msixoff)\n+{\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tint rc;\n+\n+\t/* Get NPA and NIX MSIX vector offsets */\n+\totx2_mbox_alloc_msg_msix_offset(mbox);\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n+\n+\t*npa_msixoff = msix_rsp->npa_msixoff;\n+\n+\treturn rc;\n+}\n+\n+/**\n+ * @internal\n+ * Finalize NPA LF.\n+ */\n+int\n+otx2_npa_lf_fini(void)\n+{\n+\tstruct otx2_idev_cfg *idev;\n+\tint rc = 0;\n+\n+\tidev = otx2_intra_dev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tif (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {\n+\t\trc |= npa_lf_fini(idev->npa_lf);\n+\t\trc |= npa_lf_detach(idev->npa_lf->mbox);\n+\t\totx2_npa_set_defaults(idev);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+/**\n+ * @internal\n+ * Initialize NPA LF.\n+ */\n+int\n+otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n+{\n+\tstruct otx2_dev *dev = otx2_dev;\n+\tstruct otx2_idev_cfg *idev;\n+\tstruct otx2_npa_lf *lf;\n+\tuint16_t npa_msixoff;\n+\tuint32_t nr_pools;\n+\tuint8_t aura_sz;\n+\tint rc;\n+\n+\tidev = otx2_intra_dev_get_cfg();\n+\tif (idev == NULL)\n+\t\treturn -ENOMEM;\n+\n+\t/* Is NPA LF initialized by any another driver? */\n+\tif (rte_atomic16_add_return(&idev->npa_refcnt, 1) == 1) {\n+\n+\t\trc = npa_lf_attach(dev->mbox);\n+\t\tif (rc)\n+\t\t\tgoto fail;\n+\n+\t\trc = npa_lf_get_msix_offset(dev->mbox, &npa_msixoff);\n+\t\tif (rc)\n+\t\t\tgoto npa_detach;\n+\n+\t\taura_sz = NPA_AURA_SZ_128;\n+\t\tnr_pools = otx2_aura_size_to_u32(aura_sz);\n+\n+\t\tlf = &dev->npalf;\n+\t\trc = npa_lf_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),\n+\t\t\t\t\taura_sz, nr_pools, dev->mbox);\n+\n+\t\tif (rc)\n+\t\t\tgoto npa_detach;\n+\n+\t\tlf->pf_func = dev->pf_func;\n+\t\tlf->npa_msixoff = npa_msixoff;\n+\t\tlf->intr_handle = &pci_dev->intr_handle;\n+\t\tlf->pci_dev = pci_dev;\n+\n+\t\tidev->npa_pf_func = dev->pf_func;\n+\t\tidev->npa_lf = lf;\n+\t\trte_smp_wmb();\n+\n+\t\trte_mbuf_set_platform_mempool_ops(\"octeontx2_npa\");\n+\t\totx2_npa_dbg(\"npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x\",\n+\t\t\t     lf, nr_pools, aura_sz, lf->pf_func, npa_msixoff);\n+\t}\n+\n+\treturn 0;\n+\n+npa_detach:\n+\tnpa_lf_detach(dev->mbox);\n+fail:\n+\trte_atomic16_dec(&idev->npa_refcnt);\n+\treturn rc;\n+}\n+\n+static inline char*\n+otx2_npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)\n+{\n+\tsnprintf(name, OTX2_NPA_DEV_NAME_LEN,\n+\t\t OTX2_NPA_DEV_NAME  PCI_PRI_FMT,\n+\t\t pci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t pci_dev->addr.devid, pci_dev->addr.function);\n+\n+\treturn name;\n+}\n+\n+static int\n+otx2_npa_init(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[OTX2_NPA_DEV_NAME_LEN];\n+\tconst struct rte_memzone *mz;\n+\tstruct otx2_dev *dev;\n+\tint rc = -ENOMEM;\n+\n+\tmz = rte_memzone_reserve_aligned(otx2_npa_dev_to_name(pci_dev, name),\n+\t\t\t\t\t sizeof(*dev), SOCKET_ID_ANY,\n+\t\t\t\t\t 0, OTX2_ALIGN);\n+\tif (mz == NULL)\n+\t\tgoto error;\n+\n+\tdev = mz->addr;\n+\n+\t/* Initialize the base otx2_dev object */\n+\trc = otx2_dev_init(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto malloc_fail;\n+\n+\t/* Grab the NPA LF if required */\n+\trc = otx2_npa_lf_init(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto dev_uninit;\n+\n+\tdev->drv_inited = true;\n+\treturn 0;\n+\n+dev_uninit:\n+\totx2_npa_lf_fini();\n+\totx2_dev_fini(pci_dev, dev);\n+malloc_fail:\n+\trte_memzone_free(mz);\n+error:\n+\totx2_err(\"Failed to initialize npa device rc=%d\", rc);\n+\treturn rc;\n+}\n+\n+static int\n+otx2_npa_fini(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[OTX2_NPA_DEV_NAME_LEN];\n+\tconst struct rte_memzone *mz;\n+\tstruct otx2_dev *dev;\n+\n+\tmz = rte_memzone_lookup(otx2_npa_dev_to_name(pci_dev, name));\n+\tif (mz == NULL)\n+\t\treturn -EINVAL;\n+\n+\tdev = mz->addr;\n+\tif (!dev->drv_inited)\n+\t\tgoto dev_fini;\n+\n+\tdev->drv_inited = false;\n+\totx2_npa_lf_fini();\n+\n+dev_fini:\n+\tif (otx2_npa_lf_active(dev)) {\n+\t\totx2_info(\"%s: common resource in use by other devices\",\n+\t\t\t  pci_dev->name);\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\totx2_dev_fini(pci_dev, dev);\n+\trte_memzone_free(mz);\n+\n+\treturn 0;\n+}\n \n static int\n npa_remove(struct rte_pci_device *pci_dev)\n@@ -15,8 +353,7 @@ npa_remove(struct rte_pci_device *pci_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n-\tRTE_SET_USED(pci_dev);\n-\treturn 0;\n+\treturn otx2_npa_fini(pci_dev);\n }\n \n static int\n@@ -27,8 +364,7 @@ npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n-\tRTE_SET_USED(pci_dev);\n-\treturn 0;\n+\treturn otx2_npa_init(pci_dev);\n }\n \n static const struct rte_pci_id pci_npa_map[] = {\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h\nnew file mode 100644\nindex 000000000..e1c255c60\n--- /dev/null\n+++ b/drivers/mempool/octeontx2/otx2_mempool.h\n@@ -0,0 +1,55 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_MEMPOOL_H__\n+#define __OTX2_MEMPOOL_H__\n+\n+#include <rte_bitmap.h>\n+#include <rte_bus_pci.h>\n+#include <rte_devargs.h>\n+#include <rte_mempool.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_mbox.h\"\n+\n+enum npa_lf_status {\n+\tNPA_LF_ERR_PARAM\t    = -512,\n+\tNPA_LF_ERR_ALLOC\t    = -513,\n+\tNPA_LF_ERR_INVALID_BLOCK_SZ = -514,\n+\tNPA_LF_ERR_AURA_ID_ALLOC    = -515,\n+\tNPA_LF_ERR_AURA_POOL_INIT   = -516,\n+\tNPA_LF_ERR_AURA_POOL_FINI   = -517,\n+\tNPA_LF_ERR_BASE_INVALID     = -518,\n+};\n+\n+struct otx2_npa_lf;\n+struct otx2_npa_qint {\n+\tstruct otx2_npa_lf *lf;\n+\tuint8_t qintx;\n+};\n+\n+struct otx2_npa_lf {\n+\tuint16_t qints;\n+\tuintptr_t base;\n+\tuint8_t aura_sz;\n+\tuint16_t pf_func;\n+\tuint32_t nr_pools;\n+\tvoid *npa_bmp_mem;\n+\tvoid *npa_qint_mem;\n+\tuint16_t npa_msixoff;\n+\tstruct otx2_mbox *mbox;\n+\tuint32_t stack_pg_ptrs;\n+\tuint32_t stack_pg_bytes;\n+\tstruct rte_bitmap *npa_bmp;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct rte_intr_handle *intr_handle;\n+};\n+\n+#define AURA_ID_MASK  (BIT_ULL(16) - 1)\n+\n+/* NPA LF */\n+int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n+int otx2_npa_lf_fini(void);\n+\n+#endif /* __OTX2_MEMPOOL_H__ */\ndiff --git a/drivers/mempool/octeontx2/rte_mempool_octeontx2_version.map b/drivers/mempool/octeontx2/rte_mempool_octeontx2_version.map\nindex 9a61188cd..d703368c3 100644\n--- a/drivers/mempool/octeontx2/rte_mempool_octeontx2_version.map\n+++ b/drivers/mempool/octeontx2/rte_mempool_octeontx2_version.map\n@@ -1,4 +1,8 @@\n DPDK_19.08 {\n+\tglobal:\n+\n+\totx2_npa_lf_init;\n+\totx2_npa_lf_fini;\n \n \tlocal: *;\n };\n",
    "prefixes": [
        "v3",
        "17/27"
    ]
}