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{
    "id": 54862,
    "url": "http://patches.dpdk.org/api/patches/54862/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-15-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190617155537.36144-15-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190617155537.36144-15-jerinj@marvell.com",
    "date": "2019-06-17T15:55:24",
    "name": "[v3,14/27] common/octeontx2: add FLR IRQ handler",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2937e128b05cd154806a833fba8a4f849350ab5f",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190617155537.36144-15-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5036,
            "url": "http://patches.dpdk.org/api/series/5036/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5036",
            "date": "2019-06-17T15:55:10",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5036/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54862/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/54862/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "Harman Kalra <hkalra@marvell.com>",
        "Date": "Mon, 17 Jun 2019 21:25:24 +0530",
        "Message-ID": "<20190617155537.36144-15-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190617155537.36144-1-jerinj@marvell.com>",
        "References": "<20190601014905.45531-1-jerinj@marvell.com>\n\t<20190617155537.36144-1-jerinj@marvell.com>",
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        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-17_07:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v3 14/27] common/octeontx2: add FLR IRQ handler",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nUpon receiving FLR request from VF, It is PF responsibly\nforward to AF and enable FLR for VFs.\n\nThis patch adds support for VF FLR support in PF.\n\nThis patch also add otx2_dev_active_vfs() API to find\nthe number of active VF for given PF.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/common/octeontx2/otx2_dev.c           | 180 ++++++++++++++++++\n .../rte_common_octeontx2_version.map          |   1 +\n 2 files changed, 181 insertions(+)",
    "diff": "diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c\nindex 09943855d..53a0c6efb 100644\n--- a/drivers/common/octeontx2/otx2_dev.c\n+++ b/drivers/common/octeontx2/otx2_dev.c\n@@ -51,6 +51,52 @@ mbox_mem_unmap(void *va, size_t size)\n \t\tmunmap(va, size);\n }\n \n+static int\n+pf_af_sync_msg(struct otx2_dev *dev, struct mbox_msghdr **rsp)\n+{\n+\tuint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n+\tvolatile uint64_t int_status;\n+\tstruct mbox_msghdr *msghdr;\n+\tuint64_t off;\n+\tint rc = 0;\n+\n+\t/* We need to disable PF interrupts. We are in timer interrupt */\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n+\n+\t/* Send message */\n+\totx2_mbox_msg_send(mbox, 0);\n+\n+\tdo {\n+\t\trte_delay_ms(sleep);\n+\t\ttimeout += sleep;\n+\t\tif (timeout >= MBOX_RSP_TIMEOUT) {\n+\t\t\totx2_err(\"Message timeout: %dms\", MBOX_RSP_TIMEOUT);\n+\t\t\trc = -EIO;\n+\t\t\tbreak;\n+\t\t}\n+\t\tint_status = otx2_read64(dev->bar2 + RVU_PF_INT);\n+\t} while ((int_status & 0x1) != 0x1);\n+\n+\t/* Clear */\n+\totx2_write64(int_status, dev->bar2 + RVU_PF_INT);\n+\n+\t/* Enable interrupts */\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n+\n+\tif (rc == 0) {\n+\t\t/* Get message */\n+\t\toff = mbox->rx_start +\n+\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\t\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);\n+\t\tif (rsp)\n+\t\t\t*rsp = msghdr;\n+\t\trc = msghdr->rc;\n+\t}\n+\n+\treturn rc;\n+}\n+\n static int\n af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)\n {\n@@ -703,6 +749,132 @@ mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n \t\treturn mbox_unregister_pf_irq(pci_dev, dev);\n }\n \n+static int\n+vf_flr_send_msg(struct otx2_dev *dev, uint16_t vf)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct msg_req *req;\n+\tint rc;\n+\n+\treq = otx2_mbox_alloc_msg_vf_flr(mbox);\n+\t/* Overwrite pcifunc to indicate VF */\n+\treq->hdr.pcifunc = otx2_pfvf_func(dev->pf, vf);\n+\n+\t/* Sync message in interrupt context */\n+\trc = pf_af_sync_msg(dev, NULL);\n+\tif (rc)\n+\t\totx2_err(\"Failed to send VF FLR mbox msg, rc=%d\", rc);\n+\n+\treturn rc;\n+}\n+\n+static void\n+otx2_pf_vf_flr_irq(void *param)\n+{\n+\tstruct otx2_dev *dev = (struct otx2_dev *)param;\n+\tuint16_t max_vf = 64, vf;\n+\tuintptr_t bar2;\n+\tuint64_t intr;\n+\tint i;\n+\n+\tmax_vf = (dev->maxvf > 0) ? dev->maxvf : 64;\n+\tbar2 = dev->bar2;\n+\n+\totx2_base_dbg(\"FLR VF interrupt: max_vf: %d\", max_vf);\n+\n+\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {\n+\t\tintr = otx2_read64(bar2 + RVU_PF_VFFLR_INTX(i));\n+\t\tif (!intr)\n+\t\t\tcontinue;\n+\n+\t\tfor (vf = 0; vf < max_vf; vf++) {\n+\t\t\tif (!(intr & (1ULL << vf)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tvf = 64 * i + vf;\n+\t\t\totx2_base_dbg(\"FLR: i :%d intr: 0x%\" PRIx64 \", vf-%d\",\n+\t\t\t\t      i, intr, vf);\n+\t\t\t/* Clear interrupt */\n+\t\t\totx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));\n+\t\t\t/* Disable the interrupt */\n+\t\t\totx2_write64(BIT_ULL(vf),\n+\t\t\t\t     bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));\n+\t\t\t/* Inform AF about VF reset */\n+\t\t\tvf_flr_send_msg(dev, vf);\n+\n+\t\t\t/* Signal FLR finish */\n+\t\t\totx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));\n+\t\t\t/* Enable interrupt */\n+\t\t\totx2_write64(~0ull,\n+\t\t\t\t     bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));\n+\t\t}\n+\t}\n+}\n+\n+static int\n+vf_flr_unregister_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint i;\n+\n+\totx2_base_dbg(\"Unregister VF FLR interrupts for %s\", pci_dev->name);\n+\n+\t/* HW clear irq */\n+\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; i++)\n+\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));\n+\n+\totx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,\n+\t\t\t    RVU_PF_INT_VEC_VFFLR0);\n+\n+\totx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,\n+\t\t\t    RVU_PF_INT_VEC_VFFLR1);\n+\n+\treturn 0;\n+}\n+\n+static int\n+vf_flr_register_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint i, rc;\n+\n+\totx2_base_dbg(\"Register VF FLR interrupts for %s\", pci_dev->name);\n+\n+\trc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,\n+\t\t\t       RVU_PF_INT_VEC_VFFLR0);\n+\tif (rc)\n+\t\totx2_err(\"Failed to init RVU_PF_INT_VEC_VFFLR0 rc=%d\", rc);\n+\n+\trc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,\n+\t\t\t       RVU_PF_INT_VEC_VFFLR1);\n+\tif (rc)\n+\t\totx2_err(\"Failed to init RVU_PF_INT_VEC_VFFLR1 rc=%d\", rc);\n+\n+\t/* Enable HW interrupt */\n+\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {\n+\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INTX(i));\n+\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFTRPENDX(i));\n+\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * @internal\n+ * Get number of active VFs for the given PF device.\n+ */\n+int\n+otx2_dev_active_vfs(void *otx2_dev)\n+{\n+\tstruct otx2_dev *dev = otx2_dev;\n+\tint i, count = 0;\n+\n+\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; i++)\n+\t\tcount += __builtin_popcount(dev->active_vfs[i]);\n+\n+\treturn count;\n+}\n+\n static void\n otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n {\n@@ -818,6 +990,12 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \t\t\tgoto mbox_fini;\n \t}\n \n+\t/* Register VF-FLR irq handlers */\n+\tif (otx2_dev_is_pf(dev)) {\n+\t\trc = vf_flr_register_irqs(pci_dev, dev);\n+\t\tif (rc)\n+\t\t\tgoto iounmap;\n+\t}\n \tdev->mbox_active = 1;\n \treturn rc;\n \n@@ -851,6 +1029,8 @@ otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n \n \tmbox_unregister_irq(pci_dev, dev);\n \n+\tif (otx2_dev_is_pf(dev))\n+\t\tvf_flr_unregister_irqs(pci_dev, dev);\n \t/* Release PF - VF */\n \tmbox = &dev->mbox_vfpf;\n \tif (mbox->hwbase && mbox->dev)\ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex efcf0cb55..2f4826311 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -1,6 +1,7 @@\n DPDK_19.08 {\n \tglobal:\n \n+\totx2_dev_active_vfs;\n \totx2_dev_fini;\n \totx2_dev_init;\n \n",
    "prefixes": [
        "v3",
        "14/27"
    ]
}