Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/54688/?format=api
{ "id": 54688, "url": "http://patches.dpdk.org/api/patches/54688/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-30-leyi.rong@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190611155221.2703-30-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190611155221.2703-30-leyi.rong@intel.com", "date": "2019-06-11T15:51:44", "name": "[v2,29/66] net/ice/base: call out dev/func caps when printing", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "74b84a3620ece932380fbebbafd333a4335422a8", "submitter": { "id": 1204, "url": "http://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-30-leyi.rong@intel.com/mbox/", "series": [ { "id": 4981, "url": "http://patches.dpdk.org/api/series/4981/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4981", "date": "2019-06-11T15:51:15", "name": "shared code update", "version": 2, "mbox": "http://patches.dpdk.org/series/4981/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54688/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54688/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8AE071C502;\n\tTue, 11 Jun 2019 17:54:52 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 1831A1C4D2\n\tfor <dev@dpdk.org>; Tue, 11 Jun 2019 17:54:13 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Jun 2019 08:54:13 -0700", "from lrong-srv-03.sh.intel.com ([10.67.119.177])\n\tby orsmga001.jf.intel.com with ESMTP; 11 Jun 2019 08:54:12 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "qi.z.zhang@intel.com", "Cc": "dev@dpdk.org, Leyi Rong <leyi.rong@intel.com>,\n\tAnirudh Venkataramanan <anirudh.venkataramanan@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Tue, 11 Jun 2019 23:51:44 +0800", "Message-Id": "<20190611155221.2703-30-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190611155221.2703-1-leyi.rong@intel.com>", "References": "<20190604054248.68510-1-leyi.rong@intel.com>\n\t<20190611155221.2703-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 29/66] net/ice/base: call out dev/func caps\n\twhen printing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch makes a change to add a \"func cap\" prefix when printing\nfunction capabilities, and a \"dev cap\" prefix when printing device\ncapabilities.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 75 ++++++++++++++++++-------------\n 1 file changed, 45 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex b4a9172b9..6e5a60a38 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -1948,6 +1948,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \tstruct ice_hw_func_caps *func_p = NULL;\n \tstruct ice_hw_dev_caps *dev_p = NULL;\n \tstruct ice_hw_common_caps *caps;\n+\tchar const *prefix;\n \tu32 i;\n \n \tif (!buf)\n@@ -1958,9 +1959,11 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \tif (opc == ice_aqc_opc_list_dev_caps) {\n \t\tdev_p = &hw->dev_caps;\n \t\tcaps = &dev_p->common_cap;\n+\t\tprefix = \"dev cap\";\n \t} else if (opc == ice_aqc_opc_list_func_caps) {\n \t\tfunc_p = &hw->func_caps;\n \t\tcaps = &func_p->common_cap;\n+\t\tprefix = \"func cap\";\n \t} else {\n \t\tice_debug(hw, ICE_DBG_INIT, \"wrong opcode\\n\");\n \t\treturn;\n@@ -1976,21 +1979,25 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n \t\t\tcaps->valid_functions = number;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Valid Functions = %d\\n\",\n+\t\t\t\t \"%s: valid functions = %d\\n\", prefix,\n \t\t\t\t caps->valid_functions);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_VSI:\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW caps: Dev.VSI cnt = %d\\n\",\n+\t\t\t\t\t \"%s: num VSI alloc to host = %d\\n\",\n+\t\t\t\t\t prefix,\n \t\t\t\t\t dev_p->num_vsi_allocd_to_host);\n \t\t\t} else if (func_p) {\n \t\t\t\tfunc_p->guar_num_vsi =\n \t\t\t\t\tice_get_num_per_func(hw, ICE_MAX_VSI);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW caps: Func.VSI cnt = %d\\n\",\n-\t\t\t\t\t number);\n+\t\t\t\t\t \"%s: num guaranteed VSI (fw) = %d\\n\",\n+\t\t\t\t\t prefix, number);\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"%s: num guaranteed VSI = %d\\n\",\n+\t\t\t\t\t prefix, func_p->guar_num_vsi);\n \t\t\t}\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_DCB:\n@@ -1998,49 +2005,51 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tcaps->active_tc_bitmap = logical_id;\n \t\t\tcaps->maxtc = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: DCB = %d\\n\", caps->dcb);\n+\t\t\t\t \"%s: DCB = %d\\n\", prefix, caps->dcb);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Active TC bitmap = %d\\n\",\n+\t\t\t\t \"%s: active TC bitmap = %d\\n\", prefix,\n \t\t\t\t caps->active_tc_bitmap);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: TC Max = %d\\n\", caps->maxtc);\n+\t\t\t\t \"%s: TC max = %d\\n\", prefix, caps->maxtc);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RSS:\n \t\t\tcaps->rss_table_size = number;\n \t\t\tcaps->rss_table_entry_width = logical_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: RSS table size = %d\\n\",\n+\t\t\t\t \"%s: RSS table size = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_size);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: RSS table width = %d\\n\",\n+\t\t\t\t \"%s: RSS table width = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_entry_width);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RXQS:\n \t\t\tcaps->num_rxq = number;\n \t\t\tcaps->rxq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Num Rx Qs = %d\\n\", caps->num_rxq);\n+\t\t\t\t \"%s: num Rx queues = %d\\n\", prefix,\n+\t\t\t\t caps->num_rxq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Rx first queue ID = %d\\n\",\n+\t\t\t\t \"%s: Rx first queue ID = %d\\n\", prefix,\n \t\t\t\t caps->rxq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_TXQS:\n \t\t\tcaps->num_txq = number;\n \t\t\tcaps->txq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Num Tx Qs = %d\\n\", caps->num_txq);\n+\t\t\t\t \"%s: num Tx queues = %d\\n\", prefix,\n+\t\t\t\t caps->num_txq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Tx first queue ID = %d\\n\",\n+\t\t\t\t \"%s: Tx first queue ID = %d\\n\", prefix,\n \t\t\t\t caps->txq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_MSIX:\n \t\t\tcaps->num_msix_vectors = number;\n \t\t\tcaps->msix_vector_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: MSIX vector count = %d\\n\",\n+\t\t\t\t \"%s: MSIX vector count = %d\\n\", prefix,\n \t\t\t\t caps->num_msix_vectors);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: MSIX first vector index = %d\\n\",\n+\t\t\t\t \"%s: MSIX first vector index = %d\\n\", prefix,\n \t\t\t\t caps->msix_vector_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_FD:\n@@ -2050,7 +2059,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_flow_director_fltr = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW caps: Dev.fd_fltr =%d\\n\",\n+\t\t\t\t\t \"%s: num FD filters = %d\\n\", prefix,\n \t\t\t\t\t dev_p->num_flow_director_fltr);\n \t\t\t}\n \t\t\tif (func_p) {\n@@ -2063,32 +2072,38 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\t\t GLQF_FD_SIZE_FD_BSIZE_S;\n \t\t\t\tfunc_p->fd_fltr_best_effort = val;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW:func.fd_fltr guar= %d\\n\",\n-\t\t\t\t\t func_p->fd_fltr_guar);\n+\t\t\t\t\t \"%s: num guaranteed FD filters = %d\\n\",\n+\t\t\t\t\t prefix, func_p->fd_fltr_guar);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW:func.fd_fltr best effort=%d\\n\",\n-\t\t\t\t\t func_p->fd_fltr_best_effort);\n+\t\t\t\t\t \"%s: num best effort FD filters = %d\\n\",\n+\t\t\t\t\t prefix, func_p->fd_fltr_best_effort);\n \t\t\t}\n \t\t\tbreak;\n \t\t}\n \t\tcase ICE_AQC_CAPS_MAX_MTU:\n \t\t\tcaps->max_mtu = number;\n-\t\t\tif (dev_p)\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW caps: Dev.MaxMTU = %d\\n\",\n-\t\t\t\t\t caps->max_mtu);\n-\t\t\telse if (func_p)\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"HW caps: func.MaxMTU = %d\\n\",\n-\t\t\t\t\t caps->max_mtu);\n+\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max MTU = %d\\n\",\n+\t\t\t\t prefix, caps->max_mtu);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"HW caps: Unknown capability[%d]: 0x%x\\n\", i,\n-\t\t\t\t cap);\n+\t\t\t\t \"%s: unknown capability[%d]: 0x%x\\n\", prefix,\n+\t\t\t\t i, cap);\n \t\t\tbreak;\n \t\t}\n \t}\n+\n+\t/* Re-calculate capabilities that are dependent on the number of\n+\t * physical ports; i.e. some features are not supported or function\n+\t * differently on devices with more than 4 ports.\n+\t */\n+\tif (caps && (ice_hweight32(caps->valid_functions) > 4)) {\n+\t\t/* Max 4 TCs per port */\n+\t\tcaps->maxtc = 4;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: TC max = %d (based on #ports)\\n\", prefix,\n+\t\t\t caps->maxtc);\n+\t}\n }\n \n /**\n", "prefixes": [ "v2", "29/66" ] }