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GET /api/patches/54675/?format=api
{ "id": 54675, "url": "http://patches.dpdk.org/api/patches/54675/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-19-leyi.rong@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190611155221.2703-19-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190611155221.2703-19-leyi.rong@intel.com", "date": "2019-06-11T15:51:33", "name": "[v2,18/66] net/ice/base: use macro instead of magic 8", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0dbfc5933a0f246c84ed949009cee8ee999522fb", "submitter": { "id": 1204, "url": "http://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-19-leyi.rong@intel.com/mbox/", "series": [ { "id": 4981, "url": "http://patches.dpdk.org/api/series/4981/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4981", "date": "2019-06-11T15:51:15", "name": "shared code update", "version": 2, "mbox": "http://patches.dpdk.org/series/4981/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54675/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 276731C503;\n\tTue, 11 Jun 2019 17:54:26 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id C7D951C48E\n\tfor <dev@dpdk.org>; Tue, 11 Jun 2019 17:54:00 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Jun 2019 08:54:00 -0700", "from lrong-srv-03.sh.intel.com ([10.67.119.177])\n\tby orsmga001.jf.intel.com with ESMTP; 11 Jun 2019 08:53:59 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "qi.z.zhang@intel.com", "Cc": "dev@dpdk.org, Leyi Rong <leyi.rong@intel.com>,\n\tBruce Allan <bruce.w.allan@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Tue, 11 Jun 2019 23:51:33 +0800", "Message-Id": "<20190611155221.2703-19-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190611155221.2703-1-leyi.rong@intel.com>", "References": "<20190604054248.68510-1-leyi.rong@intel.com>\n\t<20190611155221.2703-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 18/66] net/ice/base: use macro instead of\n\tmagic 8", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Replace the use of the magic number 8 by BITS_PER_BYTE when calculating\nthe number of bits from the number of bytes.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 4 +-\n drivers/net/ice/base/ice_flow.c | 74 +++++++++++++++-------------\n 2 files changed, 43 insertions(+), 35 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 5faee6d52..b569b91a7 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -3862,7 +3862,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es)\n \n \t\t\tidx = (j * 4) + k;\n \t\t\tif (used[idx])\n-\t\t\t\traw_entry |= used[idx] << (k * 8);\n+\t\t\t\traw_entry |= used[idx] << (k * BITS_PER_BYTE);\n \t\t}\n \n \t\t/* write the appropriate register set, based on HW block */\n@@ -3955,7 +3955,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\t\t\tu16 ptype;\n \t\t\t\tu8 m;\n \n-\t\t\t\tptype = byte * 8 + bit;\n+\t\t\t\tptype = byte * BITS_PER_BYTE + bit;\n \t\t\t\tif (ptype < ICE_FLOW_PTYPE_MAX) {\n \t\t\t\t\tprof->ptype[prof->ptype_count] = ptype;\n \ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex dccd7d3c7..9f2a794bc 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -26,8 +26,8 @@\n * protocol headers. Displacement values are expressed in number of bits.\n */\n #define ICE_FLOW_FLD_IPV6_TTL_DSCP_DISP\t(-4)\n-#define ICE_FLOW_FLD_IPV6_TTL_PROT_DISP\t((-2) * 8)\n-#define ICE_FLOW_FLD_IPV6_TTL_TTL_DISP\t((-1) * 8)\n+#define ICE_FLOW_FLD_IPV6_TTL_PROT_DISP\t((-2) * BITS_PER_BYTE)\n+#define ICE_FLOW_FLD_IPV6_TTL_TTL_DISP\t((-1) * BITS_PER_BYTE)\n \n /* Describe properties of a protocol header field */\n struct ice_flow_field_info {\n@@ -36,70 +36,76 @@ struct ice_flow_field_info {\n \tu16 size;\t/* Size of fields in bits */\n };\n \n+#define ICE_FLOW_FLD_INFO(_hdr, _offset_bytes, _size_bytes) { \\\n+\t.hdr = _hdr, \\\n+\t.off = _offset_bytes * BITS_PER_BYTE, \\\n+\t.size = _size_bytes * BITS_PER_BYTE, \\\n+}\n+\n /* Table containing properties of supported protocol header fields */\n static const\n struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {\n \t/* Ether */\n \t/* ICE_FLOW_FIELD_IDX_ETH_DA */\n-\t{ ICE_FLOW_SEG_HDR_ETH, 0, ETH_ALEN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ETH, 0, ETH_ALEN),\n \t/* ICE_FLOW_FIELD_IDX_ETH_SA */\n-\t{ ICE_FLOW_SEG_HDR_ETH, ETH_ALEN * 8, ETH_ALEN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ETH, ETH_ALEN, ETH_ALEN),\n \t/* ICE_FLOW_FIELD_IDX_S_VLAN */\n-\t{ ICE_FLOW_SEG_HDR_VLAN, 12 * 8, ICE_FLOW_FLD_SZ_VLAN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VLAN, 12, ICE_FLOW_FLD_SZ_VLAN),\n \t/* ICE_FLOW_FIELD_IDX_C_VLAN */\n-\t{ ICE_FLOW_SEG_HDR_VLAN, 14 * 8, ICE_FLOW_FLD_SZ_VLAN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VLAN, 14, ICE_FLOW_FLD_SZ_VLAN),\n \t/* ICE_FLOW_FIELD_IDX_ETH_TYPE */\n-\t{ ICE_FLOW_SEG_HDR_ETH, 12 * 8, ICE_FLOW_FLD_SZ_ETH_TYPE * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ETH, 12, ICE_FLOW_FLD_SZ_ETH_TYPE),\n \t/* IPv4 */\n \t/* ICE_FLOW_FIELD_IDX_IP_DSCP */\n-\t{ ICE_FLOW_SEG_HDR_IPV4, 1 * 8, 1 * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 1, 1),\n \t/* ICE_FLOW_FIELD_IDX_IP_TTL */\n-\t{ ICE_FLOW_SEG_HDR_NONE, 8 * 8, 1 * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 8, 1),\n \t/* ICE_FLOW_FIELD_IDX_IP_PROT */\n-\t{ ICE_FLOW_SEG_HDR_NONE, 9 * 8, ICE_FLOW_FLD_SZ_IP_PROT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 9, ICE_FLOW_FLD_SZ_IP_PROT),\n \t/* ICE_FLOW_FIELD_IDX_IPV4_SA */\n-\t{ ICE_FLOW_SEG_HDR_IPV4, 12 * 8, ICE_FLOW_FLD_SZ_IPV4_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 12, ICE_FLOW_FLD_SZ_IPV4_ADDR),\n \t/* ICE_FLOW_FIELD_IDX_IPV4_DA */\n-\t{ ICE_FLOW_SEG_HDR_IPV4, 16 * 8, ICE_FLOW_FLD_SZ_IPV4_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 16, ICE_FLOW_FLD_SZ_IPV4_ADDR),\n \t/* IPv6 */\n \t/* ICE_FLOW_FIELD_IDX_IPV6_SA */\n-\t{ ICE_FLOW_SEG_HDR_IPV6, 8 * 8, ICE_FLOW_FLD_SZ_IPV6_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_ADDR),\n \t/* ICE_FLOW_FIELD_IDX_IPV6_DA */\n-\t{ ICE_FLOW_SEG_HDR_IPV6, 24 * 8, ICE_FLOW_FLD_SZ_IPV6_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 24, ICE_FLOW_FLD_SZ_IPV6_ADDR),\n \t/* Transport */\n \t/* ICE_FLOW_FIELD_IDX_TCP_SRC_PORT */\n-\t{ ICE_FLOW_SEG_HDR_TCP, 0 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 0, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_TCP_DST_PORT */\n-\t{ ICE_FLOW_SEG_HDR_TCP, 2 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 2, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_UDP_SRC_PORT */\n-\t{ ICE_FLOW_SEG_HDR_UDP, 0 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 0, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_UDP_DST_PORT */\n-\t{ ICE_FLOW_SEG_HDR_UDP, 2 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP, 2, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT */\n-\t{ ICE_FLOW_SEG_HDR_SCTP, 0 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 0, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_SCTP_DST_PORT */\n-\t{ ICE_FLOW_SEG_HDR_SCTP, 2 * 8, ICE_FLOW_FLD_SZ_PORT * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_SCTP, 2, ICE_FLOW_FLD_SZ_PORT),\n \t/* ICE_FLOW_FIELD_IDX_TCP_FLAGS */\n-\t{ ICE_FLOW_SEG_HDR_TCP, 13 * 8, ICE_FLOW_FLD_SZ_TCP_FLAGS * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_TCP, 13, ICE_FLOW_FLD_SZ_TCP_FLAGS),\n \t/* ARP */\n \t/* ICE_FLOW_FIELD_IDX_ARP_SIP */\n-\t{ ICE_FLOW_SEG_HDR_ARP, 14 * 8, ICE_FLOW_FLD_SZ_IPV4_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 14, ICE_FLOW_FLD_SZ_IPV4_ADDR),\n \t/* ICE_FLOW_FIELD_IDX_ARP_DIP */\n-\t{ ICE_FLOW_SEG_HDR_ARP, 24 * 8, ICE_FLOW_FLD_SZ_IPV4_ADDR * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 24, ICE_FLOW_FLD_SZ_IPV4_ADDR),\n \t/* ICE_FLOW_FIELD_IDX_ARP_SHA */\n-\t{ ICE_FLOW_SEG_HDR_ARP, 8 * 8, ETH_ALEN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 8, ETH_ALEN),\n \t/* ICE_FLOW_FIELD_IDX_ARP_DHA */\n-\t{ ICE_FLOW_SEG_HDR_ARP, 18 * 8, ETH_ALEN * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 18, ETH_ALEN),\n \t/* ICE_FLOW_FIELD_IDX_ARP_OP */\n-\t{ ICE_FLOW_SEG_HDR_ARP, 6 * 8, ICE_FLOW_FLD_SZ_ARP_OPER * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ARP, 6, ICE_FLOW_FLD_SZ_ARP_OPER),\n \t/* ICMP */\n \t/* ICE_FLOW_FIELD_IDX_ICMP_TYPE */\n-\t{ ICE_FLOW_SEG_HDR_ICMP, 0 * 8, ICE_FLOW_FLD_SZ_ICMP_TYPE * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ICMP, 0, ICE_FLOW_FLD_SZ_ICMP_TYPE),\n \t/* ICE_FLOW_FIELD_IDX_ICMP_CODE */\n-\t{ ICE_FLOW_SEG_HDR_ICMP, 1 * 8, ICE_FLOW_FLD_SZ_ICMP_CODE * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ICMP, 1, ICE_FLOW_FLD_SZ_ICMP_CODE),\n \t/* GRE */\n \t/* ICE_FLOW_FIELD_IDX_GRE_KEYID */\n-\t{ ICE_FLOW_SEG_HDR_GRE, 12 * 8, ICE_FLOW_FLD_SZ_GRE_KEYID * 8 },\n+\tICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GRE, 12, ICE_FLOW_FLD_SZ_GRE_KEYID),\n };\n \n /* Bitmaps indicating relevant packet types for a particular protocol header\n@@ -644,7 +650,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t/* Each extraction sequence entry is a word in size, and extracts a\n \t * word-aligned offset from a protocol header.\n \t */\n-\tese_bits = ICE_FLOW_FV_EXTRACT_SZ * 8;\n+\tese_bits = ICE_FLOW_FV_EXTRACT_SZ * BITS_PER_BYTE;\n \n \tflds[fld].xtrct.prot_id = prot_id;\n \tflds[fld].xtrct.off = (ice_flds_info[fld].off / ese_bits) *\n@@ -737,15 +743,17 @@ ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t\traw->info.xtrct.prot_id = ICE_PROT_PAY;\n \t\traw->info.xtrct.off = (off / ICE_FLOW_FV_EXTRACT_SZ) *\n \t\t\tICE_FLOW_FV_EXTRACT_SZ;\n-\t\traw->info.xtrct.disp = (off % ICE_FLOW_FV_EXTRACT_SZ) * 8;\n+\t\traw->info.xtrct.disp = (off % ICE_FLOW_FV_EXTRACT_SZ) *\n+\t\t\tBITS_PER_BYTE;\n \t\traw->info.xtrct.idx = params->es_cnt;\n \n \t\t/* Determine the number of field vector entries this raw field\n \t\t * consumes.\n \t\t */\n \t\tcnt = DIVIDE_AND_ROUND_UP(raw->info.xtrct.disp +\n-\t\t\t\t\t (raw->info.src.last * 8),\n-\t\t\t\t\t ICE_FLOW_FV_EXTRACT_SZ * 8);\n+\t\t\t\t\t (raw->info.src.last * BITS_PER_BYTE),\n+\t\t\t\t\t (ICE_FLOW_FV_EXTRACT_SZ *\n+\t\t\t\t\t BITS_PER_BYTE));\n \t\toff = raw->info.xtrct.off;\n \t\tfor (j = 0; j < cnt; j++) {\n \t\t\t/* Make sure the number of extraction sequence required\n", "prefixes": [ "v2", "18/66" ] }