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Update a patch.

GET /api/patches/54671/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54671,
    "url": "http://patches.dpdk.org/api/patches/54671/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-15-leyi.rong@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190611155221.2703-15-leyi.rong@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190611155221.2703-15-leyi.rong@intel.com",
    "date": "2019-06-11T15:51:29",
    "name": "[v2,14/66] net/ice/base: cache the data of set PHY cfg AQ in SW",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "9f5ceb7af729e8984cecddafaf009f8e704cc7e0",
    "submitter": {
        "id": 1204,
        "url": "http://patches.dpdk.org/api/people/1204/?format=api",
        "name": "Leyi Rong",
        "email": "leyi.rong@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190611155221.2703-15-leyi.rong@intel.com/mbox/",
    "series": [
        {
            "id": 4981,
            "url": "http://patches.dpdk.org/api/series/4981/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4981",
            "date": "2019-06-11T15:51:15",
            "name": "shared code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/4981/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54671/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54671/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 19BDB1C4D6;\n\tTue, 11 Jun 2019 17:54:15 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id F3E491C471\n\tfor <dev@dpdk.org>; Tue, 11 Jun 2019 17:53:55 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Jun 2019 08:53:55 -0700",
            "from lrong-srv-03.sh.intel.com ([10.67.119.177])\n\tby orsmga001.jf.intel.com with ESMTP; 11 Jun 2019 08:53:54 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Leyi Rong <leyi.rong@intel.com>",
        "To": "qi.z.zhang@intel.com",
        "Cc": "dev@dpdk.org, Leyi Rong <leyi.rong@intel.com>,\n\tChinh T Cao <chinh.t.cao@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Tue, 11 Jun 2019 23:51:29 +0800",
        "Message-Id": "<20190611155221.2703-15-leyi.rong@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20190611155221.2703-1-leyi.rong@intel.com>",
        "References": "<20190604054248.68510-1-leyi.rong@intel.com>\n\t<20190611155221.2703-1-leyi.rong@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 14/66] net/ice/base: cache the data of set PHY\n\tcfg AQ in SW",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "After the transition from cable-unplug to cable-plug events, FW will\nclear the set-phy-cfg data, sent by user. Thus, we will need to\ncache these info.\n1. The submitted data when set-phy-cfg is called. This info will be used\nlater to check if FW clears out the PHY info, requested by user.\n2. The FC, FEC and LinkSpeed, requested by user. This info will be used\nlater, by device driver, to construct the new input data for the\nset-phy-cfg AQ command.\n\nSigned-off-by: Chinh T Cao <chinh.t.cao@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 119 +++++++++++++++++++++++-------\n drivers/net/ice/base/ice_common.h |   2 +-\n drivers/net/ice/base/ice_type.h   |  31 ++++++--\n drivers/net/ice/ice_ethdev.c      |   2 +-\n 4 files changed, 122 insertions(+), 32 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 09296ead2..a0ab25aef 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -270,21 +270,23 @@ enum ice_status\n ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t\t     struct ice_link_status *link, struct ice_sq_cd *cd)\n {\n-\tstruct ice_link_status *hw_link_info_old, *hw_link_info;\n \tstruct ice_aqc_get_link_status_data link_data = { 0 };\n \tstruct ice_aqc_get_link_status *resp;\n+\tstruct ice_link_status *li_old, *li;\n \tenum ice_media_type *hw_media_type;\n \tstruct ice_fc_info *hw_fc_info;\n \tbool tx_pause, rx_pause;\n \tstruct ice_aq_desc desc;\n \tenum ice_status status;\n+\tstruct ice_hw *hw;\n \tu16 cmd_flags;\n \n \tif (!pi)\n \t\treturn ICE_ERR_PARAM;\n-\thw_link_info_old = &pi->phy.link_info_old;\n+\thw = pi->hw;\n+\tli_old = &pi->phy.link_info_old;\n \thw_media_type = &pi->phy.media_type;\n-\thw_link_info = &pi->phy.link_info;\n+\tli = &pi->phy.link_info;\n \thw_fc_info = &pi->fc;\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);\n@@ -293,27 +295,27 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \tresp->cmd_flags = CPU_TO_LE16(cmd_flags);\n \tresp->lport_num = pi->lport;\n \n-\tstatus = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),\n-\t\t\t\t cd);\n+\tstatus = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);\n \n \tif (status != ICE_SUCCESS)\n \t\treturn status;\n \n \t/* save off old link status information */\n-\t*hw_link_info_old = *hw_link_info;\n+\t*li_old = *li;\n \n \t/* update current link status information */\n-\thw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);\n-\thw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);\n-\thw_link_info->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);\n+\tli->link_speed = LE16_TO_CPU(link_data.link_speed);\n+\tli->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);\n+\tli->phy_type_high = LE64_TO_CPU(link_data.phy_type_high);\n \t*hw_media_type = ice_get_media_type(pi);\n-\thw_link_info->link_info = link_data.link_info;\n-\thw_link_info->an_info = link_data.an_info;\n-\thw_link_info->ext_info = link_data.ext_info;\n-\thw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);\n-\thw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;\n-\thw_link_info->topo_media_conflict = link_data.topo_media_conflict;\n-\thw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;\n+\tli->link_info = link_data.link_info;\n+\tli->an_info = link_data.an_info;\n+\tli->ext_info = link_data.ext_info;\n+\tli->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);\n+\tli->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;\n+\tli->topo_media_conflict = link_data.topo_media_conflict;\n+\tli->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |\n+\t\t\t\t      ICE_AQ_CFG_PACING_TYPE_M);\n \n \t/* update fc info */\n \ttx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);\n@@ -327,13 +329,24 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \telse\n \t\thw_fc_info->current_mode = ICE_FC_NONE;\n \n-\thw_link_info->lse_ena =\n-\t\t!!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));\n-\n+\tli->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));\n+\n+\tice_debug(hw, ICE_DBG_LINK, \"link_speed = 0x%x\\n\", li->link_speed);\n+\tice_debug(hw, ICE_DBG_LINK, \"phy_type_low = 0x%llx\\n\",\n+\t\t  (unsigned long long)li->phy_type_low);\n+\tice_debug(hw, ICE_DBG_LINK, \"phy_type_high = 0x%llx\\n\",\n+\t\t  (unsigned long long)li->phy_type_high);\n+\tice_debug(hw, ICE_DBG_LINK, \"media_type = 0x%x\\n\", *hw_media_type);\n+\tice_debug(hw, ICE_DBG_LINK, \"link_info = 0x%x\\n\", li->link_info);\n+\tice_debug(hw, ICE_DBG_LINK, \"an_info = 0x%x\\n\", li->an_info);\n+\tice_debug(hw, ICE_DBG_LINK, \"ext_info = 0x%x\\n\", li->ext_info);\n+\tice_debug(hw, ICE_DBG_LINK, \"lse_ena = 0x%x\\n\", li->lse_ena);\n+\tice_debug(hw, ICE_DBG_LINK, \"max_frame = 0x%x\\n\", li->max_frame_size);\n+\tice_debug(hw, ICE_DBG_LINK, \"pacing = 0x%x\\n\", li->pacing);\n \n \t/* save link status information */\n \tif (link)\n-\t\t*link = *hw_link_info;\n+\t\t*link = *li;\n \n \t/* flag cleared so calling functions don't call AQ again */\n \tpi->phy.get_link_info = false;\n@@ -2412,7 +2425,7 @@ ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n /**\n  * ice_aq_set_phy_cfg\n  * @hw: pointer to the HW struct\n- * @lport: logical port number\n+ * @pi: port info structure of the interested logical port\n  * @cfg: structure with PHY configuration data to be set\n  * @cd: pointer to command details structure or NULL\n  *\n@@ -2422,10 +2435,11 @@ ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,\n  * parameters. This status will be indicated by the command response (0x0601).\n  */\n enum ice_status\n-ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,\n \t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)\n {\n \tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n \n \tif (!cfg)\n \t\treturn ICE_ERR_PARAM;\n@@ -2440,10 +2454,26 @@ ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n \t}\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);\n-\tdesc.params.set_phy.lport_num = lport;\n+\tdesc.params.set_phy.lport_num = pi->lport;\n \tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n \n-\treturn ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);\n+\tice_debug(hw, ICE_DBG_LINK, \"phy_type_low = 0x%llx\\n\",\n+\t\t  (unsigned long long)LE64_TO_CPU(cfg->phy_type_low));\n+\tice_debug(hw, ICE_DBG_LINK, \"phy_type_high = 0x%llx\\n\",\n+\t\t  (unsigned long long)LE64_TO_CPU(cfg->phy_type_high));\n+\tice_debug(hw, ICE_DBG_LINK, \"caps = 0x%x\\n\", cfg->caps);\n+\tice_debug(hw, ICE_DBG_LINK, \"low_power_ctrl = 0x%x\\n\",\n+\t\t  cfg->low_power_ctrl);\n+\tice_debug(hw, ICE_DBG_LINK, \"eee_cap = 0x%x\\n\", cfg->eee_cap);\n+\tice_debug(hw, ICE_DBG_LINK, \"eeer_value = 0x%x\\n\", cfg->eeer_value);\n+\tice_debug(hw, ICE_DBG_LINK, \"link_fec_opt = 0x%x\\n\", cfg->link_fec_opt);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);\n+\n+\tif (!status)\n+\t\tpi->phy.curr_user_phy_cfg = *cfg;\n+\n+\treturn status;\n }\n \n /**\n@@ -2487,6 +2517,38 @@ enum ice_status ice_update_link_info(struct ice_port_info *pi)\n \treturn status;\n }\n \n+/**\n+ * ice_cache_phy_user_req\n+ * @pi: port information structure\n+ * @cache_data: PHY logging data\n+ * @cache_mode: PHY logging mode\n+ *\n+ * Log the user request on (FC, FEC, SPEED) for later user.\n+ */\n+static void\n+ice_cache_phy_user_req(struct ice_port_info *pi,\n+\t\t       struct ice_phy_cache_mode_data cache_data,\n+\t\t       enum ice_phy_cache_mode cache_mode)\n+{\n+\tif (!pi)\n+\t\treturn;\n+\n+\tswitch (cache_mode) {\n+\tcase ICE_FC_MODE:\n+\t\tpi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;\n+\t\tbreak;\n+\tcase ICE_SPEED_MODE:\n+\t\tpi->phy.curr_user_speed_req =\n+\t\t\tcache_data.data.curr_user_speed_req;\n+\t\tbreak;\n+\tcase ICE_FEC_MODE:\n+\t\tpi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n /**\n  * ice_set_fc\n  * @pi: port information structure\n@@ -2499,6 +2561,7 @@ enum ice_status\n ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n {\n \tstruct ice_aqc_set_phy_cfg_data cfg = { 0 };\n+\tstruct ice_phy_cache_mode_data cache_data;\n \tstruct ice_aqc_get_phy_caps_data *pcaps;\n \tenum ice_status status;\n \tu8 pause_mask = 0x0;\n@@ -2509,6 +2572,10 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \thw = pi->hw;\n \t*aq_failures = ICE_SET_FC_AQ_FAIL_NONE;\n \n+\t/* Cache user FC request */\n+\tcache_data.data.curr_user_fc_req = pi->fc.req_mode;\n+\tice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);\n+\n \tswitch (pi->fc.req_mode) {\n \tcase ICE_FC_FULL:\n \t\tpause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;\n@@ -2540,8 +2607,10 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \t/* clear the old pause settings */\n \tcfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |\n \t\t\t\t   ICE_AQC_PHY_EN_RX_LINK_PAUSE);\n+\n \t/* set the new capabilities */\n \tcfg.caps |= pause_mask;\n+\n \t/* If the capabilities have changed, then set the new config */\n \tif (cfg.caps != pcaps->caps) {\n \t\tint retry_count, retry_max = 10;\n@@ -2557,7 +2626,7 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n \t\tcfg.eeer_value = pcaps->eeer_value;\n \t\tcfg.link_fec_opt = pcaps->link_fec_options;\n \n-\t\tstatus = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);\n+\t\tstatus = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);\n \t\tif (status) {\n \t\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_SET;\n \t\t\tgoto out;\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex aee754b85..cccb5f009 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -134,7 +134,7 @@ ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n \n enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n enum ice_status\n-ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,\n \t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);\n enum ice_status\n ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 45b0b3c05..5da267f1b 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -148,6 +148,12 @@ enum ice_fc_mode {\n \tICE_FC_DFLT\n };\n \n+enum ice_phy_cache_mode {\n+\tICE_FC_MODE = 0,\n+\tICE_SPEED_MODE,\n+\tICE_FEC_MODE\n+};\n+\n enum ice_fec_mode {\n \tICE_FEC_NONE = 0,\n \tICE_FEC_RS,\n@@ -155,6 +161,14 @@ enum ice_fec_mode {\n \tICE_FEC_AUTO\n };\n \n+struct ice_phy_cache_mode_data {\n+\tunion {\n+\t\tenum ice_fec_mode curr_user_fec_req;\n+\t\tenum ice_fc_mode curr_user_fc_req;\n+\t\tu16 curr_user_speed_req;\n+\t} data;\n+};\n+\n enum ice_set_fc_aq_failures {\n \tICE_SET_FC_AQ_FAIL_NONE = 0,\n \tICE_SET_FC_AQ_FAIL_GET,\n@@ -232,6 +246,13 @@ struct ice_phy_info {\n \tu64 phy_type_high;\n \tenum ice_media_type media_type;\n \tu8 get_link_info;\n+\t/* Please refer to struct ice_aqc_get_link_status_data to get\n+\t * detail of enable bit in curr_user_speed_req\n+\t */\n+\tu16 curr_user_speed_req;\n+\tenum ice_fec_mode curr_user_fec_req;\n+\tenum ice_fc_mode curr_user_fc_req;\n+\tstruct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;\n };\n \n #define ICE_MAX_NUM_MIRROR_RULES\t64\n@@ -648,6 +669,8 @@ struct ice_port_info {\n \tu8 port_state;\n #define ICE_SCHED_PORT_STATE_INIT\t0x0\n #define ICE_SCHED_PORT_STATE_READY\t0x1\n+\tu8 lport;\n+#define ICE_LPORT_MASK\t\t\t0xff\n \tu16 dflt_tx_vsi_rule_id;\n \tu16 dflt_tx_vsi_num;\n \tu16 dflt_rx_vsi_rule_id;\n@@ -663,11 +686,9 @@ struct ice_port_info {\n \tstruct ice_dcbx_cfg remote_dcbx_cfg;\t/* Peer Cfg */\n \tstruct ice_dcbx_cfg desired_dcbx_cfg;\t/* CEE Desired Cfg */\n \t/* LLDP/DCBX Status */\n-\tu8 dcbx_status;\n-\tu8 is_sw_lldp;\n-\tu8 lport;\n-#define ICE_LPORT_MASK\t\t0xff\n-\tu8 is_vf;\n+\tu8 dcbx_status:3;\t\t/* see ICE_DCBX_STATUS_DIS */\n+\tu8 is_sw_lldp:1;\n+\tu8 is_vf:1;\n };\n \n struct ice_switch_info {\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex bdbceb411..962d506a1 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2295,7 +2295,7 @@ ice_force_phys_link_state(struct ice_hw *hw, bool link_up)\n \telse\n \t\tcfg.caps &= ~ICE_AQ_PHY_ENA_LINK;\n \n-\tstatus = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);\n+\tstatus = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);\n \n out:\n \tice_free(hw, pcaps);\n",
    "prefixes": [
        "v2",
        "14/66"
    ]
}