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GET /api/patches/54609/?format=api
{ "id": 54609, "url": "http://patches.dpdk.org/api/patches/54609/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1560152324-20538-10-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1560152324-20538-10-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1560152324-20538-10-git-send-email-arybchenko@solarflare.com", "date": "2019-06-10T07:38:24", "name": "[09/29] net/sfc/base: add NVRAM info to API", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b2651d545575a74dc7664d0bf56d3b49f0bc2a11", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1560152324-20538-10-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 4965, "url": "http://patches.dpdk.org/api/series/4965/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4965", "date": "2019-06-10T07:38:19", "name": "net/sfc/base: update base driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4965/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54609/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54609/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DBCFB1BF45;\n\tMon, 10 Jun 2019 09:39:40 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 26B6B1BE8D\n\tfor <dev@dpdk.org>; Mon, 10 Jun 2019 09:38:59 +0200 (CEST)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n\t32374140058\n\tfor <dev@dpdk.org>; Mon, 10 Jun 2019 07:38:58 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Mon, 10 Jun 2019 00:38:51 -0700", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Mon, 10 Jun 2019 00:38:50 -0700", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tx5A7cnmh008780; Mon, 10 Jun 2019 08:38:49 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\t63E171627D7; Mon, 10 Jun 2019 08:38:49 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Richard Houldsworth <rhouldsworth@solarflare.com>", "Date": "Mon, 10 Jun 2019 08:38:24 +0100", "Message-ID": "<1560152324-20538-10-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1560152324-20538-1-git-send-email-arybchenko@solarflare.com>", "References": "<1560152324-20538-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24664.003", "X-TM-AS-Result": "No-5.850700-4.000000-10", "X-TMASE-MatchedRID": "gPHG3QhDFSZSQAJO4/Vvl3YZxYoZm58FEwOwAhdI3QO3ltgdOztD8KEG\n\tKhm9baaNzgG6q5uVl29TvVffeIwvQ8HVNeDWrWSGB8Lglj0iCAA/pOSL72dTfwdkFovAReUoLPJ\n\ttWpbJjY16sTzJDZX20UymwL6ADf586sEU5+BT/F0Pe5gzF3TVt6uVOrDvB8LTNN1jIkOk1JfJUF\n\tbx9STukyO7mPP5e5uv/xrkZhZF1M978ZKYQ4N2coicBKfMHlV8fS0Ip2eEHnz3IzXlXlpamPoLR\n\t4+zsDTtifGCYEa4FxeD1xXyFt3U8nYs5m2o/yWSHCDzB3jb03kIbWuRtkzLyw==", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--5.850700-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24664.003", "X-MDID": "1560152338-pg6j-67F73fR", "Subject": "[dpdk-dev] [PATCH 09/29] net/sfc/base: add NVRAM info to API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Richard Houldsworth <rhouldsworth@solarflare.com>\n\nAdd function to query partition characteristics.\nRefactor efx_nvram_size to share implementation.\n\nSigned-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_impl.h | 6 +++++\n drivers/net/sfc/base/ef10_nvram.c | 36 +++++++++++++++++++++--------\n drivers/net/sfc/base/efx.h | 6 +++++\n drivers/net/sfc/base/efx_impl.h | 3 ++-\n drivers/net/sfc/base/efx_nvram.c | 46 +++++++++++++++++++++++++++++++++-----\n drivers/net/sfc/base/siena_impl.h | 6 +++++\n drivers/net/sfc/base/siena_nvram.c | 23 +++++++++++++++++++\n 7 files changed, 110 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h\nindex fae94fe..0cfbf59 100644\n--- a/drivers/net/sfc/base/ef10_impl.h\n+++ b/drivers/net/sfc/base/ef10_impl.h\n@@ -452,6 +452,12 @@\n \t__out\t\t\tsize_t *sizep);\n \n extern\t__checkReturn\t\tefx_rc_t\n+ef10_nvram_partn_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tuint32_t partn,\n+\t__out\t\t\tefx_nvram_info_t * enip);\n+\n+extern\t__checkReturn\t\tefx_rc_t\n ef10_nvram_partn_rw_start(\n \t__in\t\t\tefx_nic_t *enp,\n \t__in\t\t\tuint32_t partn,\ndiff --git a/drivers/net/sfc/base/ef10_nvram.c b/drivers/net/sfc/base/ef10_nvram.c\nindex 2aed421..a618c75 100644\n--- a/drivers/net/sfc/base/ef10_nvram.c\n+++ b/drivers/net/sfc/base/ef10_nvram.c\n@@ -1960,6 +1960,29 @@ static uint32_t checksum_tlv_partition(\n }\n \n \t__checkReturn\t\tefx_rc_t\n+ef10_nvram_partn_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tuint32_t partn,\n+\t__out\t\t\tefx_nvram_info_t *enip)\n+{\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)\n+\t\tgoto fail1;\n+\n+\tif (enip->eni_write_size == 0)\n+\t\tenip->eni_write_size = EF10_NVRAM_CHUNK;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\t\tefx_rc_t\n ef10_nvram_partn_lock(\n \t__in\t\t\tefx_nic_t *enp,\n \t__in\t\t\tuint32_t partn)\n@@ -2439,22 +2462,17 @@ static uint32_t checksum_tlv_partition(\n \t__in\t\t\tuint32_t partn,\n \t__out\t\t\tsize_t *chunk_sizep)\n {\n-\tuint32_t write_size = 0;\n+\tefx_nvram_info_t eni = { 0 };\n \tefx_rc_t rc;\n \n-\tif ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,\n-\t NULL, &write_size)) != 0)\n+\tif ((rc = ef10_nvram_partn_info(enp, partn, &eni)) != 0)\n \t\tgoto fail1;\n \n \tif ((rc = ef10_nvram_partn_lock(enp, partn)) != 0)\n \t\tgoto fail2;\n \n-\tif (chunk_sizep != NULL) {\n-\t\tif (write_size == 0)\n-\t\t\t*chunk_sizep = EF10_NVRAM_CHUNK;\n-\t\telse\n-\t\t\t*chunk_sizep = write_size;\n-\t}\n+\tif (chunk_sizep != NULL)\n+\t\t*chunk_sizep = eni.eni_write_size;\n \n \treturn (0);\n \ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex a5342af..4905918 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -1635,6 +1635,12 @@ enum {\n \t__out\t\t\tsize_t *sizep);\n \n extern\t__checkReturn\t\tefx_rc_t\n+efx_nvram_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tefx_nvram_type_t type,\n+\t__out\t\t\tefx_nvram_info_t *enip);\n+\n+extern\t__checkReturn\t\tefx_rc_t\n efx_nvram_rw_start(\n \t__in\t\t\tefx_nic_t *enp,\n \t__in\t\t\tefx_nvram_type_t type,\ndiff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h\nindex 684403f..577d5aa 100644\n--- a/drivers/net/sfc/base/efx_impl.h\n+++ b/drivers/net/sfc/base/efx_impl.h\n@@ -501,7 +501,8 @@\n #endif\t/* EFSYS_OPT_DIAG */\n \tefx_rc_t\t(*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,\n \t\t\t\t\t uint32_t *);\n-\tefx_rc_t\t(*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);\n+\tefx_rc_t\t(*envo_partn_info)(efx_nic_t *, uint32_t,\n+\t\t\t\t\t efx_nvram_info_t *);\n \tefx_rc_t\t(*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);\n \tefx_rc_t\t(*envo_partn_read)(efx_nic_t *, uint32_t,\n \t\t\t\t\t unsigned int, caddr_t, size_t);\ndiff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c\nindex df7e851..b817cb6 100644\n--- a/drivers/net/sfc/base/efx_nvram.c\n+++ b/drivers/net/sfc/base/efx_nvram.c\n@@ -16,7 +16,7 @@\n \tsiena_nvram_test,\t\t/* envo_test */\n #endif\t/* EFSYS_OPT_DIAG */\n \tsiena_nvram_type_to_partn,\t/* envo_type_to_partn */\n-\tsiena_nvram_partn_size,\t\t/* envo_partn_size */\n+\tsiena_nvram_partn_info,\t\t/* envo_partn_info */\n \tsiena_nvram_partn_rw_start,\t/* envo_partn_rw_start */\n \tsiena_nvram_partn_read,\t\t/* envo_partn_read */\n \tsiena_nvram_partn_read,\t\t/* envo_partn_read_backup */\n@@ -37,7 +37,7 @@\n \tef10_nvram_test,\t\t/* envo_test */\n #endif\t/* EFSYS_OPT_DIAG */\n \tef10_nvram_type_to_partn,\t/* envo_type_to_partn */\n-\tef10_nvram_partn_size,\t\t/* envo_partn_size */\n+\tef10_nvram_partn_info,\t\t/* envo_partn_info */\n \tef10_nvram_partn_rw_start,\t/* envo_partn_rw_start */\n \tef10_nvram_partn_read,\t\t/* envo_partn_read */\n \tef10_nvram_partn_read_backup,\t/* envo_partn_read_backup */\n@@ -138,6 +138,7 @@\n \t__out\t\t\tsize_t *sizep)\n {\n \tconst efx_nvram_ops_t *envop = enp->en_envop;\n+\tefx_nvram_info_t eni = { 0 };\n \tuint32_t partn;\n \tefx_rc_t rc;\n \n@@ -147,9 +148,11 @@\n \tif ((rc = envop->envo_type_to_partn(enp, type, &partn)) != 0)\n \t\tgoto fail1;\n \n-\tif ((rc = envop->envo_partn_size(enp, partn, sizep)) != 0)\n+\tif ((rc = envop->envo_partn_info(enp, partn, &eni)) != 0)\n \t\tgoto fail2;\n \n+\t*sizep = eni.eni_partn_size;\n+\n \treturn (0);\n \n fail2:\n@@ -161,6 +164,36 @@\n \treturn (rc);\n }\n \n+extern\t__checkReturn\t\tefx_rc_t\n+efx_nvram_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tefx_nvram_type_t type,\n+\t__out\t\t\tefx_nvram_info_t *enip)\n+{\n+\tconst efx_nvram_ops_t *envop = enp->en_envop;\n+\tuint32_t partn;\n+\tefx_rc_t rc;\n+\n+\tEFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);\n+\tEFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM);\n+\n+\tif ((rc = envop->envo_type_to_partn(enp, type, &partn)) != 0)\n+\t\tgoto fail1;\n+\n+\tif ((rc = envop->envo_partn_info(enp, partn, enip)) != 0)\n+\t\tgoto fail2;\n+\n+\treturn (0);\n+\n+fail2:\n+\tEFSYS_PROBE(fail2);\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n \t__checkReturn\t\tefx_rc_t\n efx_nvram_get_version(\n \t__in\t\t\tefx_nic_t *enp,\n@@ -305,7 +338,7 @@\n {\n \tconst efx_nvram_ops_t *envop = enp->en_envop;\n \tunsigned int offset = 0;\n-\tsize_t size = 0;\n+\tefx_nvram_info_t eni = { 0 };\n \tuint32_t partn;\n \tefx_rc_t rc;\n \n@@ -317,10 +350,11 @@\n \n \tEFSYS_ASSERT3U(enp->en_nvram_partn_locked, ==, partn);\n \n-\tif ((rc = envop->envo_partn_size(enp, partn, &size)) != 0)\n+\tif ((rc = envop->envo_partn_info(enp, partn, &eni)) != 0)\n \t\tgoto fail2;\n \n-\tif ((rc = envop->envo_partn_erase(enp, partn, offset, size)) != 0)\n+\tif ((rc = envop->envo_partn_erase(enp, partn, offset,\n+\t\t eni.eni_partn_size)) != 0)\n \t\tgoto fail3;\n \n \treturn (0);\ndiff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h\nindex 1adb8a4..38d0289 100644\n--- a/drivers/net/sfc/base/siena_impl.h\n+++ b/drivers/net/sfc/base/siena_impl.h\n@@ -192,6 +192,12 @@\n \t__out\t\t\tsize_t *sizep);\n \n extern\t__checkReturn\t\tefx_rc_t\n+siena_nvram_partn_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tuint32_t partn,\n+\t__out\t\t\tefx_nvram_info_t * enip);\n+\n+extern\t__checkReturn\t\tefx_rc_t\n siena_nvram_partn_rw_start(\n \t__in\t\t\tefx_nic_t *enp,\n \t__in\t\t\tuint32_t partn,\ndiff --git a/drivers/net/sfc/base/siena_nvram.c b/drivers/net/sfc/base/siena_nvram.c\nindex b8ea8a7..7d423d2 100644\n--- a/drivers/net/sfc/base/siena_nvram.c\n+++ b/drivers/net/sfc/base/siena_nvram.c\n@@ -40,6 +40,29 @@\n }\n \n \t__checkReturn\t\tefx_rc_t\n+siena_nvram_partn_info(\n+\t__in\t\t\tefx_nic_t *enp,\n+\t__in\t\t\tuint32_t partn,\n+\t__out\t\t\tefx_nvram_info_t * enip)\n+{\n+\tefx_rc_t rc;\n+\n+\tif ((rc = efx_mcdi_nvram_info_ex(enp, partn, enip)) != 0)\n+\t\tgoto fail1;\n+\n+\tif (enip->eni_write_size == 0)\n+\t\tenip->eni_write_size = SIENA_NVRAM_CHUNK;\n+\n+\treturn (0);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, efx_rc_t, rc);\n+\n+\treturn (rc);\n+}\n+\n+\n+\t__checkReturn\t\tefx_rc_t\n siena_nvram_partn_lock(\n \t__in\t\t\tefx_nic_t *enp,\n \t__in\t\t\tuint32_t partn)\n", "prefixes": [ "09/29" ] }