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{
    "id": 54473,
    "url": "http://patches.dpdk.org/api/patches/54473/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/f9536aaa82a7d3731ee7417301b19f2f9ea31515.1559818024.git.xuanziyang2@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<f9536aaa82a7d3731ee7417301b19f2f9ea31515.1559818024.git.xuanziyang2@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/f9536aaa82a7d3731ee7417301b19f2f9ea31515.1559818024.git.xuanziyang2@huawei.com",
    "date": "2019-06-06T11:07:09",
    "name": "[v4,11/11] net/hinic: add support for basic device operations",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "0f472896c3bba9000865826733ff5cc9d3f13451",
    "submitter": {
        "id": 1321,
        "url": "http://patches.dpdk.org/api/people/1321/?format=api",
        "name": "Ziyang Xuan",
        "email": "xuanziyang2@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/f9536aaa82a7d3731ee7417301b19f2f9ea31515.1559818024.git.xuanziyang2@huawei.com/mbox/",
    "series": [
        {
            "id": 4924,
            "url": "http://patches.dpdk.org/api/series/4924/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4924",
            "date": "2019-06-06T11:04:33",
            "name": "A new net PMD - hinic",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/4924/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54473/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/54473/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 51E9E1B9BB;\n\tThu,  6 Jun 2019 12:55:50 +0200 (CEST)",
            "from huawei.com (szxga06-in.huawei.com [45.249.212.32])\n\tby dpdk.org (Postfix) with ESMTP id 126301B9AE\n\tfor <dev@dpdk.org>; Thu,  6 Jun 2019 12:55:48 +0200 (CEST)",
            "from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60])\n\tby Forcepoint Email with ESMTP id 2A6D21646A477AD63E76;\n\tThu,  6 Jun 2019 18:55:46 +0800 (CST)",
            "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP\n\tServer id 14.3.439.0; Thu, 6 Jun 2019 18:55:38 +0800"
        ],
        "From": "Ziyang Xuan <xuanziyang2@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <shahar.belkar@huawei.com>,\n\t<stephen@networkplumber.org>, <luoxianjun@huawei.com>, Ziyang Xuan\n\t<xuanziyang2@huawei.com>",
        "Date": "Thu, 6 Jun 2019 19:07:09 +0800",
        "Message-ID": "<f9536aaa82a7d3731ee7417301b19f2f9ea31515.1559818024.git.xuanziyang2@huawei.com>",
        "X-Mailer": "git-send-email 2.18.0",
        "In-Reply-To": "<cover.1559818024.git.xuanziyang2@huawei.com>",
        "References": "<cover.1559818024.git.xuanziyang2@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.175.119.39]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH v4 11/11] net/hinic: add support for basic device\n\toperations",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add hinic PMD initialization and ethernet operatioins code.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/hinic_pmd_ethdev.c        | 2125 +++++++++++++++++++\n drivers/net/hinic/rte_pmd_hinic_version.map |    4 +\n 2 files changed, 2129 insertions(+)\n create mode 100644 drivers/net/hinic/rte_pmd_hinic_version.map",
    "diff": "diff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c\nindex f19e457c1..47ac96065 100644\n--- a/drivers/net/hinic/hinic_pmd_ethdev.c\n+++ b/drivers/net/hinic/hinic_pmd_ethdev.c\n@@ -14,9 +14,2134 @@\n #include <rte_errno.h>\n #include <rte_kvargs.h>\n \n+#include \"hinic_pmd_ethdev.h\"\n+#include \"hinic_pmd_tx.h\"\n+#include \"hinic_pmd_rx.h\"\n+\n+#define HINIC_MIN_RX_BUF_SIZE\t1024\n+\n+#define HINIC_MAX_MAC_ADDRS\t1\n+#define EQ_MSIX_RESEND_TIMER_CLEAR\t1\n+\n+/* Hinic PMD parameters */\n+#define ETH_HINIC_FW_VER\t\"check_fw_version\"\n+\n+static const char *const valid_params[] = {\n+\tETH_HINIC_FW_VER,\n+\tNULL};\n+\n+\n /** Driver-specific log messages type. */\n int hinic_logtype;\n \n+static int check_fw_ver = 1;\n+\n+static int hinic_dev_init(struct rte_eth_dev *eth_dev);\n+static int hinic_dev_uninit(struct rte_eth_dev *dev);\n+static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev);\n+static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev);\n+static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool *mp);\n+static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_txconf *tx_conf);\n+\n+static const struct eth_dev_ops hinic_pmd_ops = {\n+\t.dev_configure                 = hinic_dev_configure,\n+\t.dev_infos_get                 = hinic_dev_infos_get,\n+\t.rx_queue_setup                = hinic_rx_queue_setup,\n+\t.tx_queue_setup                = hinic_tx_queue_setup,\n+\t.dev_start                     = hinic_dev_start,\n+\t.link_update                   = hinic_link_update,\n+\t.rx_queue_release              = hinic_rx_queue_release,\n+\t.tx_queue_release              = hinic_tx_queue_release,\n+\t.dev_stop                      = hinic_dev_stop,\n+\t.dev_close                     = hinic_dev_close,\n+\t.promiscuous_enable            = hinic_dev_promiscuous_enable,\n+\t.promiscuous_disable           = hinic_dev_promiscuous_disable,\n+\t.rss_hash_update               = hinic_rss_hash_update,\n+\t.rss_hash_conf_get             = hinic_rss_conf_get,\n+\t.reta_update                   = hinic_rss_indirtbl_update,\n+\t.reta_query                    = hinic_rss_indirtbl_query,\n+\t.stats_get                     = hinic_dev_stats_get,\n+\t.stats_reset                   = hinic_dev_stats_reset,\n+\t.xstats_get                    = hinic_dev_xstats_get,\n+\t.xstats_reset                  = hinic_dev_xstats_reset,\n+\t.xstats_get_names              = hinic_dev_xstats_get_names,\n+\t.fw_version_get                = hinic_fw_version_get,\n+};\n+\n+static int hinic_check_fw_ver_param(__rte_unused const char *key,\n+\t\t\t    const char *value,\n+\t\t\t    __rte_unused void *opaque)\n+{\n+\tint num = -1;\n+\tchar *end = NULL;\n+\n+\twhile (isblank(*value))\n+\t\tvalue++;\n+\n+\tnum = strtoul(value, &end, 10);\n+\tif ((*end == '-') || errno)\n+\t\treturn -1;\n+\tcheck_fw_ver = num;\n+\n+\treturn 0;\n+}\n+\n+static int\n+hinic_pci_verify_fw_ver(struct rte_eth_dev *eth_dev,\n+\t\t\tstruct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\tconst char *hinic_fw_ver_arg = ETH_HINIC_FW_VER;\n+\tint ret = HINIC_OK;\n+\tchar ver_str[64] = {0};\n+\n+\tif  (hinic_fw_version_get(eth_dev, ver_str, 64) != HINIC_OK)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to get FW version\");\n+\n+\tPMD_DRV_LOG(INFO, \"FW version = %s\\n\", ver_str);\n+\n+\tif (!devargs)\n+\t\treturn ret;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, valid_params);\n+\tif (kvlist == NULL)\n+\t\treturn ret;\n+\n+\tif (!rte_kvargs_count(kvlist, hinic_fw_ver_arg)) {\n+\t\trte_kvargs_free(kvlist);\n+\t\treturn ret;\n+\t}\n+\n+\tif (!rte_kvargs_process(kvlist, hinic_fw_ver_arg,\n+\t\t\thinic_check_fw_ver_param, NULL) && check_fw_ver > 0) {\n+\t\t/* TODO: Verify version compatibility\n+\t\t * and update ret accordingly\n+\t\t */\n+\t}\n+\trte_kvargs_free(kvlist);\n+\n+\treturn ret;\n+}\n+\n+RTE_PMD_REGISTER_PARAM_STRING(net_hinic,\n+\t\t\tETH_HINIC_FW_VER \"=<int>\");\n+\n+static struct rte_pci_id pci_id_hinic_map[] = {\n+\t{ RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) },\n+\t{ RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) },\n+\t{ RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_40GE) },\n+\t{ RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) },\n+\t{.vendor_id = 0},\n+};\n+\n+static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t\t   struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n+\t\tsizeof(struct hinic_nic_dev), hinic_dev_init);\n+}\n+\n+static int hinic_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit);\n+}\n+\n+static struct rte_pci_driver rte_hinic_pmd = {\n+\t.id_table = pci_id_hinic_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n+\t.probe = hinic_pci_probe,\n+\t.remove = hinic_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map);\n+\n+struct hinic_xstats_name_off {\n+\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n+\tu32  offset;\n+};\n+\n+#define HINIC_FUNC_STAT(_stat_item) {\t\\\n+\t.name = #_stat_item, \\\n+\t.offset = offsetof(struct hinic_vport_stats, _stat_item) \\\n+}\n+\n+static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = {\n+\tHINIC_FUNC_STAT(tx_unicast_pkts_vport),\n+\tHINIC_FUNC_STAT(tx_unicast_bytes_vport),\n+\tHINIC_FUNC_STAT(tx_multicast_pkts_vport),\n+\tHINIC_FUNC_STAT(tx_multicast_bytes_vport),\n+\tHINIC_FUNC_STAT(tx_broadcast_pkts_vport),\n+\tHINIC_FUNC_STAT(tx_broadcast_bytes_vport),\n+\n+\tHINIC_FUNC_STAT(rx_unicast_pkts_vport),\n+\tHINIC_FUNC_STAT(rx_unicast_bytes_vport),\n+\tHINIC_FUNC_STAT(rx_multicast_pkts_vport),\n+\tHINIC_FUNC_STAT(rx_multicast_bytes_vport),\n+\tHINIC_FUNC_STAT(rx_broadcast_pkts_vport),\n+\tHINIC_FUNC_STAT(rx_broadcast_bytes_vport),\n+\n+\tHINIC_FUNC_STAT(tx_discard_vport),\n+\tHINIC_FUNC_STAT(rx_discard_vport),\n+\tHINIC_FUNC_STAT(tx_err_vport),\n+\tHINIC_FUNC_STAT(rx_err_vport),\n+};\n+\n+#define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \\\n+\t\tsizeof(hinic_vport_stats_strings[0]))\n+\n+#define HINIC_PORT_STAT(_stat_item) { \\\n+\t.name = #_stat_item, \\\n+\t.offset = offsetof(struct hinic_phy_port_stats, _stat_item) \\\n+}\n+\n+static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = {\n+\tHINIC_PORT_STAT(mac_rx_total_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_total_oct_num),\n+\tHINIC_PORT_STAT(mac_rx_bad_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_bad_oct_num),\n+\tHINIC_PORT_STAT(mac_rx_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_good_oct_num),\n+\tHINIC_PORT_STAT(mac_rx_uni_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_multi_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_broad_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_total_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_total_oct_num),\n+\tHINIC_PORT_STAT(mac_tx_bad_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_bad_oct_num),\n+\tHINIC_PORT_STAT(mac_tx_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_good_oct_num),\n+\tHINIC_PORT_STAT(mac_tx_uni_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_multi_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_broad_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_fragment_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_undersize_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_undermin_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_64_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_oversize_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_jabber_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_mac_pause_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_mac_control_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_sym_err_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_fcs_err_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_send_app_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_fragment_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_undersize_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_undermin_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_64_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_oversize_pkt_num),\n+\tHINIC_PORT_STAT(mac_trans_jabber_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_mac_pause_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_mac_control_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_err_all_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_from_app_good_pkt_num),\n+\tHINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num),\n+};\n+\n+#define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \\\n+\t\tsizeof(hinic_phyport_stats_strings[0]))\n+\n+static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = {\n+\t{\"rx_nombuf\", offsetof(struct hinic_rxq_stats, rx_nombuf)},\n+\n+#ifdef HINIC_XSTAT_RXBUF_INFO\n+\t{\"rxmbuf\", offsetof(struct hinic_rxq_stats, rx_mbuf)},\n+\t{\"avail\", offsetof(struct hinic_rxq_stats, rx_avail)},\n+\t{\"hole\", offsetof(struct hinic_rxq_stats, rx_hole)},\n+\t{\"burst_pkt\", offsetof(struct hinic_rxq_stats, burst_pkts)},\n+#endif\n+\n+#ifdef HINIC_XSTAT_PROF_RX\n+\t{\"app_tsc\", offsetof(struct hinic_rxq_stats, app_tsc)},\n+\t{\"pmd_tsc\", offsetof(struct hinic_rxq_stats, pmd_tsc)},\n+#endif\n+\n+#ifdef HINIC_XSTAT_MBUF_USE\n+\t{\"rx_alloc_mbuf\", offsetof(struct hinic_rxq_stats, alloc_mbuf)},\n+\t{\"rx_free_mbuf\", offsetof(struct hinic_rxq_stats, free_mbuf)},\n+\t{\"rx_left_mbuf\", offsetof(struct hinic_rxq_stats, left_mbuf)},\n+#endif\n+};\n+\n+#define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \\\n+\t\tsizeof(hinic_rxq_stats_strings[0]))\n+\n+static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = {\n+\t{\"tx_busy\", offsetof(struct hinic_txq_stats, tx_busy)},\n+\t{\"offload_errors\", offsetof(struct hinic_txq_stats, off_errs)},\n+\t{\"copy_pkts\", offsetof(struct hinic_txq_stats, cpy_pkts)},\n+\t{\"rl_drop\", offsetof(struct hinic_txq_stats, rl_drop)},\n+\n+#ifdef HINIC_XSTAT_PROF_TX\n+\t{\"app_tsc\", offsetof(struct hinic_txq_stats, app_tsc)},\n+\t{\"pmd_tsc\", offsetof(struct hinic_txq_stats, pmd_tsc)},\n+\t{\"burst_pkts\", offsetof(struct hinic_txq_stats, burst_pkts)},\n+#endif\n+};\n+\n+#define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \\\n+\t\tsizeof(hinic_txq_stats_strings[0]))\n+\n+static const struct rte_eth_desc_lim hinic_rx_desc_lim = {\n+\t.nb_max = HINIC_MAX_QUEUE_DEPTH,\n+\t.nb_min = HINIC_MIN_QUEUE_DEPTH,\n+\t.nb_align = HINIC_RXD_ALIGN,\n+};\n+\n+static const struct rte_eth_desc_lim hinic_tx_desc_lim = {\n+\t.nb_max = HINIC_MAX_QUEUE_DEPTH,\n+\t.nb_min = HINIC_MIN_QUEUE_DEPTH,\n+\t.nb_align = HINIC_TXD_ALIGN,\n+};\n+\n+static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev)\n+{\n+\treturn (HINIC_VPORT_XSTATS_NUM +\n+\t\tHINIC_PHYPORT_XSTATS_NUM +\n+\t\tHINIC_RXQ_XSTATS_NUM * nic_dev->num_rq +\n+\t\tHINIC_TXQ_XSTATS_NUM * nic_dev->num_sq);\n+}\n+\n+static void\n+hinic_dev_handle_aeq_event(struct hinic_nic_dev *nic_dev, void *param)\n+{\n+\tstruct hinic_hwdev *hwdev = nic_dev->hwdev;\n+\tstruct hinic_eq *aeq = &hwdev->aeqs->aeq[0];\n+\n+\t/* clear resend timer cnt register */\n+\thinic_misx_intr_clear_resend_bit(hwdev, aeq->eq_irq.msix_entry_idx,\n+\t\t\t\t\t EQ_MSIX_RESEND_TIMER_CLEAR);\n+\t(void)hinic_aeq_poll_msg(aeq, 0, param);\n+}\n+\n+/**\n+ * Interrupt handler triggered by NIC  for handling\n+ * specific event.\n+ *\n+ * @param: The address of parameter (struct rte_eth_dev *) regsitered before.\n+ **/\n+static void hinic_dev_interrupt_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\tif (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) {\n+\t\tPMD_DRV_LOG(INFO, \"Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d\",\n+\t\t\t    nic_dev->proc_dev_name, dev->data->port_id);\n+\t\treturn;\n+\t}\n+\n+\t/* aeq0 msg handler */\n+\thinic_dev_handle_aeq_event(nic_dev, param);\n+}\n+\n+static int hinic_func_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct rte_ether_addr *eth_addr;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tint rc;\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\n+\t/* EAL is SECONDARY and eth_dev is already created */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\trc = rte_intr_callback_register(&pci_dev->intr_handle,\n+\t\t\t\t\t\thinic_dev_interrupt_handler,\n+\t\t\t\t\t\t(void *)eth_dev);\n+\t\tif (rc)\n+\t\t\tPMD_DRV_LOG(ERR, \"Initialize %s failed in secondary process\",\n+\t\t\t\t    eth_dev->data->name);\n+\n+\t\treturn rc;\n+\t}\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);\n+\tmemset(nic_dev, 0, sizeof(*nic_dev));\n+\n+\tsnprintf(nic_dev->proc_dev_name,\n+\t\t sizeof(nic_dev->proc_dev_name),\n+\t\t \"hinic-%.4x:%.2x:%.2x.%x\",\n+\t\t pci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t pci_dev->addr.devid, pci_dev->addr.function);\n+\n+\trte_eth_copy_pci_info(eth_dev, pci_dev);\n+\n+\t/* clear RX ring mbuf allocated failed */\n+\teth_dev->data->rx_mbuf_alloc_failed = 0;\n+\n+\t/* alloc mac_addrs */\n+\teth_addr = (struct rte_ether_addr *)rte_zmalloc(\"hinic_mac\",\n+\t\t\t\t\t\t\tsizeof(*eth_addr), 0);\n+\tif (!eth_addr) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate ethernet addresses' memory failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+\t\trc = -ENOMEM;\n+\t\tgoto eth_addr_fail;\n+\t}\n+\teth_dev->data->mac_addrs = eth_addr;\n+\n+\t/* create hardware nic_device */\n+\trc = hinic_nic_dev_create(eth_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Create nic device failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+\t\tgoto create_nic_dev_fail;\n+\t}\n+\n+\trc = hinic_init_mac_addr(eth_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize mac table failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+\t\tgoto init_mac_fail;\n+\t}\n+\n+\t/* register callback func to eal lib */\n+\trc = rte_intr_callback_register(&pci_dev->intr_handle,\n+\t\t\t\t\thinic_dev_interrupt_handler,\n+\t\t\t\t\t(void *)eth_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Register rte interrupt callback failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+\t\tgoto reg_intr_cb_fail;\n+\t}\n+\n+\t/* Verify fw-driver version compatibility */\n+\trc = hinic_pci_verify_fw_ver(eth_dev, pci_dev->device.devargs);\n+\tif (rc != HINIC_OK)\n+\t\tgoto enable_intr_fail;\n+\n+\t/* enable uio/vfio intr/eventfd mapping */\n+\trc = rte_intr_enable(&pci_dev->intr_handle);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Enable rte interrupt failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+\t\tgoto enable_intr_fail;\n+\t}\n+\thinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);\n+\n+\thinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status);\n+\tPMD_DRV_LOG(INFO, \"Initialize %s in primary successfully\",\n+\t\t    eth_dev->data->name);\n+\n+\treturn 0;\n+\n+enable_intr_fail:\n+\t(void)rte_intr_callback_unregister(&pci_dev->intr_handle,\n+\t\t\t\t\t   hinic_dev_interrupt_handler,\n+\t\t\t\t\t   (void *)eth_dev);\n+\n+reg_intr_cb_fail:\n+\thinic_deinit_mac_addr(eth_dev);\n+\n+init_mac_fail:\n+\thinic_nic_dev_destroy(eth_dev);\n+\n+create_nic_dev_fail:\n+\trte_free(eth_addr);\n+\teth_dev->data->mac_addrs = NULL;\n+\n+eth_addr_fail:\n+\tPMD_DRV_LOG(INFO, \"Initialize %s in primary failed\",\n+\t\t    eth_dev->data->name);\n+\treturn rc;\n+}\n+\n+static int hinic_dev_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev;\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\n+\tPMD_DRV_LOG(INFO, \"Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process\",\n+\t\t    pci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t    pci_dev->addr.devid, pci_dev->addr.function,\n+\t\t    (rte_eal_process_type() == RTE_PROC_PRIMARY) ?\n+\t\t    \"primary\" : \"secondary\");\n+\n+\t/* rte_eth_dev ops, rx_burst and tx_burst */\n+\teth_dev->dev_ops = &hinic_pmd_ops;\n+\teth_dev->rx_pkt_burst = hinic_recv_pkts;\n+\teth_dev->tx_pkt_burst = hinic_xmit_pkts;\n+\n+\treturn hinic_func_init(eth_dev);\n+}\n+\n+/**\n+ * PF Function device uninit.\n+ */\n+static int hinic_dev_uninit(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\thinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status);\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\thinic_dev_close(dev);\n+\n+\tdev->dev_ops = NULL;\n+\tdev->rx_pkt_burst = NULL;\n+\tdev->tx_pkt_burst = NULL;\n+\n+\trte_free(dev->data->mac_addrs);\n+\tdev->data->mac_addrs = NULL;\n+\n+\treturn HINIC_OK;\n+}\n+\n+/**\n+ * Ethernet device configuration.\n+ *\n+ * Prepare the driver for a given number of TX and RX queues, mtu size\n+ * and configure RSS.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+int hinic_dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct hinic_nic_io *nic_io;\n+\tint err;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tnic_io = nic_dev->hwdev->nic_io;\n+\n+\tnic_dev->num_sq =  dev->data->nb_tx_queues;\n+\tnic_dev->num_rq = dev->data->nb_rx_queues;\n+\n+\tnic_io->num_sqs =  dev->data->nb_tx_queues;\n+\tnic_io->num_rqs = dev->data->nb_rx_queues;\n+\n+\t/* queue pair is max_num(sq, rq) */\n+\tnic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ?\n+\t\t\tnic_dev->num_sq : nic_dev->num_rq;\n+\tnic_io->num_qps = nic_dev->num_qps;\n+\n+\tif (nic_dev->num_qps > nic_io->max_qps) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Queue number out of range, get queue_num:%d, max_queue_num:%d\",\n+\t\t\tnic_dev->num_qps, nic_io->max_qps);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* mtu size is 256~9600 */\n+\tif (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE ||\n+\t    dev->data->dev_conf.rxmode.max_rx_pkt_len >\n+\t    HINIC_MAX_JUMBO_FRAME_SIZE) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"Max rx pkt len out of range, get max_rx_pkt_len:%d, \"\n+\t\t\t\"expect between %d and %d\",\n+\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len,\n+\t\t\tHINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tnic_dev->mtu_size =\n+\t\tHINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len);\n+\n+\t/* rss template */\n+\terr = hinic_config_mq_mode(dev, TRUE);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Config multi-queue failed\");\n+\t\treturn err;\n+\t}\n+\n+\treturn HINIC_OK;\n+}\n+\n+/**\n+ * DPDK callback to create the receive queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param queue_idx\n+ *   RX queue index.\n+ * @param nb_desc\n+ *   Number of descriptors for receive queue.\n+ * @param socket_id\n+ *   NUMA socket on which memory must be allocated.\n+ * @param rx_conf\n+ *   Thresholds parameters (unused_).\n+ * @param mp\n+ *   Memory pool for buffer allocations.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool *mp)\n+{\n+\tint rc;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct hinic_rxq *rxq;\n+\tu16 rq_depth, rx_free_thresh;\n+\tu32 buf_size;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\t/* queue depth must be power of 2, otherwise will be aligned up */\n+\trq_depth = (nb_desc & (nb_desc - 1)) ?\n+\t\t((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;\n+\n+\t/*\n+\t * Validate number of receive descriptors.\n+\t * It must not exceed hardware maximum and minimum.\n+\t */\n+\tif (rq_depth > HINIC_MAX_QUEUE_DEPTH ||\n+\t\trq_depth < HINIC_MIN_QUEUE_DEPTH) {\n+\t\tPMD_DRV_LOG(ERR, \"RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)\",\n+\t\t\t    HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,\n+\t\t\t    (int)nb_desc, (int)rq_depth,\n+\t\t\t    (int)dev->data->port_id, (int)queue_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * The RX descriptor ring will be cleaned after rxq->rx_free_thresh\n+\t * descriptors are used or if the number of descriptors required\n+\t * to transmit a packet is greater than the number of free RX\n+\t * descriptors.\n+\t * The following constraints must be satisfied:\n+\t *  rx_free_thresh must be greater than 0.\n+\t *  rx_free_thresh must be less than the size of the ring minus 1.\n+\t * When set to zero use default values.\n+\t */\n+\trx_free_thresh = (u16)((rx_conf->rx_free_thresh) ?\n+\t\t\trx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH);\n+\tif (rx_free_thresh >= (rq_depth - 1)) {\n+\t\tPMD_DRV_LOG(ERR, \"rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)\",\n+\t\t\t    (unsigned int)rx_free_thresh,\n+\t\t\t    (int)dev->data->port_id,\n+\t\t\t    (int)queue_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trxq = (struct hinic_rxq *)rte_zmalloc_socket(\"hinic_rx_queue\",\n+\t\t\t\t\t\t     sizeof(struct hinic_rxq),\n+\t\t\t\t\t\t     RTE_CACHE_LINE_SIZE,\n+\t\t\t\t\t\t     socket_id);\n+\tif (!rxq) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate rxq[%d] failed, dev_name: %s\",\n+\t\t\t    queue_idx, dev->data->name);\n+\t\treturn -ENOMEM;\n+\t}\n+\tnic_dev->rxqs[queue_idx] = rxq;\n+\n+\t/* alloc rx sq hw wqepage*/\n+\trc = hinic_create_rq(nic_dev, queue_idx, rq_depth);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Create rxq[%d] failed, dev_name: %s, rq_depth: %d\",\n+\t\t\t    queue_idx, dev->data->name, rq_depth);\n+\t\tgoto ceate_rq_fail;\n+\t}\n+\n+\t/* mbuf pool must be assigned before setup rx resources */\n+\trxq->mb_pool = mp;\n+\n+\trc =\n+\thinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n+\t\t\t\t  RTE_PKTMBUF_HEADROOM, &buf_size);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Adjust buf size failed, dev_name: %s\",\n+\t\t\t    dev->data->name);\n+\t\tgoto adjust_bufsize_fail;\n+\t}\n+\n+\t/* rx queue info, rearm control */\n+\trxq->wq = &nic_dev->nic_io->rq_wq[queue_idx];\n+\trxq->pi_virt_addr = nic_dev->nic_io->qps[queue_idx].rq.pi_virt_addr;\n+\trxq->nic_dev = nic_dev;\n+\trxq->q_id = queue_idx;\n+\trxq->q_depth = rq_depth;\n+\trxq->buf_len = (u16)buf_size;\n+\trxq->rx_free_thresh = rx_free_thresh;\n+\n+\t/* the last point cant do mbuf rearm in bulk */\n+\trxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh;\n+\n+\t/* device port identifier */\n+\trxq->port_id = dev->data->port_id;\n+\n+\t/* alloc rx_cqe and prepare rq_wqe */\n+\trc = hinic_setup_rx_resources(rxq);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Setup rxq[%d] rx_resources failed, dev_name:%s\",\n+\t\t\t    queue_idx, dev->data->name);\n+\t\tgoto setup_rx_res_err;\n+\t}\n+\n+\t/* record nic_dev rxq in rte_eth rx_queues */\n+\tdev->data->rx_queues[queue_idx] = rxq;\n+\n+\tPMD_DRV_LOG(INFO, \"Setup rxq[%d] successfully, dev_name: %s, rq_depth: %d\",\n+\t\t    queue_idx, dev->data->name, rq_depth);\n+\treturn 0;\n+\n+setup_rx_res_err:\n+adjust_bufsize_fail:\n+\thinic_destroy_rq(nic_dev, queue_idx);\n+\n+ceate_rq_fail:\n+\trte_free(rxq);\n+\n+\treturn rc;\n+}\n+\n+static void hinic_reset_rx_queue(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_rxq *rxq;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tint q_id = 0;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\tfor (q_id = 0; q_id < nic_dev->num_rq; q_id++) {\n+\t\trxq = (struct hinic_rxq *)dev->data->rx_queues[q_id];\n+\n+\t\trxq->wq->cons_idx = 0;\n+\t\trxq->wq->prod_idx = 0;\n+\t\trxq->wq->delta = rxq->q_depth;\n+\t\trxq->wq->mask = rxq->q_depth - 1;\n+\n+\t\t/* alloc mbuf to rq */\n+\t\thinic_rx_alloc_pkts(rxq);\n+\t}\n+}\n+\n+/**\n+ * DPDK callback to configure the transmit queue.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param queue_idx\n+ *   Transmit queue index.\n+ * @param nb_desc\n+ *   Number of descriptors for transmit queue.\n+ * @param socket_id\n+ *   NUMA socket on which memory must be allocated.\n+ * @param tx_conf\n+ *   Tx queue configuration parameters.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t __rte_unused const struct rte_eth_txconf *tx_conf)\n+{\n+\tint rc;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct hinic_txq *txq;\n+\tu16 sq_depth, tx_free_thresh;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\t/* queue depth must be power of 2, otherwise will be aligned up */\n+\tsq_depth = (nb_desc & (nb_desc - 1)) ?\n+\t\t\t((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;\n+\n+\t/*\n+\t * Validate number of transmit descriptors.\n+\t * It must not exceed hardware maximum and minimum.\n+\t */\n+\tif (sq_depth > HINIC_MAX_QUEUE_DEPTH ||\n+\t\tsq_depth < HINIC_MIN_QUEUE_DEPTH) {\n+\t\tPMD_DRV_LOG(ERR, \"TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)\",\n+\t\t\t  HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,\n+\t\t\t  (int)nb_desc, (int)sq_depth,\n+\t\t\t  (int)dev->data->port_id, (int)queue_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * The TX descriptor ring will be cleaned after txq->tx_free_thresh\n+\t * descriptors are used or if the number of descriptors required\n+\t * to transmit a packet is greater than the number of free TX\n+\t * descriptors.\n+\t * The following constraints must be satisfied:\n+\t *  tx_free_thresh must be greater than 0.\n+\t *  tx_free_thresh must be less than the size of the ring minus 1.\n+\t * When set to zero use default values.\n+\t */\n+\ttx_free_thresh = (u16)((tx_conf->tx_free_thresh) ?\n+\t\t\ttx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH);\n+\tif (tx_free_thresh >= (sq_depth - 1)) {\n+\t\tPMD_DRV_LOG(ERR, \"tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)\",\n+\t\t\t(unsigned int)tx_free_thresh, (int)dev->data->port_id,\n+\t\t\t(int)queue_idx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttxq = (struct hinic_txq *)rte_zmalloc_socket(\"hinic_tx_queue\",\n+\t\tsizeof(struct hinic_txq), RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (!txq) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate txq[%d] failed, dev_name: %s\",\n+\t\t\t    queue_idx, dev->data->name);\n+\t\treturn -ENOMEM;\n+\t}\n+\tnic_dev->txqs[queue_idx] = txq;\n+\n+\t/* alloc tx sq hw wqepage */\n+\trc = hinic_create_sq(nic_dev, queue_idx, sq_depth);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Create txq[%d] failed, dev_name: %s, sq_depth: %d\",\n+\t\t\t    queue_idx, dev->data->name, sq_depth);\n+\t\tgoto create_sq_fail;\n+\t}\n+\n+\ttxq->q_id = queue_idx;\n+\ttxq->q_depth = sq_depth;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->tx_free_thresh = tx_free_thresh;\n+\ttxq->nic_dev = nic_dev;\n+\ttxq->wq = &nic_dev->nic_io->sq_wq[queue_idx];\n+\ttxq->sq = &nic_dev->nic_io->qps[queue_idx].sq;\n+\ttxq->cons_idx_addr = nic_dev->nic_io->qps[queue_idx].sq.cons_idx_addr;\n+\ttxq->sq_head_addr = HINIC_GET_WQ_HEAD(txq);\n+\ttxq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) -\n+\t\t\t\t\tsizeof(struct hinic_sq_bufdesc);\n+\ttxq->cos = nic_dev->default_cos;\n+\n+\t/* alloc software txinfo */\n+\trc = hinic_setup_tx_resources(txq);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Setup txq[%d] tx_resources failed, dev_name: %s\",\n+\t\t\t    queue_idx, dev->data->name);\n+\t\tgoto setup_tx_res_fail;\n+\t}\n+\n+\t/* record nic_dev txq in rte_eth tx_queues */\n+\tdev->data->tx_queues[queue_idx] = txq;\n+\n+\treturn HINIC_OK;\n+\n+setup_tx_res_fail:\n+\thinic_destroy_sq(nic_dev, queue_idx);\n+\n+create_sq_fail:\n+\trte_free(txq);\n+\n+\treturn rc;\n+}\n+\n+static void hinic_reset_tx_queue(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct hinic_txq *txq;\n+\tstruct hinic_nic_io *nic_io;\n+\tstruct hinic_hwdev *hwdev;\n+\tvolatile u32 *ci_addr;\n+\tint q_id = 0;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\thwdev = nic_dev->hwdev;\n+\tnic_io = hwdev->nic_io;\n+\n+\tfor (q_id = 0; q_id < nic_dev->num_sq; q_id++) {\n+\t\ttxq = (struct hinic_txq *)dev->data->tx_queues[q_id];\n+\n+\t\ttxq->wq->cons_idx = 0;\n+\t\ttxq->wq->prod_idx = 0;\n+\t\ttxq->wq->delta = txq->q_depth;\n+\t\ttxq->wq->mask  = txq->q_depth - 1;\n+\n+\t\t/*clear hardware ci*/\n+\t\tci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base,\n+\t\t\t\t\t\t\tq_id);\n+\t\t*ci_addr = 0;\n+\t}\n+}\n+\n+/**\n+ * Get link speed from NIC.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param speed_capa\n+ *   Pointer to link speed structure.\n+ */\n+static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tu32 supported_link, advertised_link;\n+\tint err;\n+\n+#define HINIC_LINK_MODE_SUPPORT_1G\t(1U << HINIC_GE_BASE_KX)\n+\n+#define HINIC_LINK_MODE_SUPPORT_10G\t(1U << HINIC_10GE_BASE_KR)\n+\n+#define HINIC_LINK_MODE_SUPPORT_25G\t((1U << HINIC_25GE_BASE_KR_S) | \\\n+\t\t\t\t\t(1U << HINIC_25GE_BASE_CR_S) | \\\n+\t\t\t\t\t(1U << HINIC_25GE_BASE_KR) | \\\n+\t\t\t\t\t(1U << HINIC_25GE_BASE_CR))\n+\n+#define HINIC_LINK_MODE_SUPPORT_40G\t((1U << HINIC_40GE_BASE_KR4) | \\\n+\t\t\t\t\t(1U << HINIC_40GE_BASE_CR4))\n+\n+#define HINIC_LINK_MODE_SUPPORT_100G\t((1U << HINIC_100GE_BASE_KR4) | \\\n+\t\t\t\t\t(1U << HINIC_100GE_BASE_CR4))\n+\n+\terr = hinic_get_link_mode(nic_dev->hwdev,\n+\t\t\t\t  &supported_link, &advertised_link);\n+\tif (err || supported_link == HINIC_SUPPORTED_UNKNOWN ||\n+\t    advertised_link == HINIC_SUPPORTED_UNKNOWN) {\n+\t\tPMD_DRV_LOG(WARNING, \"Get speed capability info failed, device: %s, port_id: %u\",\n+\t\t\t  nic_dev->proc_dev_name, dev->data->port_id);\n+\t} else {\n+\t\t*speed_capa = 0;\n+\t\tif (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G))\n+\t\t\t*speed_capa |= ETH_LINK_SPEED_1G;\n+\t\tif (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G))\n+\t\t\t*speed_capa |= ETH_LINK_SPEED_10G;\n+\t\tif (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G))\n+\t\t\t*speed_capa |= ETH_LINK_SPEED_25G;\n+\t\tif (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G))\n+\t\t\t*speed_capa |= ETH_LINK_SPEED_40G;\n+\t\tif (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G))\n+\t\t\t*speed_capa |= ETH_LINK_SPEED_100G;\n+\t}\n+}\n+\n+/**\n+ * DPDK callback to get information about the device.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param info\n+ *   Pointer to Info structure output buffer.\n+ */\n+void hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\tinfo->max_rx_queues  = nic_dev->nic_cap.max_rqs;\n+\tinfo->max_tx_queues  = nic_dev->nic_cap.max_sqs;\n+\tinfo->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE;\n+\tinfo->max_rx_pktlen  = HINIC_MAX_JUMBO_FRAME_SIZE;\n+\tinfo->max_mac_addrs  = HINIC_MAX_MAC_ADDRS;\n+\n+\thinic_get_speed_capa(dev, &info->speed_capa);\n+\tinfo->rx_queue_offload_capa = 0;\n+\tinfo->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n+\t\t\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\tDEV_RX_OFFLOAD_VLAN_FILTER |\n+\t\t\t\tDEV_RX_OFFLOAD_JUMBO_FRAME;\n+\n+\tinfo->tx_queue_offload_capa = 0;\n+\tinfo->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n+\t\t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |\n+\t\t\t\tDEV_TX_OFFLOAD_TCP_TSO |\n+\t\t\t\tDEV_TX_OFFLOAD_MULTI_SEGS;\n+\n+\tinfo->hash_key_size = HINIC_RSS_KEY_SIZE;\n+\tinfo->reta_size = HINIC_RSS_INDIR_SIZE;\n+\tinfo->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL;\n+\tinfo->rx_desc_lim = hinic_rx_desc_lim;\n+\tinfo->tx_desc_lim = hinic_tx_desc_lim;\n+}\n+\n+int hinic_rxtx_configure(struct rte_eth_dev *dev)\n+{\n+\tint err;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\t/* rx configure, if rss enable, need to init default configuration */\n+\terr = hinic_rx_configure(dev);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Configure rss failed\");\n+\t\treturn err;\n+\t}\n+\n+\t/* rx mode init */\n+\terr = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Configure rx_mode:0x%x failed\",\n+\t\t\tHINIC_DEFAULT_RX_MODE);\n+\t\tgoto set_rx_mode_fail;\n+\t}\n+\n+\treturn HINIC_OK;\n+\n+set_rx_mode_fail:\n+\thinic_rx_remove_configure(dev);\n+\n+\treturn err;\n+}\n+\n+static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\t(void)hinic_config_rx_mode(nic_dev, 0);\n+\thinic_rx_remove_configure(dev);\n+}\n+\n+/**\n+ * DPDK callback to start the device.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ *   0 on success, negative errno value on failure.\n+ */\n+int hinic_dev_start(struct rte_eth_dev *dev)\n+{\n+\tint rc;\n+\tchar *name;\n+\tstruct hinic_nic_dev *nic_dev;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tname = dev->data->name;\n+\n+\t/* reset rx and tx queue */\n+\thinic_reset_rx_queue(dev);\n+\thinic_reset_tx_queue(dev);\n+\n+\t/* init txq and rxq context */\n+\trc = hinic_init_qp_ctxts(nic_dev->hwdev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize qp context failed, dev_name:%s\",\n+\t\t\t    name);\n+\t\tgoto init_qp_fail;\n+\t}\n+\n+\t/* rss template */\n+\trc = hinic_config_mq_mode(dev, TRUE);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Configure mq mode failed, dev_name: %s\",\n+\t\t\t    name);\n+\t\tgoto cfg_mq_mode_fail;\n+\t}\n+\n+\t/* set default mtu */\n+\trc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Set mtu_size[%d] failed, dev_name: %s\",\n+\t\t\t    nic_dev->mtu_size, name);\n+\t\tgoto set_mtu_fail;\n+\t}\n+\n+\t/* configure rss rx_mode and other rx or tx default feature */\n+\trc = hinic_rxtx_configure(dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Configure tx and rx failed, dev_name: %s\",\n+\t\t\t    name);\n+\t\tgoto cfg_rxtx_fail;\n+\t}\n+\n+\t/* open virtual port and ready to start packet receiving */\n+\trc = hinic_set_vport_enable(nic_dev->hwdev, true);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Enable vport failed, dev_name:%s\", name);\n+\t\tgoto en_vport_fail;\n+\t}\n+\n+\t/* open physical port and start packet receiving */\n+\trc = hinic_set_port_enable(nic_dev->hwdev, true);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Enable physical port failed, dev_name:%s\",\n+\t\t\t    name);\n+\t\tgoto en_port_fail;\n+\t}\n+\n+\t/* update eth_dev link status */\n+\tif (dev->data->dev_conf.intr_conf.lsc != 0)\n+\t\t(void)hinic_link_update(dev, 0);\n+\n+\thinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status);\n+\n+\tPMD_DRV_LOG(INFO, \"Device %s started\", name);\n+\n+\treturn 0;\n+\n+en_port_fail:\n+\t(void)hinic_set_vport_enable(nic_dev->hwdev, false);\n+\n+en_vport_fail:\n+\t/* Flush tx && rx chip resources in case of set vport fake fail */\n+\t(void)hinic_flush_qp_res(nic_dev->hwdev);\n+\trte_delay_ms(100);\n+\n+\thinic_remove_rxtx_configure(dev);\n+\n+cfg_rxtx_fail:\n+set_mtu_fail:\n+cfg_mq_mode_fail:\n+\thinic_free_qp_ctxts(nic_dev->hwdev);\n+\n+init_qp_fail:\n+\thinic_free_all_rx_mbuf(dev);\n+\thinic_free_all_tx_mbuf(dev);\n+\n+\treturn rc;\n+}\n+\n+/**\n+ * DPDK callback to release the receive queue.\n+ *\n+ * @param queue\n+ *   Generic receive queue pointer.\n+ */\n+void hinic_rx_queue_release(void *queue)\n+{\n+\tstruct hinic_rxq *rxq = (struct hinic_rxq *)queue;\n+\tstruct hinic_nic_dev *nic_dev;\n+\n+\tif (!rxq) {\n+\t\tPMD_DRV_LOG(WARNING, \"Rxq is null when release\");\n+\t\treturn;\n+\t}\n+\tnic_dev = rxq->nic_dev;\n+\n+\t/* free rxq_pkt mbuf */\n+\thinic_free_all_rx_skbs(rxq);\n+\n+\t/* free rxq_cqe, rxq_info */\n+\thinic_free_rx_resources(rxq);\n+\n+\t/* free root rq wq */\n+\thinic_destroy_rq(nic_dev, rxq->q_id);\n+\n+\tnic_dev->rxqs[rxq->q_id] = NULL;\n+\n+\t/* free rxq */\n+\trte_free(rxq);\n+}\n+\n+/**\n+ * DPDK callback to release the transmit queue.\n+ *\n+ * @param queue\n+ *   Generic transmit queue pointer.\n+ */\n+void hinic_tx_queue_release(void *queue)\n+{\n+\tstruct hinic_txq *txq = (struct hinic_txq *)queue;\n+\tstruct hinic_nic_dev *nic_dev;\n+\n+\tif (!txq) {\n+\t\tPMD_DRV_LOG(WARNING, \"Txq is null when release\");\n+\t\treturn;\n+\t}\n+\tnic_dev = txq->nic_dev;\n+\n+\t/* free txq_pkt mbuf */\n+\thinic_free_all_tx_skbs(txq);\n+\n+\t/* free txq_info */\n+\thinic_free_tx_resources(txq);\n+\n+\t/* free root sq wq */\n+\thinic_destroy_sq(nic_dev, txq->q_id);\n+\tnic_dev->txqs[txq->q_id] = NULL;\n+\n+\t/* free txq */\n+\trte_free(txq);\n+}\n+\n+void hinic_free_all_rq(struct hinic_nic_dev *nic_dev)\n+{\n+\tu16 q_id;\n+\n+\tfor (q_id = 0; q_id < nic_dev->num_rq; q_id++)\n+\t\thinic_destroy_rq(nic_dev, q_id);\n+}\n+\n+void hinic_free_all_sq(struct hinic_nic_dev *nic_dev)\n+{\n+\tu16 q_id;\n+\n+\tfor (q_id = 0; q_id < nic_dev->num_sq; q_id++)\n+\t\thinic_destroy_sq(nic_dev, q_id);\n+}\n+\n+/**\n+ * DPDK callback to stop the device.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ */\n+void hinic_dev_stop(struct rte_eth_dev *dev)\n+{\n+\tint rc;\n+\tchar *name;\n+\tuint16_t port_id;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct rte_eth_link link;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tname = dev->data->name;\n+\tport_id = dev->data->port_id;\n+\n+\tif (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) {\n+\t\tPMD_DRV_LOG(INFO, \"Device %s already stopped\", name);\n+\t\treturn;\n+\t}\n+\n+\t/* just stop phy port and vport */\n+\trc = hinic_set_port_enable(nic_dev->hwdev, false);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(WARNING, \"Disable phy port failed, error: %d, dev_name:%s, port_id:%d\",\n+\t\t\t  rc, name, port_id);\n+\n+\trc = hinic_set_vport_enable(nic_dev->hwdev, false);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(WARNING, \"Disable vport failed, error: %d, dev_name:%s, port_id:%d\",\n+\t\t\t  rc, name, port_id);\n+\n+\t/* Clear recorded link status */\n+\tmemset(&link, 0, sizeof(link));\n+\t(void)rte_eth_linkstatus_set(dev, &link);\n+\n+\t/* flush pending io request */\n+\trc = hinic_rx_tx_flush(nic_dev->hwdev);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(WARNING, \"Flush pending io failed, error: %d, dev_name: %s, port_id: %d\",\n+\t\t\t    rc, name, port_id);\n+\n+\t/* clean rss table and rx_mode */\n+\thinic_remove_rxtx_configure(dev);\n+\n+\t/* clean root context */\n+\thinic_free_qp_ctxts(nic_dev->hwdev);\n+\n+\t/* free mbuf */\n+\thinic_free_all_rx_mbuf(dev);\n+\thinic_free_all_tx_mbuf(dev);\n+\n+\tPMD_DRV_LOG(INFO, \"Device %s stopped\", name);\n+}\n+\n+void hinic_disable_interrupt(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tint ret, retries = 0;\n+\n+\thinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);\n+\n+\t/* disable msix interrupt in hardware */\n+\thinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE);\n+\n+\t/* disable rte interrupt */\n+\tret = rte_intr_disable(&pci_dev->intr_handle);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(ERR, \"Disable intr failed: %d\", ret);\n+\n+\tdo {\n+\t\tret =\n+\t\trte_intr_callback_unregister(&pci_dev->intr_handle,\n+\t\t\t\t\t     hinic_dev_interrupt_handler, dev);\n+\t\tif (ret >= 0) {\n+\t\t\tbreak;\n+\t\t} else if (ret == -EAGAIN) {\n+\t\t\trte_delay_ms(100);\n+\t\t\tretries++;\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR, \"intr callback unregister failed: %d\",\n+\t\t\t\t    ret);\n+\t\t\tbreak;\n+\t\t}\n+\t} while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES);\n+\n+\tif (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES)\n+\t\tPMD_DRV_LOG(ERR, \"Unregister intr callback failed after %d retries\",\n+\t\t\t    retries);\n+}\n+\n+/**\n+ * DPDK callback to close the device.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ */\n+void hinic_dev_close(struct rte_eth_dev *dev)\n+{\n+\tchar *name;\n+\tstruct hinic_nic_dev *nic_dev;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tname = dev->data->name;\n+\n+\tif (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) {\n+\t\tPMD_DRV_LOG(INFO, \"Device %s already closed\", name);\n+\t\treturn;\n+\t}\n+\n+\t/* stop device first */\n+\thinic_dev_stop(dev);\n+\n+\t/* rx_cqe, rx_info */\n+\thinic_free_all_rx_resources(dev);\n+\n+\t/* tx_info */\n+\thinic_free_all_tx_resources(dev);\n+\n+\t/* free wq, pi_dma_addr */\n+\thinic_free_all_rq(nic_dev);\n+\n+\t/* free wq, db_addr */\n+\thinic_free_all_sq(nic_dev);\n+\n+\t/* deinit mac vlan tbl */\n+\thinic_deinit_mac_addr(dev);\n+\n+\t/* disable hardware and uio interrupt */\n+\thinic_disable_interrupt(dev);\n+\n+\t/* deinit nic hardware device */\n+\thinic_nic_dev_destroy(dev);\n+\n+\tPMD_DRV_LOG(INFO, \"Device %s closed\", name);\n+}\n+\n+static int hinic_priv_get_dev_link_status(struct hinic_nic_dev *nic_dev,\n+\t\t\t\t\t  struct rte_eth_link *link)\n+{\n+\tint rc = HINIC_OK;\n+\tu8 port_link_status = 0;\n+\tstruct nic_port_info port_link_info;\n+\tstruct hinic_hwdev *nic_hwdev = nic_dev->hwdev;\n+\tuint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M,\n+\t\t\t\t\tETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G,\n+\t\t\t\t\tETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G,\n+\t\t\t\t\tETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G};\n+\n+\tmemset(link, 0, sizeof(*link));\n+\trc = hinic_get_link_status(nic_hwdev, &port_link_status);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnic_dev->link_status = port_link_status;\n+\tif (!port_link_status) {\n+\t\tlink->link_status = ETH_LINK_DOWN;\n+\t\tlink->link_speed = 0;\n+\t\tlink->link_duplex = ETH_LINK_HALF_DUPLEX;\n+\t\tlink->link_autoneg = ETH_LINK_FIXED;\n+\t\treturn rc;\n+\t}\n+\n+\tmemset(&port_link_info, 0, sizeof(port_link_info));\n+\trc = hinic_get_port_info(nic_hwdev, &port_link_info);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tlink->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX];\n+\tlink->link_duplex = port_link_info.duplex;\n+\tlink->link_autoneg = port_link_info.autoneg_state;\n+\tlink->link_status = port_link_status;\n+\n+\treturn rc;\n+}\n+\n+static int hinic_set_dev_promiscuous(struct hinic_nic_dev *nic_dev, bool enable)\n+{\n+\tu32 rx_mode_ctrl = nic_dev->rx_mode_status;\n+\n+\tif (enable)\n+\t\trx_mode_ctrl |= HINIC_RX_MODE_PROMISC;\n+\telse\n+\t\trx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC);\n+\n+\treturn hinic_config_rx_mode(nic_dev, rx_mode_ctrl);\n+}\n+\n+/**\n+ * DPDK callback to get device statistics.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param stats\n+ *   Stats structure output buffer.\n+ *\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tint i, err, q_num;\n+\tu64 rx_discards_pmd = 0;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tstruct hinic_vport_stats vport_stats;\n+\tstruct hinic_rxq\t*rxq = NULL;\n+\tstruct hinic_rxq_stats rxq_stats;\n+\tstruct hinic_txq\t*txq = NULL;\n+\tstruct hinic_txq_stats txq_stats;\n+\n+\terr = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Get vport stats from fw failed, nic_dev: %s\",\n+\t\t\tnic_dev->proc_dev_name);\n+\t\treturn err;\n+\t}\n+\n+\tdev->data->rx_mbuf_alloc_failed = 0;\n+\n+\t/* rx queue stats */\n+\tq_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?\n+\t\t\tnic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS;\n+\tfor (i = 0; i < q_num; i++) {\n+\t\trxq = nic_dev->rxqs[i];\n+\t\thinic_rxq_get_stats(rxq, &rxq_stats);\n+\t\tstats->q_ipackets[i] = rxq_stats.packets;\n+\t\tstats->q_ibytes[i] = rxq_stats.bytes;\n+\t\tstats->q_errors[i] = rxq_stats.rx_discards;\n+\n+\t\tstats->ierrors += rxq_stats.errors;\n+\t\trx_discards_pmd += rxq_stats.rx_discards;\n+\t\tdev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf;\n+\t}\n+\n+\t/* tx queue stats */\n+\tq_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?\n+\t\tnic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS;\n+\tfor (i = 0; i < q_num; i++) {\n+\t\ttxq = nic_dev->txqs[i];\n+\t\thinic_txq_get_stats(txq, &txq_stats);\n+\t\tstats->q_opackets[i] = txq_stats.packets;\n+\t\tstats->q_obytes[i] = txq_stats.bytes;\n+\t\tstats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs);\n+\t}\n+\n+\t/* vport stats */\n+\tstats->oerrors += vport_stats.tx_discard_vport;\n+\n+\tstats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd;\n+\n+\tstats->ipackets = (vport_stats.rx_unicast_pkts_vport +\n+\t\t\tvport_stats.rx_multicast_pkts_vport +\n+\t\t\tvport_stats.rx_broadcast_pkts_vport -\n+\t\t\trx_discards_pmd);\n+\n+\tstats->opackets = (vport_stats.tx_unicast_pkts_vport +\n+\t\t\tvport_stats.tx_multicast_pkts_vport +\n+\t\t\tvport_stats.tx_broadcast_pkts_vport);\n+\n+\tstats->ibytes = (vport_stats.rx_unicast_bytes_vport +\n+\t\t\tvport_stats.rx_multicast_bytes_vport +\n+\t\t\tvport_stats.rx_broadcast_bytes_vport);\n+\n+\tstats->obytes = (vport_stats.tx_unicast_bytes_vport +\n+\t\t\tvport_stats.tx_multicast_bytes_vport +\n+\t\t\tvport_stats.tx_broadcast_bytes_vport);\n+\treturn 0;\n+}\n+\n+/**\n+ * DPDK callback to clear device statistics.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ */\n+void hinic_dev_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tint qid;\n+\tstruct hinic_rxq\t*rxq = NULL;\n+\tstruct hinic_txq\t*txq = NULL;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\thinic_clear_vport_stats(nic_dev->hwdev);\n+\n+\tfor (qid = 0; qid < nic_dev->num_rq; qid++) {\n+\t\trxq = nic_dev->rxqs[qid];\n+\t\thinic_rxq_stats_reset(rxq);\n+\t}\n+\n+\tfor (qid = 0; qid < nic_dev->num_sq; qid++) {\n+\t\ttxq = nic_dev->txqs[qid];\n+\t\thinic_txq_stats_reset(txq);\n+\t}\n+}\n+\n+/**\n+ * DPDK callback to clear device extended statistics.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ **/\n+void hinic_dev_xstats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\thinic_dev_stats_reset(dev);\n+\n+\tif (hinic_func_type(nic_dev->hwdev) != TYPE_VF)\n+\t\thinic_clear_phy_port_stats(nic_dev->hwdev);\n+}\n+\n+static void hinic_gen_random_mac_addr(struct rte_ether_addr *mac_addr)\n+{\n+\tuint64_t random_value;\n+\n+\t/* Set Organizationally Unique Identifier (OUI) prefix */\n+\tmac_addr->addr_bytes[0] = 0x00;\n+\tmac_addr->addr_bytes[1] = 0x09;\n+\tmac_addr->addr_bytes[2] = 0xC0;\n+\t/* Force indication of locally assigned MAC address. */\n+\tmac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;\n+\t/* Generate the last 3 bytes of the MAC address with a random number. */\n+\trandom_value = rte_rand();\n+\tmemcpy(&mac_addr->addr_bytes[3], &random_value, 3);\n+}\n+\n+/**\n+ * Init mac_vlan table in NIC.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev =\n+\t\t\t\tHINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);\n+\tuint8_t addr_bytes[RTE_ETHER_ADDR_LEN];\n+\tu16 func_id = 0;\n+\tint rc = 0;\n+\n+\trc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tmemmove(eth_dev->data->mac_addrs->addr_bytes,\n+\t\taddr_bytes, RTE_ETHER_ADDR_LEN);\n+\n+\tif (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))\n+\t\thinic_gen_random_mac_addr(eth_dev->data->mac_addrs);\n+\n+\tfunc_id = hinic_global_func_id(nic_dev->hwdev);\n+\trc = hinic_set_mac(nic_dev->hwdev, eth_dev->data->mac_addrs->addr_bytes,\n+\t\t\t   0, func_id);\n+\tif (rc && rc != HINIC_PF_SET_VF_ALREADY)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Deinit mac_vlan table in NIC.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ *\n+ * @return\n+ *   0 on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev =\n+\t\t\t\tHINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);\n+\tint rc;\n+\tu16 func_id = 0;\n+\n+\tif (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))\n+\t\treturn;\n+\n+\tfunc_id = hinic_global_func_id(nic_dev->hwdev);\n+\trc = hinic_del_mac(nic_dev->hwdev,\n+\t\t\t   eth_dev->data->mac_addrs->addr_bytes,\n+\t\t\t   0, func_id);\n+\tif (rc && rc != HINIC_PF_SET_VF_ALREADY)\n+\t\tPMD_DRV_LOG(ERR, \"Delete mac table failed, dev_name: %s\",\n+\t\t\t    eth_dev->data->name);\n+}\n+\n+/**\n+ * DPDK callback to retrieve physical link information.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param wait_to_complete\n+ *   Wait for request completion.\n+ *\n+ * @return\n+ *   0 link status changed, -1 link status not changed\n+ */\n+int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n+{\n+#define CHECK_INTERVAL 10  /* 10ms */\n+#define MAX_REPEAT_TIME 100  /* 1s (100 * 10ms) in total */\n+\tint rc = HINIC_OK;\n+\tstruct rte_eth_link new_link, old_link;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tunsigned int rep_cnt = MAX_REPEAT_TIME;\n+\n+\tmemset(&old_link, 0, sizeof(old_link));\n+\tmemset(&new_link, 0, sizeof(new_link));\n+\trte_eth_linkstatus_get(dev, &old_link);\n+\n+\tdo {\n+\t\t/* Get link status information from hardware */\n+\t\trc = hinic_priv_get_dev_link_status(nic_dev, &new_link);\n+\t\tif (rc != HINIC_OK) {\n+\t\t\tnew_link.link_speed = ETH_SPEED_NUM_NONE;\n+\t\t\tnew_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n+\t\t\tPMD_DRV_LOG(ERR, \"Get link status failed\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (!wait_to_complete)\n+\t\t\tbreak;\n+\n+\t\trte_delay_ms(CHECK_INTERVAL);\n+\t} while (!new_link.link_status && rep_cnt--);\n+\n+out:\n+\t(void)rte_eth_linkstatus_set(dev, &new_link);\n+\n+\tif (old_link.link_status == new_link.link_status)\n+\t\treturn HINIC_ERROR;\n+\n+\tPMD_DRV_LOG(INFO, \"Device %s link status change from %s to %s\",\n+\t\t    nic_dev->proc_dev_name,\n+\t\t    (old_link.link_status ? \"UP\" : \"DOWN\"),\n+\t\t    (new_link.link_status ? \"UP\" : \"DOWN\"));\n+\n+\treturn HINIC_OK;\n+}\n+\n+/**\n+ * DPDK callback to enable promiscuous mode.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ */\n+void hinic_dev_promiscuous_enable(struct rte_eth_dev *dev)\n+{\n+\tint rc = HINIC_OK;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\tPMD_DRV_LOG(INFO, \"Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d\",\n+\t\t    nic_dev->proc_dev_name, dev->data->port_id,\n+\t\t    dev->data->promiscuous);\n+\n+\trc = hinic_set_dev_promiscuous(nic_dev, true);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(ERR, \"Enable promiscuous failed\");\n+}\n+\n+/**\n+ * DPDK callback to disable promiscuous mode.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ */\n+void hinic_dev_promiscuous_disable(struct rte_eth_dev *dev)\n+{\n+\tint rc = HINIC_OK;\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\n+\tPMD_DRV_LOG(INFO, \"Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d\",\n+\t\t    nic_dev->proc_dev_name, dev->data->port_id,\n+\t\t    dev->data->promiscuous);\n+\n+\trc = hinic_set_dev_promiscuous(nic_dev, false);\n+\tif (rc)\n+\t\tPMD_DRV_LOG(ERR, \"Disable promiscuous failed\");\n+}\n+\n+/**\n+ * DPDK callback to update the RSS hash key and RSS hash type.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param rss_conf\n+ *   RSS configuration data.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+int hinic_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t  struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tu8 tmpl_idx = nic_dev->rss_tmpl_idx;\n+\tu8 hashkey[HINIC_RSS_KEY_SIZE] = {0};\n+\tu8 prio_tc[HINIC_DCB_UP_MAX] = {0};\n+\tu64 rss_hf = rss_conf->rss_hf;\n+\tstruct nic_rss_type rss_type = {0};\n+\tint err = 0;\n+\n+\tPMD_DRV_LOG(INFO, \"rss info, rss_flag:0x%x, rss_key_len:%d, rss_hf:%lu, tmpl_idx:%d\",\n+\t\t    nic_dev->flags, rss_conf->rss_key_len, rss_hf, tmpl_idx);\n+\n+\tif (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {\n+\t\tPMD_DRV_LOG(INFO, \"RSS is not enabled\");\n+\t\treturn HINIC_OK;\n+\t}\n+\n+\tif (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid rss key, rss_key_len:%d\",\n+\t\t\t    rss_conf->rss_key_len);\n+\t\treturn HINIC_ERROR;\n+\t}\n+\n+\tif (rss_conf->rss_key) {\n+\t\tmemcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len);\n+\t\terr = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx,\n+\t\t\t\t\t\t hashkey);\n+\t\tif (err) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Set rss template table failed\");\n+\t\t\tgoto disable_rss;\n+\t\t}\n+\t}\n+\n+\trss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0;\n+\trss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0;\n+\trss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0;\n+\trss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0;\n+\trss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0;\n+\trss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0;\n+\trss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0;\n+\trss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0;\n+\n+\terr = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Set rss type table failed\");\n+\t\tgoto disable_rss;\n+\t}\n+\n+\treturn 0;\n+\n+disable_rss:\n+\tmemset(prio_tc, 0, sizeof(prio_tc));\n+\t(void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);\n+\treturn err;\n+}\n+\n+/**\n+ * DPDK callback to get the RSS hash configuration.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param rss_conf\n+ *   RSS configuration data.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+int hinic_rss_conf_get(struct rte_eth_dev *dev,\n+\t\t       struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tu8 tmpl_idx = nic_dev->rss_tmpl_idx;\n+\tu8 hashkey[HINIC_RSS_KEY_SIZE] = {0};\n+\tstruct nic_rss_type rss_type = {0};\n+\tint err;\n+\n+\tif (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {\n+\t\tPMD_DRV_LOG(INFO, \"RSS is not enabled\");\n+\t\treturn HINIC_ERROR;\n+\t}\n+\n+\terr = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (rss_conf->rss_key &&\n+\t    rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) {\n+\t\tmemcpy(rss_conf->rss_key, hashkey, sizeof(hashkey));\n+\t\trss_conf->rss_key_len = sizeof(hashkey);\n+\t}\n+\n+\terr = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type);\n+\tif (err)\n+\t\treturn err;\n+\n+\trss_conf->rss_hf = 0;\n+\trss_conf->rss_hf |=  rss_type.ipv4 ?\n+\t\t(ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0;\n+\trss_conf->rss_hf |=  rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0;\n+\trss_conf->rss_hf |=  rss_type.ipv6 ?\n+\t\t(ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0;\n+\trss_conf->rss_hf |=  rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0;\n+\trss_conf->rss_hf |=  rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0;\n+\trss_conf->rss_hf |=  rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0;\n+\trss_conf->rss_hf |=  rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0;\n+\trss_conf->rss_hf |=  rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0;\n+\n+\treturn HINIC_OK;\n+}\n+\n+/**\n+ * DPDK callback to update the RETA indirection table.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param reta_conf\n+ *   Pointer to RETA configuration structure array.\n+ * @param reta_size\n+ *   Size of the RETA table.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+int hinic_rss_indirtbl_update(struct rte_eth_dev *dev,\n+\t\t\t      struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t      uint16_t reta_size)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tu8 tmpl_idx = nic_dev->rss_tmpl_idx;\n+\tu8 prio_tc[HINIC_DCB_UP_MAX] = {0};\n+\tu32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};\n+\tint err = 0;\n+\tu16 i = 0;\n+\tu16 idx, shift;\n+\n+\tPMD_DRV_LOG(INFO, \"Update indirect table, rss_flag:0x%x, reta_size:%d, tmpl_idx:%d\",\n+\t\t    nic_dev->flags, reta_size, tmpl_idx);\n+\n+\tif (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG))\n+\t\treturn HINIC_OK;\n+\n+\tif (reta_size != NIC_RSS_INDIR_SIZE) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid reta size, reta_size:%d\", reta_size);\n+\t\treturn HINIC_ERROR;\n+\t}\n+\n+\terr = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* update rss indir_tbl */\n+\tfor (i = 0; i < reta_size; i++) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tif (reta_conf[idx].mask & (1ULL << shift))\n+\t\t\tindirtbl[i] = reta_conf[idx].reta[shift];\n+\t}\n+\n+\tfor (i = 0 ; i < reta_size; i++) {\n+\t\tif (indirtbl[i] >= nic_dev->num_rq) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid reta entry, index:%d, num_rq:%d\",\n+\t\t\t\t    i, nic_dev->num_rq);\n+\t\t\tgoto disable_rss;\n+\t\t}\n+\t}\n+\n+\terr = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);\n+\tif (err)\n+\t\tgoto disable_rss;\n+\n+\tnic_dev->rss_indir_flag = true;\n+\n+\treturn 0;\n+\n+disable_rss:\n+\tmemset(prio_tc, 0, sizeof(prio_tc));\n+\t(void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);\n+\n+\treturn HINIC_ERROR;\n+}\n+\n+\n+/**\n+ * DPDK callback to get the RETA indirection table.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param reta_conf\n+ *   Pointer to RETA configuration structure array.\n+ * @param reta_size\n+ *   Size of the RETA table.\n+ *\n+ * @return\n+ *   0 on success, negative error value otherwise.\n+ */\n+int hinic_rss_indirtbl_query(struct rte_eth_dev *dev,\n+\t\t\t     struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t     uint16_t reta_size)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tu8 tmpl_idx = nic_dev->rss_tmpl_idx;\n+\tint err = 0;\n+\tu32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};\n+\tu16 idx, shift;\n+\tu16 i = 0;\n+\n+\tif (reta_size != NIC_RSS_INDIR_SIZE) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid reta size, reta_size:%d\", reta_size);\n+\t\treturn HINIC_ERROR;\n+\t}\n+\n+\terr = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"Get rss indirect table failed, error:%d\",\n+\t\t\t    err);\n+\t\treturn err;\n+\t}\n+\n+\tfor (i = 0; i < reta_size; i++) {\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tif (reta_conf[idx].mask & (1ULL << shift))\n+\t\t\treta_conf[idx].reta[shift] = (uint16_t)indirtbl[i];\n+\t}\n+\n+\treturn HINIC_OK;\n+}\n+\n+/**\n+ * DPDK callback to get extended device statistics.\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device.\n+ * @param xstats\n+ *   Pointer to rte extended stats table.\n+ * @param n\n+ *   The size of the stats table.\n+ *\n+ * @return\n+ *   Number of extended stats on success and stats is filled,\n+ *   negative error value otherwise.\n+ */\n+int hinic_dev_xstats_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_xstat *xstats,\n+\t\t\t unsigned int n)\n+{\n+\tu16 qid = 0;\n+\tu32 i;\n+\tint err, count;\n+\tstruct hinic_nic_dev *nic_dev;\n+\tstruct hinic_phy_port_stats port_stats;\n+\tstruct hinic_vport_stats vport_stats;\n+\tstruct hinic_rxq\t*rxq = NULL;\n+\tstruct hinic_rxq_stats rxq_stats;\n+\tstruct hinic_txq\t*txq = NULL;\n+\tstruct hinic_txq_stats txq_stats;\n+\n+\tnic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tcount = hinic_xstats_calc_num(nic_dev);\n+\tif ((int)n < count)\n+\t\treturn count;\n+\n+\tcount = 0;\n+\n+\t/* Get stats from hinic_rxq_stats */\n+\tfor (qid = 0; qid < nic_dev->num_rq; qid++) {\n+\t\trxq = nic_dev->rxqs[qid];\n+\t\thinic_rxq_get_stats(rxq, &rxq_stats);\n+\n+\t\tfor (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\t*(uint64_t *)(((char *)&rxq_stats) +\n+\t\t\t\thinic_rxq_stats_strings[i].offset);\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\t/* Get stats from hinic_txq_stats */\n+\tfor (qid = 0; qid < nic_dev->num_sq; qid++) {\n+\t\ttxq = nic_dev->txqs[qid];\n+\t\thinic_txq_get_stats(txq, &txq_stats);\n+\n+\t\tfor (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {\n+\t\t\txstats[count].value =\n+\t\t\t\t*(uint64_t *)(((char *)&txq_stats) +\n+\t\t\t\thinic_txq_stats_strings[i].offset);\n+\t\t\txstats[count].id = count;\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\t/* Get stats from hinic_vport_stats */\n+\terr = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);\n+\tif (err)\n+\t\treturn err;\n+\n+\tfor (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {\n+\t\txstats[count].value =\n+\t\t\t*(uint64_t *)(((char *)&vport_stats) +\n+\t\t\thinic_vport_stats_strings[i].offset);\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\t/* Get stats from hinic_phy_port_stats */\n+\terr = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats);\n+\tif (err)\n+\t\treturn err;\n+\n+\tfor (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {\n+\t\txstats[count].value = *(uint64_t *)(((char *)&port_stats) +\n+\t\t\t\thinic_phyport_stats_strings[i].offset);\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n+/**\n+ * DPDK callback to retrieve names of extended device statistics\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param xstats_names\n+ *   Buffer to insert names into.\n+ *\n+ * @return\n+ *   Number of xstats names.\n+ */\n+int hinic_dev_xstats_get_names(struct rte_eth_dev *dev,\n+\t\t\t       struct rte_eth_xstat_name *xstats_names,\n+\t\t\t       __rte_unused unsigned int limit)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tint count = 0;\n+\tu16 i = 0, q_num;\n+\n+\tif (xstats_names == NULL)\n+\t\treturn hinic_xstats_calc_num(nic_dev);\n+\n+\t/* get pmd rxq stats */\n+\tfor (q_num = 0; q_num < nic_dev->num_rq; q_num++) {\n+\t\tfor (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t\t \"rxq%d_%s_pmd\",\n+\t\t\t\t q_num, hinic_rxq_stats_strings[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\t/* get pmd txq stats */\n+\tfor (q_num = 0; q_num < nic_dev->num_sq; q_num++) {\n+\t\tfor (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t\t \"txq%d_%s_pmd\",\n+\t\t\t\t q_num, hinic_txq_stats_strings[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\t/* get vport stats */\n+\tfor (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {\n+\t\tsnprintf(xstats_names[count].name,\n+\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t \"%s\",\n+\t\t\t hinic_vport_stats_strings[i].name);\n+\t\tcount++;\n+\t}\n+\n+\t/* get phy port stats */\n+\tfor (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {\n+\t\tsnprintf(xstats_names[count].name,\n+\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t \"%s\",\n+\t\t\t hinic_phyport_stats_strings[i].name);\n+\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n+/**\n+ * DPDK callback to get fw version\n+ *\n+ * @param dev\n+ *   Pointer to Ethernet device structure.\n+ * @param fw_version\n+ *   Pointer to fw version structure.\n+ * @param fw_size\n+ *   Size of fw version.\n+ *\n+ * @return\n+ *   Number of xstats names.\n+ */\n+int\n+hinic_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tstruct hinic_fw_version fw_ver;\n+\tint ret;\n+\n+\tmemset(&fw_ver, 0, sizeof(fw_ver));\n+\tret = hinic_get_fw_version(nic_dev->hwdev, &fw_ver);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = snprintf(fw_version, fw_size, \"%s\", fw_ver.microcode_ver);\n+\tret += 1; /* add the size of '\\0' */\n+\tif (fw_size < (u32)ret)\n+\t\treturn ret;\n+\telse\n+\t\treturn 0;\n+}\n+\n RTE_INIT(hinic_init_log)\n {\n \thinic_logtype = rte_log_register(\"pmd.net.hinic\");\ndiff --git a/drivers/net/hinic/rte_pmd_hinic_version.map b/drivers/net/hinic/rte_pmd_hinic_version.map\nnew file mode 100644\nindex 000000000..9a61188cd\n--- /dev/null\n+++ b/drivers/net/hinic/rte_pmd_hinic_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.08 {\n+\n+\tlocal: *;\n+};\n",
    "prefixes": [
        "v4",
        "11/11"
    ]
}